Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	550196803	10396	0	0
ctrl_rd_A	550196803	1001	0	0
host_fifo_config_rd_A	550196803	4539	0	0
host_timeout_ctrl_rd_A	550196803	681	0	0
intr_enable_rd_A	550196803	3383	0	0
ovrd_rd_A	550196803	1931	0	0
target_fifo_config_rd_A	550196803	819	0	0
target_id_rd_A	550196803	1022	0	0
timeout_ctrl_rd_A	550196803	795	0	0
timing0_rd_A	550196803	796	0	0
timing1_rd_A	550196803	740	0	0
timing2_rd_A	550196803	773	0	0
timing3_rd_A	550196803	900	0	0
timing4_rd_A	550196803	775	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550196803	10396	0	0
T58	7716	3	0	0
T59	2293	281	0	0
T60	2082	26	0	0
T61	2539	116	0	0
T62	7786	422	0	0
T63	13205	690	0	0
T64	10074	5	0	0
T68	4176	4	0	0
T75	3915	192	0	0
T91	5547	3	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550196803	1001	0	0
T62	7786	10	0	0
T63	13205	19	0	0
T73	6683	82	0	0
T76	7343	63	0	0
T98	1460	15	0	0
T102	2190	27	0	0
T112	4938	44	0	0
T121	3616	2	0	0
T122	1720	10	0	0
T123	7402	24	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550196803	4539	0	0
T31	0	173	0	0
T124	213062	96	0	0
T125	598262	167	0	0
T126	0	136	0	0
T127	0	277	0	0
T128	0	226	0	0
T129	0	89	0	0
T130	0	168	0	0
T131	0	144	0	0
T132	0	167	0	0
T133	29481	0	0	0
T134	169934	0	0	0
T135	108988	0	0	0
T136	63751	0	0	0
T137	14503	0	0	0
T138	804646	0	0	0
T139	254063	0	0	0
T140	161532	0	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550196803	681	0	0
T62	7786	2	0	0
T63	13205	29	0	0
T69	3702	4	0	0
T73	6683	36	0	0
T75	3915	2	0	0
T76	7343	28	0	0
T98	1460	4	0	0
T112	4938	58	0	0
T121	3616	32	0	0
T122	1720	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550196803	3383	0	0
T31	0	48	0	0
T51	183454	18	0	0
T62	0	12	0	0
T63	0	10	0	0
T112	0	60	0	0
T141	0	39	0	0
T142	0	23	0	0
T143	0	22	0	0
T144	0	29	0	0
T145	0	5	0	0
T146	57951	0	0	0
T147	1042	0	0	0
T148	620425	0	0	0
T149	328890	0	0	0
T150	94520	0	0	0
T151	905749	0	0	0
T152	327684	0	0	0
T153	220426	0	0	0
T154	824529	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550196803	1931	0	0
T4	1469	51	0	0
T37	7714	0	0	0
T89	0	36	0	0
T155	0	50	0	0
T156	0	71	0	0
T157	0	79	0	0
T158	0	55	0	0
T159	0	45	0	0
T160	0	51	0	0
T161	0	51	0	0
T162	0	43	0	0
T163	260703	0	0	0
T164	15910	0	0	0
T165	258273	0	0	0
T166	111450	0	0	0
T167	37475	0	0	0
T168	29308	0	0	0
T169	475608	0	0	0
T170	43366	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550196803	819	0	0
T62	7786	18	0	0
T63	13205	35	0	0
T73	6683	65	0	0
T76	7343	56	0	0
T98	1460	8	0	0
T102	2190	10	0	0
T112	4938	23	0	0
T121	3616	28	0	0
T122	1720	13	0	0
T123	7402	10	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550196803	1022	0	0
T62	7786	10	0	0
T63	13205	22	0	0
T69	3702	3	0	0
T73	6683	68	0	0
T76	7343	76	0	0
T98	1460	1	0	0
T112	4938	28	0	0
T121	3616	11	0	0
T122	1720	14	0	0
T123	7402	14	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550196803	795	0	0
T62	7786	7	0	0
T63	13205	30	0	0
T73	6683	46	0	0
T75	3915	2	0	0
T76	7343	67	0	0
T98	1460	15	0	0
T112	4938	27	0	0
T121	3616	17	0	0
T122	1720	14	0	0
T123	7402	18	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550196803	796	0	0
T62	7786	10	0	0
T63	13205	28	0	0
T69	3702	9	0	0
T73	6683	62	0	0
T75	3915	9	0	0
T76	7343	61	0	0
T102	2190	8	0	0
T112	4938	45	0	0
T121	3616	45	0	0
T122	1720	19	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550196803	740	0	0
T62	7786	6	0	0
T63	13205	14	0	0
T69	3702	6	0	0
T73	6683	65	0	0
T76	7343	57	0	0
T98	1460	3	0	0
T112	4938	41	0	0
T121	3616	6	0	0
T122	1720	16	0	0
T123	7402	3	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550196803	773	0	0
T62	7786	9	0	0
T63	13205	13	0	0
T73	6683	76	0	0
T76	7343	50	0	0
T98	1460	5	0	0
T102	2190	9	0	0
T112	4938	17	0	0
T121	3616	38	0	0
T122	1720	11	0	0
T123	7402	3	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550196803	900	0	0
T62	7786	5	0	0
T63	13205	49	0	0
T69	3702	2	0	0
T73	6683	58	0	0
T76	7343	69	0	0
T98	1460	14	0	0
T102	2190	5	0	0
T112	4938	64	0	0
T121	3616	40	0	0
T122	1720	2	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550196803	775	0	0
T62	7786	10	0	0
T63	13205	16	0	0
T73	6683	35	0	0
T76	7343	53	0	0
T98	1460	10	0	0
T102	2190	23	0	0
T112	4938	25	0	0
T121	3616	7	0	0
T122	1720	17	0	0
T123	7402	34	0	0