Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	24308	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

38427

1

T1

196

T2

230

T3

11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	32477	1			T1	48		T2	62		T3	11
values[0x0]	14872	1			T1	73		T2	78		T3	5
values[0x1]	15386	1			T1	101		T2	108		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	17336	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

45399

1

T1

212

T2

240

T3

11

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	215	1			T1	1		T2	2		T4	5
valid_sources[0x01]	388	1			T1	2		T8	1		T4	7
valid_sources[0x02]	201	1			T2	1		T4	5		T13	1
valid_sources[0x03]	261	1			T1	1		T4	5		T10	1
valid_sources[0x04]	168	1			T4	6		T13	1		T14	3
valid_sources[0x05]	345	1			T4	3		T10	6		T14	1
valid_sources[0x06]	315	1			T1	2		T4	5		T14	2
valid_sources[0x07]	303	1			T4	1		T9	1		T6	10
valid_sources[0x08]	333	1			T1	1		T2	2		T4	5
valid_sources[0x09]	302	1			T2	1		T4	16		T10	1
valid_sources[0x0a]	247	1			T2	2		T4	3		T10	1
valid_sources[0x0b]	428	1			T2	1		T4	1		T13	1
valid_sources[0x0c]	331	1			T3	1		T4	1		T10	7
valid_sources[0x0d]	306	1			T2	1		T4	3		T13	3
valid_sources[0x0e]	234	1			T1	2		T2	1		T4	6
valid_sources[0x0f]	272	1			T4	8		T6	11		T14	3
valid_sources[0x10]	504	1			T1	2		T2	2		T4	10
valid_sources[0x11]	204	1			T1	1		T2	1		T8	1
valid_sources[0x12]	536	1			T2	2		T4	9		T12	1
valid_sources[0x13]	201	1			T13	1		T10	3		T6	2
valid_sources[0x14]	368	1			T2	3		T4	3		T10	5
valid_sources[0x15]	235	1			T1	1		T4	6		T9	1
valid_sources[0x16]	219	1			T1	2		T8	1		T4	2
valid_sources[0x17]	250	1			T1	1		T4	4		T13	1
valid_sources[0x18]	256	1			T1	1		T4	2		T13	4
valid_sources[0x19]	204	1			T1	2		T8	2		T4	4
valid_sources[0x1a]	255	1			T1	5		T2	1		T4	3
valid_sources[0x1b]	226	1			T1	1		T2	2		T4	1
valid_sources[0x1c]	209	1			T1	1		T2	1		T4	3
valid_sources[0x1d]	184	1			T2	1		T4	8		T12	1
valid_sources[0x1e]	150	1			T2	2		T4	6		T13	2
valid_sources[0x1f]	203	1			T1	5		T2	1		T4	5
valid_sources[0x20]	204	1			T2	2		T8	4		T4	3
valid_sources[0x21]	232	1			T1	3		T2	2		T10	1
valid_sources[0x22]	156	1			T1	2		T2	2		T8	1
valid_sources[0x23]	199	1			T1	1		T2	1		T8	1
valid_sources[0x24]	187	1			T2	1		T4	3		T13	2
valid_sources[0x25]	206	1			T1	4		T2	1		T4	1
valid_sources[0x26]	379	1			T2	1		T4	4		T13	2
valid_sources[0x27]	164	1			T4	6		T9	1		T13	1
valid_sources[0x28]	180	1			T1	3		T4	3		T12	1
valid_sources[0x29]	185	1			T2	1		T7	20		T4	5
valid_sources[0x2a]	200	1			T1	1		T3	1		T4	4
valid_sources[0x2b]	218	1			T1	2		T4	5		T13	1
valid_sources[0x2c]	361	1			T1	2		T2	1		T4	1
valid_sources[0x2d]	230	1			T1	1		T2	2		T4	5
valid_sources[0x2e]	217	1			T2	1		T4	3		T10	1
valid_sources[0x2f]	217	1			T2	2		T4	6		T5	39
valid_sources[0x30]	162	1			T4	6		T6	4		T14	1
valid_sources[0x31]	177	1			T4	7		T10	4		T14	1
valid_sources[0x32]	216	1			T2	2		T4	5		T14	1
valid_sources[0x33]	223	1			T2	1		T4	5		T12	1
valid_sources[0x34]	207	1			T2	2		T8	1		T4	5
valid_sources[0x35]	176	1			T1	1		T4	7		T13	3
valid_sources[0x36]	208	1			T2	1		T4	2		T13	1
valid_sources[0x37]	223	1			T1	1		T4	3		T13	1
valid_sources[0x38]	174	1			T1	1		T8	1		T4	8
valid_sources[0x39]	379	1			T1	1		T13	2		T5	12
valid_sources[0x3a]	228	1			T1	1		T2	1		T4	1
valid_sources[0x3b]	200	1			T1	4		T2	2		T8	1
valid_sources[0x3c]	229	1			T2	3		T8	1		T4	9
valid_sources[0x3d]	357	1			T1	2		T2	2		T4	7
valid_sources[0x3e]	220	1			T2	3		T4	2		T9	1
valid_sources[0x3f]	179	1			T4	7		T13	1		T10	2
valid_sources[0x40]	164	1			T2	3		T4	5		T6	13
valid_sources[0x41]	162	1			T2	2		T8	1		T14	3
valid_sources[0x42]	245	1			T1	6		T2	2		T4	3
valid_sources[0x43]	342	1			T8	1		T4	1		T13	1
valid_sources[0x44]	184	1			T4	4		T10	1		T6	5
valid_sources[0x45]	209	1			T1	1		T2	1		T4	4
valid_sources[0x46]	192	1			T4	3		T14	4		T15	2
valid_sources[0x47]	343	1			T4	1		T5	21		T6	16
valid_sources[0x48]	505	1			T1	1		T2	1		T4	1
valid_sources[0x49]	202	1			T1	2		T2	1		T4	2
valid_sources[0x4a]	223	1			T2	1		T4	7		T13	2
valid_sources[0x4b]	309	1			T1	3		T4	6		T5	6
valid_sources[0x4c]	293	1			T4	5		T10	2		T14	2
valid_sources[0x4d]	230	1			T2	1		T4	12		T13	1
valid_sources[0x4e]	250	1			T2	1		T3	7		T4	6
valid_sources[0x4f]	160	1			T2	1		T3	1		T4	3
valid_sources[0x50]	199	1			T1	1		T2	2		T4	5
valid_sources[0x51]	239	1			T2	1		T4	4		T9	2
valid_sources[0x52]	214	1			T4	2		T13	1		T10	1
valid_sources[0x53]	255	1			T1	3		T2	1		T4	6
valid_sources[0x54]	183	1			T2	2		T4	9		T6	3
valid_sources[0x55]	196	1			T4	4		T13	3		T14	5
valid_sources[0x56]	181	1			T3	1		T4	7		T10	2
valid_sources[0x57]	229	1			T1	1		T4	3		T12	1
valid_sources[0x58]	209	1			T1	1		T4	4		T9	1
valid_sources[0x59]	228	1			T4	5		T10	7		T14	7
valid_sources[0x5a]	331	1			T2	3		T4	1		T10	8
valid_sources[0x5b]	232	1			T2	1		T4	4		T9	1
valid_sources[0x5c]	337	1			T13	2		T10	1		T5	19
valid_sources[0x5d]	255	1			T1	2		T4	1		T13	2
valid_sources[0x5e]	207	1			T1	3		T2	2		T4	5
valid_sources[0x5f]	311	1			T4	6		T10	1		T14	3
valid_sources[0x60]	235	1			T4	9		T5	11		T6	8
valid_sources[0x61]	254	1			T4	6		T9	1		T13	1
valid_sources[0x62]	301	1			T1	1		T2	1		T4	9
valid_sources[0x63]	347	1			T1	2		T2	1		T4	3
valid_sources[0x64]	215	1			T2	1		T4	9		T5	7
valid_sources[0x65]	213	1			T8	1		T4	1		T13	2
valid_sources[0x66]	312	1			T1	2		T4	7		T14	6
valid_sources[0x67]	282	1			T2	1		T4	10		T12	2
valid_sources[0x68]	221	1			T2	1		T8	1		T4	10
valid_sources[0x69]	216	1			T1	3		T2	2		T4	5
valid_sources[0x6a]	364	1			T3	1		T4	6		T6	1
valid_sources[0x6b]	522	1			T2	1		T4	4		T10	3
valid_sources[0x6c]	603	1			T4	5		T13	1		T10	3
valid_sources[0x6d]	263	1			T2	2		T4	7		T13	2
valid_sources[0x6e]	219	1			T1	2		T2	1		T4	6
valid_sources[0x6f]	192	1			T2	3		T4	5		T9	1
valid_sources[0x70]	319	1			T2	2		T4	2		T13	7
valid_sources[0x71]	256	1			T8	1		T4	2		T13	2
valid_sources[0x72]	205	1			T2	4		T4	5		T10	2
valid_sources[0x73]	481	1			T4	2		T10	2		T5	55
valid_sources[0x74]	199	1			T1	1		T2	1		T8	1
valid_sources[0x75]	153	1			T1	2		T2	1		T4	4
valid_sources[0x76]	219	1			T1	1		T2	3		T4	7
valid_sources[0x77]	253	1			T1	2		T4	1		T10	1
valid_sources[0x78]	219	1			T2	1		T8	2		T4	5
valid_sources[0x79]	281	1			T1	2		T2	2		T4	7
valid_sources[0x7a]	199	1			T1	3		T2	2		T4	5
valid_sources[0x7b]	224	1			T2	3		T4	12		T13	1
valid_sources[0x7c]	219	1			T4	10		T13	1		T10	1
valid_sources[0x7d]	251	1			T1	1		T4	5		T9	1
valid_sources[0x7e]	199	1			T1	1		T2	1		T4	8
valid_sources[0x7f]	219	1			T1	1		T2	2		T8	1
valid_sources[0x80]	221	1			T2	2		T4	4		T13	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14351

1

T1

45

T2

62

T3

5

values[0x0]

all_enables

biggest_size

12389

1

T1

72

T2

77

T3

2

values[0x1]

all_enables

biggest_size

11687

1

T1

79

T2

91

T3

4