Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
33.33	0.00	0.00	100.00				dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	622189	9551	0	0
ctrl_rd_A	622189	1976	0	0
host_fifo_config_rd_A	622189	1846	0	0
host_timeout_ctrl_rd_A	622189	1554	0	0
intr_enable_rd_A	622189	5671	0	0
ovrd_rd_A	622189	1934	0	0
target_fifo_config_rd_A	622189	1629	0	0
target_id_rd_A	622189	2275	0	0
timeout_ctrl_rd_A	622189	1870	0	0
timing0_rd_A	622189	1806	0	0
timing1_rd_A	622189	1758	0	0
timing2_rd_A	622189	1904	0	0
timing3_rd_A	622189	1663	0	0
timing4_rd_A	622189	1795	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622189	9551	0	0
T1	3080	319	0	0
T2	2119	146	0	0
T3	1673	0	0	0
T4	11631	4	0	0
T5	0	7	0	0
T7	997	0	0	0
T8	1566	0	0	0
T9	1592	0	0	0
T11	813	0	0	0
T12	1195	0	0	0
T13	8162	545	0	0
T14	0	769	0	0
T15	0	4	0	0
T16	0	6	0	0
T17	0	364	0	0
T21	0	3	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622189	1976	0	0
T4	11631	53	0	0
T5	11631	140	0	0
T6	4995	22	0	0
T9	1592	0	0	0
T10	1913	0	0	0
T11	813	0	0	0
T12	1195	0	0	0
T13	8162	7	0	0
T14	4580	0	0	0
T15	9809	0	0	0
T18	0	9	0	0
T20	0	30	0	0
T21	0	17	0	0
T26	0	29	0	0
T27	0	1	0	0
T35	0	136	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622189	1846	0	0
T4	11631	86	0	0
T5	11631	120	0	0
T6	4995	26	0	0
T9	1592	0	0	0
T10	1913	0	0	0
T11	813	0	0	0
T12	1195	0	0	0
T13	8162	15	0	0
T14	4580	0	0	0
T15	9809	0	0	0
T18	0	26	0	0
T20	0	19	0	0
T21	0	19	0	0
T26	0	5	0	0
T27	0	35	0	0
T35	0	119	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622189	1554	0	0
T4	11631	49	0	0
T5	11631	60	0	0
T6	4995	68	0	0
T9	1592	0	0	0
T10	1913	0	0	0
T11	813	0	0	0
T12	1195	0	0	0
T13	8162	25	0	0
T14	4580	0	0	0
T15	9809	0	0	0
T18	0	38	0	0
T20	0	12	0	0
T21	0	29	0	0
T26	0	4	0	0
T27	0	42	0	0
T35	0	81	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622189	5671	0	0
T4	11631	431	0	0
T5	11631	727	0	0
T6	4995	82	0	0
T7	997	18	0	0
T8	1566	0	0	0
T9	1592	0	0	0
T10	1913	0	0	0
T11	813	0	0	0
T12	1195	10	0	0
T13	8162	0	0	0
T18	0	18	0	0
T20	0	19	0	0
T21	0	154	0	0
T60	0	25	0	0
T61	0	32	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622189	1934	0	0
T4	11631	97	0	0
T5	11631	116	0	0
T6	4995	28	0	0
T9	1592	0	0	0
T10	1913	0	0	0
T11	813	0	0	0
T12	1195	0	0	0
T13	8162	16	0	0
T14	4580	0	0	0
T15	9809	0	0	0
T18	0	11	0	0
T20	0	29	0	0
T21	0	47	0	0
T26	0	20	0	0
T27	0	23	0	0
T35	0	182	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622189	1629	0	0
T4	11631	67	0	0
T5	11631	126	0	0
T6	4995	48	0	0
T9	1592	0	0	0
T10	1913	0	0	0
T11	813	0	0	0
T12	1195	0	0	0
T13	8162	15	0	0
T14	4580	0	0	0
T15	9809	0	0	0
T18	0	27	0	0
T20	0	23	0	0
T21	0	20	0	0
T26	0	12	0	0
T27	0	10	0	0
T35	0	83	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622189	2275	0	0
T4	11631	85	0	0
T5	11631	228	0	0
T6	4995	43	0	0
T9	1592	0	0	0
T10	1913	0	0	0
T11	813	0	0	0
T12	1195	0	0	0
T13	8162	14	0	0
T14	4580	0	0	0
T15	9809	0	0	0
T18	0	7	0	0
T20	0	30	0	0
T21	0	33	0	0
T26	0	30	0	0
T27	0	26	0	0
T35	0	146	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622189	1870	0	0
T4	11631	42	0	0
T5	11631	150	0	0
T6	4995	63	0	0
T9	1592	0	0	0
T10	1913	0	0	0
T11	813	0	0	0
T12	1195	0	0	0
T13	8162	0	0	0
T14	4580	0	0	0
T15	9809	0	0	0
T18	0	29	0	0
T20	0	33	0	0
T21	0	27	0	0
T26	0	9	0	0
T27	0	20	0	0
T29	0	107	0	0
T35	0	95	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622189	1806	0	0
T4	11631	59	0	0
T5	11631	117	0	0
T6	4995	85	0	0
T9	1592	0	0	0
T10	1913	0	0	0
T11	813	0	0	0
T12	1195	0	0	0
T13	8162	25	0	0
T14	4580	0	0	0
T15	9809	0	0	0
T18	0	22	0	0
T20	0	8	0	0
T21	0	42	0	0
T26	0	15	0	0
T27	0	1	0	0
T35	0	104	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622189	1758	0	0
T4	11631	48	0	0
T5	11631	111	0	0
T6	4995	50	0	0
T9	1592	0	0	0
T10	1913	0	0	0
T11	813	0	0	0
T12	1195	0	0	0
T13	8162	5	0	0
T14	4580	0	0	0
T15	9809	0	0	0
T18	0	12	0	0
T20	0	16	0	0
T21	0	53	0	0
T26	0	18	0	0
T27	0	22	0	0
T35	0	116	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622189	1904	0	0
T4	11631	58	0	0
T5	11631	106	0	0
T6	4995	31	0	0
T9	1592	0	0	0
T10	1913	0	0	0
T11	813	0	0	0
T12	1195	0	0	0
T13	8162	8	0	0
T14	4580	0	0	0
T15	9809	0	0	0
T18	0	38	0	0
T20	0	27	0	0
T21	0	45	0	0
T26	0	12	0	0
T27	0	25	0	0
T35	0	153	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622189	1663	0	0
T4	11631	49	0	0
T5	11631	112	0	0
T6	4995	62	0	0
T9	1592	0	0	0
T10	1913	0	0	0
T11	813	0	0	0
T12	1195	0	0	0
T13	8162	11	0	0
T14	4580	0	0	0
T15	9809	0	0	0
T18	0	16	0	0
T20	0	18	0	0
T21	0	38	0	0
T26	0	12	0	0
T27	0	35	0	0
T35	0	103	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622189	1795	0	0
T4	11631	67	0	0
T5	11631	106	0	0
T6	4995	64	0	0
T9	1592	0	0	0
T10	1913	0	0	0
T11	813	0	0	0
T12	1195	0	0	0
T13	8162	0	0	0
T14	4580	0	0	0
T15	9809	0	0	0
T18	0	35	0	0
T20	0	12	0	0
T21	0	26	0	0
T26	0	22	0	0
T27	0	6	0	0
T29	0	111	0	0
T35	0	149	0	0