Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

151794

1

T3

95

T12

1088

T17

85

ack

13632

1

T3

1

T12

34

T17

1

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	611	1			T12	3		T13	1		T11	1
high	34114	1			T3	21		T12	224		T17	20
med	61660	1			T3	43		T12	458		T17	34
sml	68382	1			T3	32		T12	432		T17	32
all_zero	659	1			T12	5		T27	3		T28	1

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

82364

1

T3

57

T12

540

T17

39

auto[1]

83062

1

T3

39

T12

582

T17

47

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

113529

1

T3

60

T12

767

T17

60

auto[1]

51897

1

T3

36

T12

355

T17

26

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

158339

1

T3

96

T12

1106

T17

86

auto[1]

7087

1

T12

16

T13

14

T10

26

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

156411

1

T3

95

T12

1089

T17

85

auto[1]

9015

1

T3

1

T12

33

T17

1

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

157115

1

T3

95

T12

1090

T17

85

auto[1]

8311

1

T3

1

T12

32

T17

1

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

82364

1

T3

57

T12

540

T17

39

auto[1]

83062

1

T3

39

T12

582

T17

47

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

113529

1

T3

60

T12

767

T17

60

auto[1]

51897

1

T3

36

T12

355

T17

26

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

158339

1

T3

96

T12

1106

T17

86

auto[1]

7087

1

T12

16

T13

14

T10

26

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

156411

1

T3

95

T12

1089

T17

85

auto[1]

9015

1

T3

1

T12

33

T17

1

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

157115

1

T3

95

T12

1090

T17

85

auto[1]

8311

1

T3

1

T12

32

T17

1

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

5

1

T202

1

T71

1

T203

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

1

1

T140

1

-

-

-

-

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

5

1

T204

1

T153

1

T205

1

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

268

1

T12

2

T13

1

T206

2

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

129

1

T12

1

T13

1

T22

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

144

1

T12

2

T22

2

T69

2

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

490

1

T12

6

T13

3

T27

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

218

1

T12

1

T13

1

T22

3

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

257

1

T12

2

T27

1

T206

3

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

464

1

T12

3

T13

2

T21

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

242

1

T12

4

T13

2

T206

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

254

1

T13

2

T206

1

T22

2

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

8

1

T144

1

T207

1

T208

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

2

1

T209

1

T210

1

-

-

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

3

1

T173

1

T211

1

T212

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	48475	1			T3	37		T12	328		T17	28
write_address_byte	9015	1			T3	1		T12	33		T17	1
read_with_ack	2055	1			T10	16		T37	8		T11	17
read_with_nack	5032	1			T12	16		T13	14		T10	10
stop_byte	8311	1			T3	1		T12	32		T17	1
write_address_byte_nak	4374	1			T12	30		T13	20		T27	4
data_byte_nack	151794	1			T3	95		T12	1088		T17	85
stop_byte_nack	4898	1			T3	1		T12	29		T17	1
nakok_byte_nack	76199	1			T3	38		T12	565		T17	47
nakok_addr_byte_nack	2218	1			T12	8		T13	9		T27	2