Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 41919495 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 13802764 1 T1 169 T2 658 T3 3821



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 49372017 1 T1 40751 T2 1318 T3 11430
values[0x0] 3173903 1 T1 221 T2 9 T3 48
values[0x1] 3176339 1 T1 226 T2 8 T3 61



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 30518707 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 25203552 1 T1 15420 T2 799 T3 5833



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 377888 1 T3 58 T12 202 T13 75
valid_sources[0x01] 196383 1 T3 48 T12 146 T13 76
valid_sources[0x02] 301230 1 T3 58 T12 193 T13 56
valid_sources[0x03] 192080 1 T3 41 T12 235 T13 46
valid_sources[0x04] 219836 1 T3 46 T12 166 T13 32
valid_sources[0x05] 319374 1 T3 48 T12 197 T13 49
valid_sources[0x06] 227223 1 T3 41 T12 203 T13 73
valid_sources[0x07] 192396 1 T3 32 T12 209 T13 71
valid_sources[0x08] 190491 1 T3 49 T12 196 T13 66
valid_sources[0x09] 193811 1 T3 47 T12 198 T13 49
valid_sources[0x0a] 187781 1 T3 40 T12 162 T13 85
valid_sources[0x0b] 212099 1 T1 576 T3 42 T12 241
valid_sources[0x0c] 230912 1 T3 47 T12 226 T13 67
valid_sources[0x0d] 192380 1 T3 46 T12 190 T13 40
valid_sources[0x0e] 353415 1 T3 39 T12 218 T13 73
valid_sources[0x0f] 196350 1 T3 45 T12 222 T13 88
valid_sources[0x10] 202093 1 T3 49 T12 204 T13 59
valid_sources[0x11] 188820 1 T3 48 T12 211 T13 59
valid_sources[0x12] 237338 1 T3 46 T12 197 T13 49
valid_sources[0x13] 229572 1 T1 2881 T3 48 T12 201
valid_sources[0x14] 198378 1 T3 58 T12 176 T13 57
valid_sources[0x15] 186787 1 T3 48 T12 211 T13 68
valid_sources[0x16] 299980 1 T1 363 T3 49 T12 154
valid_sources[0x17] 248408 1 T3 55 T12 193 T13 29
valid_sources[0x18] 185725 1 T3 47 T12 201 T13 62
valid_sources[0x19] 208680 1 T3 43 T12 184 T13 34
valid_sources[0x1a] 202789 1 T3 59 T12 176 T13 52
valid_sources[0x1b] 236907 1 T3 40 T12 162 T13 66
valid_sources[0x1c] 183480 1 T3 51 T12 201 T13 71
valid_sources[0x1d] 249906 1 T3 40 T12 171 T13 54
valid_sources[0x1e] 198964 1 T3 44 T12 193 T13 43
valid_sources[0x1f] 195425 1 T1 2620 T3 42 T12 192
valid_sources[0x20] 197550 1 T3 49 T12 181 T13 61
valid_sources[0x21] 187909 1 T3 50 T12 170 T13 47
valid_sources[0x22] 189367 1 T3 39 T12 197 T13 73
valid_sources[0x23] 191468 1 T1 789 T3 42 T12 166
valid_sources[0x24] 191759 1 T3 51 T12 181 T13 55
valid_sources[0x25] 189788 1 T3 54 T12 228 T13 26
valid_sources[0x26] 211664 1 T3 52 T12 254 T13 48
valid_sources[0x27] 200181 1 T1 1087 T2 1333 T3 43
valid_sources[0x28] 188654 1 T3 51 T12 199 T13 69
valid_sources[0x29] 201731 1 T3 49 T12 174 T13 74
valid_sources[0x2a] 190559 1 T3 38 T12 213 T13 64
valid_sources[0x2b] 302927 1 T3 53 T12 209 T13 59
valid_sources[0x2c] 192345 1 T1 243 T3 43 T12 216
valid_sources[0x2d] 200612 1 T3 54 T12 243 T13 74
valid_sources[0x2e] 202132 1 T3 38 T12 134 T13 57
valid_sources[0x2f] 188330 1 T1 179 T3 55 T12 160
valid_sources[0x30] 219355 1 T3 43 T12 191 T13 76
valid_sources[0x31] 193581 1 T3 49 T12 210 T13 117
valid_sources[0x32] 187763 1 T3 43 T12 170 T13 38
valid_sources[0x33] 190505 1 T3 40 T12 204 T13 49
valid_sources[0x34] 192617 1 T3 46 T12 212 T13 35
valid_sources[0x35] 192467 1 T3 41 T12 192 T13 44
valid_sources[0x36] 201422 1 T3 44 T12 189 T13 84
valid_sources[0x37] 202598 1 T3 51 T12 172 T13 47
valid_sources[0x38] 190263 1 T3 40 T12 208 T13 63
valid_sources[0x39] 187914 1 T1 176 T3 39 T12 201
valid_sources[0x3a] 202331 1 T3 46 T12 171 T13 72
valid_sources[0x3b] 189091 1 T3 43 T12 170 T13 57
valid_sources[0x3c] 195695 1 T3 47 T12 202 T13 82
valid_sources[0x3d] 186607 1 T3 49 T12 196 T13 54
valid_sources[0x3e] 195283 1 T3 52 T12 183 T13 75
valid_sources[0x3f] 194611 1 T3 43 T12 204 T13 71
valid_sources[0x40] 197662 1 T3 41 T12 199 T13 63
valid_sources[0x41] 352069 1 T3 40 T12 195 T13 26
valid_sources[0x42] 272521 1 T3 52 T12 201 T13 76
valid_sources[0x43] 188001 1 T1 1270 T3 46 T12 234
valid_sources[0x44] 191385 1 T3 49 T12 205 T13 33
valid_sources[0x45] 201713 1 T3 43 T12 177 T13 96
valid_sources[0x46] 204499 1 T3 40 T12 168 T13 74
valid_sources[0x47] 194347 1 T3 51 T12 175 T13 29
valid_sources[0x48] 194738 1 T1 4 T3 47 T12 199
valid_sources[0x49] 202737 1 T3 44 T12 204 T13 46
valid_sources[0x4a] 191730 1 T3 43 T12 164 T13 43
valid_sources[0x4b] 196773 1 T3 54 T12 240 T13 50
valid_sources[0x4c] 192124 1 T3 43 T12 205 T13 70
valid_sources[0x4d] 204317 1 T3 46 T12 203 T13 59
valid_sources[0x4e] 193490 1 T3 44 T12 177 T13 57
valid_sources[0x4f] 195189 1 T3 41 T12 150 T13 50
valid_sources[0x50] 199628 1 T3 42 T12 181 T13 54
valid_sources[0x51] 190738 1 T3 62 T12 234 T13 56
valid_sources[0x52] 345138 1 T3 46 T12 174 T13 68
valid_sources[0x53] 188393 1 T3 46 T12 198 T13 44
valid_sources[0x54] 195865 1 T3 45 T12 196 T13 43
valid_sources[0x55] 189400 1 T3 38 T12 239 T13 47
valid_sources[0x56] 206272 1 T3 43 T12 161 T13 49
valid_sources[0x57] 196288 1 T3 43 T12 194 T13 72
valid_sources[0x58] 185307 1 T3 49 T12 154 T13 51
valid_sources[0x59] 202499 1 T1 268 T3 38 T12 175
valid_sources[0x5a] 185930 1 T3 37 T12 203 T13 39
valid_sources[0x5b] 206632 1 T3 58 T12 216 T13 50
valid_sources[0x5c] 193188 1 T3 46 T12 213 T13 95
valid_sources[0x5d] 215712 1 T1 1623 T3 42 T12 209
valid_sources[0x5e] 191146 1 T2 2 T3 44 T12 223
valid_sources[0x5f] 184770 1 T3 43 T12 206 T13 66
valid_sources[0x60] 190666 1 T3 43 T12 163 T13 67
valid_sources[0x61] 480126 1 T3 34 T12 186 T13 43
valid_sources[0x62] 198076 1 T3 58 T12 235 T13 55
valid_sources[0x63] 546608 1 T1 1355 T3 38 T12 201
valid_sources[0x64] 188645 1 T3 26 T12 182 T13 56
valid_sources[0x65] 462704 1 T3 48 T12 225 T13 37
valid_sources[0x66] 199088 1 T1 838 T3 42 T12 166
valid_sources[0x67] 194919 1 T3 39 T12 224 T13 65
valid_sources[0x68] 207051 1 T3 42 T12 207 T13 54
valid_sources[0x69] 307013 1 T3 38 T12 191 T13 62
valid_sources[0x6a] 193492 1 T3 48 T12 190 T13 53
valid_sources[0x6b] 202300 1 T3 44 T12 208 T13 67
valid_sources[0x6c] 323432 1 T3 40 T12 201 T4 36
valid_sources[0x6d] 228143 1 T3 37 T12 181 T13 73
valid_sources[0x6e] 224551 1 T3 34 T12 191 T13 88
valid_sources[0x6f] 191641 1 T3 51 T12 192 T13 20
valid_sources[0x70] 193496 1 T3 38 T12 226 T13 45
valid_sources[0x71] 192741 1 T3 49 T12 247 T13 41
valid_sources[0x72] 196342 1 T3 42 T12 260 T13 49
valid_sources[0x73] 209246 1 T3 47 T12 228 T13 38
valid_sources[0x74] 215590 1 T3 33 T12 176 T13 67
valid_sources[0x75] 238917 1 T3 44 T12 191 T13 22
valid_sources[0x76] 214576 1 T3 53 T12 182 T13 53
valid_sources[0x77] 190128 1 T1 274 T3 53 T12 187
valid_sources[0x78] 304311 1 T1 1573 T3 48 T12 166
valid_sources[0x79] 353145 1 T1 1612 T3 48 T12 220
valid_sources[0x7a] 197878 1 T3 38 T12 262 T13 52
valid_sources[0x7b] 200111 1 T3 45 T12 252 T13 31
valid_sources[0x7c] 190485 1 T3 44 T12 195 T13 68
valid_sources[0x7d] 213368 1 T1 397 T3 39 T12 195
valid_sources[0x7e] 217122 1 T3 31 T12 158 T13 55
valid_sources[0x7f] 194790 1 T3 39 T12 195 T13 79
valid_sources[0x80] 240243 1 T3 49 T12 242 T13 35



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 11298546 1 T1 49 T2 645 T3 3771
values[0x0] all_enables biggest_size 1602421 1 T1 75 T2 8 T3 27
values[0x1] all_enables biggest_size 901797 1 T1 45 T2 5 T3 23

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%