Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.47	100.00	85.90			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core.u_i2c_txfifo	95.19	100.00	80.77			100.00	100.00
tb.dut.i2c_core.u_i2c_fmtfifo	96.15	100.00	84.62			100.00	100.00
tb.dut.i2c_core.u_i2c_rxfifo	96.15	100.00	84.62			100.00	100.00
tb.dut.i2c_core.u_i2c_acqfifo	97.12	100.00	88.46			100.00	100.00

---

Module Instance : tb.dut.i2c_core.u_i2c_txfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.19	100.00	80.77			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.19	100.00	80.77			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.17	96.63	73.13			90.91	100.00	i2c_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

---

Module Instance : tb.dut.i2c_core.u_i2c_fmtfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.17	96.63	73.13			90.91	100.00	i2c_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

---

Module Instance : tb.dut.i2c_core.u_i2c_rxfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.17	96.63	73.13			90.91	100.00	i2c_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

---

Module Instance : tb.dut.i2c_core.u_i2c_acqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	88.46			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	88.46			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.17	96.63	73.13			90.91	100.00	i2c_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

Line Coverage for Module : prim_fifo_sync ( parameter Width=13,Pass=0,Depth=64,OutputZeroIfEmpty=1,Secure=0,DepthW=7,gen_normal_fifo.PTRV_W=6,gen_normal_fifo.PTR_WIDTH=7 + Width=8,Pass=0,Depth=64,OutputZeroIfEmpty=1,Secure=0,DepthW=7,gen_normal_fifo.PTRV_W=6,gen_normal_fifo.PTR_WIDTH=7 )
Line Coverage for Module self-instances :

SCORE	LINE
96.15	100.00

tb.dut.i2c_core.u_i2c_fmtfifo

SCORE	LINE
96.15	100.00

tb.dut.i2c_core.u_i2c_rxfifo

SCORE	LINE
95.19	100.00

tb.dut.i2c_core.u_i2c_txfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=10,Pass=0,Depth=268,OutputZeroIfEmpty=1,Secure=0,DepthW=9,gen_normal_fifo.PTRV_W=9,gen_normal_fifo.PTR_WIDTH=10 )
Line Coverage for Module self-instances :

SCORE	LINE
97.12	100.00

tb.dut.i2c_core.u_i2c_acqfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=13,Pass=0,Depth=64,OutputZeroIfEmpty=1,Secure=0,DepthW=7,gen_normal_fifo.PTRV_W=6,gen_normal_fifo.PTR_WIDTH=7 )
Cond Coverage for Module self-instances :

SCORE	COND
96.15	84.62

tb.dut.i2c_core.u_i2c_fmtfifo

	Total	Covered	Percent
Conditions	26	22	84.62
Logical	26	22	84.62
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (7'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T17,T27

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T3,T12,T17
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T12,T17
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T12

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T11,T24
1	0	1	Covered	T2,T3,T12
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T12

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T17,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T12

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T17,T27

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=10,Pass=0,Depth=268,OutputZeroIfEmpty=1,Secure=0,DepthW=9,gen_normal_fifo.PTRV_W=9,gen_normal_fifo.PTR_WIDTH=10 )
Cond Coverage for Module self-instances :

SCORE	COND
97.12	88.46

tb.dut.i2c_core.u_i2c_acqfifo

	Total	Covered	Percent
Conditions	26	23	88.46
Logical	26	23	88.46
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (9'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((9'(gen_normal_fifo.wptr_value) - 9'(gen_normal_fifo.rptr_value))) : (((9'(Depth) - 9'(gen_normal_fifo.rptr_value)) + 9'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T51,T52,T53

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((9'(gen_normal_fifo.wptr_value) - 9'(gen_normal_fifo.rptr_value))) : (((9'(Depth) - 9'(gen_normal_fifo.rptr_value)) + 9'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T7,T32,T33
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T7,T32,T33
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T29,T49
1	1	0	Not Covered
1	1	1	Covered	T1,T7,T8

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T73,T74,T75
1	0	1	Covered	T1,T7,T8
1	1	0	Not Covered
1	1	1	Covered	T1,T7,T8

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T51,T52,T53
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T51,T52,T53

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=8,Pass=0,Depth=64,OutputZeroIfEmpty=1,Secure=0,DepthW=7,gen_normal_fifo.PTRV_W=6,gen_normal_fifo.PTR_WIDTH=7 )
Cond Coverage for Module self-instances :

SCORE	COND
96.15	84.62

tb.dut.i2c_core.u_i2c_rxfifo

SCORE	COND
95.19	80.77

tb.dut.i2c_core.u_i2c_txfifo

	Total	Covered	Percent
Conditions	26	22	84.62
Logical	26	22	84.62
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (7'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T12,T7

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T12,T13
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T12,T13
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T14,T11
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T12

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T12
1	1	0	Not Covered
1	1	1	Covered	T1,T12,T13

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T12,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T12

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T12,T7

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T12
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T12
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T3,T12

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1726439872	535459833	0	0
DepthKnown_A	1726439872	1725772960	0	0
RvalidKnown_A	1726439872	1725772960	0	0
WreadyKnown_A	1726439872	1725772960	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	1726439872	535459833	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1726439872	535459833	0	0
T1	176908	620	0	0
T2	63040	27117	0	0
T3	97808	23038	0	0
T4	5324	0	0	0
T7	3876648	508073	0	0
T8	174160	1056	0	0
T10	1110120	307443	0	0
T11	0	246633	0	0
T12	2085236	741471	0	0
T13	365704	88854	0	0
T14	0	288780	0	0
T17	98836	23930	0	0
T18	0	63199	0	0
T27	0	177893	0	0
T32	0	145999	0	0
T33	0	31475	0	0
T34	0	71246	0	0
T37	316082	174343	0	0
T38	0	176974	0	0
T51	0	555976	0	0
T67	0	1750	0	0
T68	0	1018	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1726439872	1725772960	0	0
T1	353816	353572	0	0
T2	63040	62696	0	0
T3	97808	97528	0	0
T4	5324	5016	0	0
T7	3876648	3876308	0	0
T8	174160	173868	0	0
T10	1110120	1109544	0	0
T12	2085236	2084948	0	0
T13	365704	365316	0	0
T17	98836	98532	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1726439872	1725772960	0	0
T1	353816	353572	0	0
T2	63040	62696	0	0
T3	97808	97528	0	0
T4	5324	5016	0	0
T7	3876648	3876308	0	0
T8	174160	173868	0	0
T10	1110120	1109544	0	0
T12	2085236	2084948	0	0
T13	365704	365316	0	0
T17	98836	98532	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1726439872	1725772960	0	0
T1	353816	353572	0	0
T2	63040	62696	0	0
T3	97808	97528	0	0
T4	5324	5016	0	0
T7	3876648	3876308	0	0
T8	174160	173868	0	0
T10	1110120	1109544	0	0
T12	2085236	2084948	0	0
T13	365704	365316	0	0
T17	98836	98532	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	1726439872	535459833	0	0
T1	176908	620	0	0
T2	63040	27117	0	0
T3	97808	23038	0	0
T4	5324	0	0	0
T7	3876648	508073	0	0
T8	174160	1056	0	0
T10	1110120	307443	0	0
T11	0	246633	0	0
T12	2085236	741471	0	0
T13	365704	88854	0	0
T14	0	288780	0	0
T17	98836	23930	0	0
T18	0	63199	0	0
T27	0	177893	0	0
T32	0	145999	0	0
T33	0	31475	0	0
T34	0	71246	0	0
T37	316082	174343	0	0
T38	0	176974	0	0
T51	0	555976	0	0
T67	0	1750	0	0
T68	0	1018	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_i2c_txfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_i2c_txfifo

	Total	Covered	Percent
Conditions	26	21	80.77
Logical	26	21	80.77
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (7'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T15,T16

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T7,T8

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T7,T8
1	1	0	Not Covered
1	1	1	Covered	T1,T7,T8

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T15,T16

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_i2c_txfifo

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T15,T16
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T7,T8

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T7,T8

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_i2c_txfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	431609968	110670786	0	0
DepthKnown_A	431609968	431443240	0	0
RvalidKnown_A	431609968	431443240	0	0
WreadyKnown_A	431609968	431443240	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	431609968	110670786	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431609968	110670786	0	0
T1	88454	84163	0	0
T2	15760	0	0	0
T3	24452	0	0	0
T4	1331	0	0	0
T7	969162	957442	0	0
T8	43540	38039	0	0
T10	277530	0	0	0
T12	521309	0	0	0
T13	91426	0	0	0
T17	24709	0	0	0
T18	0	81410	0	0
T19	0	314000	0	0
T32	0	82440	0	0
T33	0	42828	0	0
T34	0	100462	0	0
T67	0	128678	0	0
T68	0	154168	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431609968	431443240	0	0
T1	88454	88393	0	0
T2	15760	15674	0	0
T3	24452	24382	0	0
T4	1331	1254	0	0
T7	969162	969077	0	0
T8	43540	43467	0	0
T10	277530	277386	0	0
T12	521309	521237	0	0
T13	91426	91329	0	0
T17	24709	24633	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431609968	431443240	0	0
T1	88454	88393	0	0
T2	15760	15674	0	0
T3	24452	24382	0	0
T4	1331	1254	0	0
T7	969162	969077	0	0
T8	43540	43467	0	0
T10	277530	277386	0	0
T12	521309	521237	0	0
T13	91426	91329	0	0
T17	24709	24633	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431609968	431443240	0	0
T1	88454	88393	0	0
T2	15760	15674	0	0
T3	24452	24382	0	0
T4	1331	1254	0	0
T7	969162	969077	0	0
T8	43540	43467	0	0
T10	277530	277386	0	0
T12	521309	521237	0	0
T13	91426	91329	0	0
T17	24709	24633	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	431609968	110670786	0	0
T1	88454	84163	0	0
T2	15760	0	0	0
T3	24452	0	0	0
T4	1331	0	0	0
T7	969162	957442	0	0
T8	43540	38039	0	0
T10	277530	0	0	0
T12	521309	0	0	0
T13	91426	0	0	0
T17	24709	0	0	0
T18	0	81410	0	0
T19	0	314000	0	0
T32	0	82440	0	0
T33	0	42828	0	0
T34	0	100462	0	0
T67	0	128678	0	0
T68	0	154168	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_i2c_fmtfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_i2c_fmtfifo

	Total	Covered	Percent
Conditions	26	22	84.62
Logical	26	22	84.62
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (7'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T17,T27

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T3,T12,T17
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T12,T17
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T12

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T11,T24
1	0	1	Covered	T2,T3,T12
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T12

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T17,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T12

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T17,T27

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_i2c_fmtfifo

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T17,T27
0	1	Covered	T1,T2,T3
0	0	Covered	T3,T12,T17

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T12

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_i2c_fmtfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	431609968	173953644	0	0
DepthKnown_A	431609968	431443240	0	0
RvalidKnown_A	431609968	431443240	0	0
WreadyKnown_A	431609968	431443240	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	431609968	173953644	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431609968	173953644	0	0
T2	15760	13788	0	0
T3	24452	23038	0	0
T4	1331	0	0	0
T7	969162	0	0	0
T8	43540	0	0	0
T10	277530	217386	0	0
T11	0	186357	0	0
T12	521309	480157	0	0
T13	91426	83493	0	0
T14	0	139961	0	0
T17	24709	23930	0	0
T27	0	163287	0	0
T37	158041	148280	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431609968	431443240	0	0
T1	88454	88393	0	0
T2	15760	15674	0	0
T3	24452	24382	0	0
T4	1331	1254	0	0
T7	969162	969077	0	0
T8	43540	43467	0	0
T10	277530	277386	0	0
T12	521309	521237	0	0
T13	91426	91329	0	0
T17	24709	24633	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431609968	431443240	0	0
T1	88454	88393	0	0
T2	15760	15674	0	0
T3	24452	24382	0	0
T4	1331	1254	0	0
T7	969162	969077	0	0
T8	43540	43467	0	0
T10	277530	277386	0	0
T12	521309	521237	0	0
T13	91426	91329	0	0
T17	24709	24633	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431609968	431443240	0	0
T1	88454	88393	0	0
T2	15760	15674	0	0
T3	24452	24382	0	0
T4	1331	1254	0	0
T7	969162	969077	0	0
T8	43540	43467	0	0
T10	277530	277386	0	0
T12	521309	521237	0	0
T13	91426	91329	0	0
T17	24709	24633	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	431609968	173953644	0	0
T2	15760	13788	0	0
T3	24452	23038	0	0
T4	1331	0	0	0
T7	969162	0	0	0
T8	43540	0	0	0
T10	277530	217386	0	0
T11	0	186357	0	0
T12	521309	480157	0	0
T13	91426	83493	0	0
T14	0	139961	0	0
T17	24709	23930	0	0
T27	0	163287	0	0
T37	158041	148280	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_i2c_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_i2c_rxfifo

	Total	Covered	Percent
Conditions	26	22	84.62
Logical	26	22	84.62
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (7'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T12,T10

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T12,T13,T10
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T12,T13,T10
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T14,T11
1	1	0	Not Covered
1	1	1	Covered	T2,T12,T13

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T12,T13
1	1	0	Not Covered
1	1	1	Covered	T12,T13,T10

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T12,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T12,T13

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T12,T10

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T12,T13
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_i2c_rxfifo

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T12,T10
0	1	Covered	T1,T2,T3
0	0	Covered	T12,T13,T10

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T12,T13

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T12,T13
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_i2c_rxfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	431609968	43731950	0	0
DepthKnown_A	431609968	431443240	0	0
RvalidKnown_A	431609968	431443240	0	0
WreadyKnown_A	431609968	431443240	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	431609968	43731950	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431609968	43731950	0	0
T2	15760	13329	0	0
T3	24452	0	0	0
T4	1331	0	0	0
T7	969162	0	0	0
T8	43540	0	0	0
T10	277530	90057	0	0
T11	0	60276	0	0
T12	521309	261314	0	0
T13	91426	5361	0	0
T14	0	148819	0	0
T17	24709	0	0	0
T27	0	14606	0	0
T37	158041	26063	0	0
T38	0	176974	0	0
T76	0	173364	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431609968	431443240	0	0
T1	88454	88393	0	0
T2	15760	15674	0	0
T3	24452	24382	0	0
T4	1331	1254	0	0
T7	969162	969077	0	0
T8	43540	43467	0	0
T10	277530	277386	0	0
T12	521309	521237	0	0
T13	91426	91329	0	0
T17	24709	24633	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431609968	431443240	0	0
T1	88454	88393	0	0
T2	15760	15674	0	0
T3	24452	24382	0	0
T4	1331	1254	0	0
T7	969162	969077	0	0
T8	43540	43467	0	0
T10	277530	277386	0	0
T12	521309	521237	0	0
T13	91426	91329	0	0
T17	24709	24633	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431609968	431443240	0	0
T1	88454	88393	0	0
T2	15760	15674	0	0
T3	24452	24382	0	0
T4	1331	1254	0	0
T7	969162	969077	0	0
T8	43540	43467	0	0
T10	277530	277386	0	0
T12	521309	521237	0	0
T13	91426	91329	0	0
T17	24709	24633	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	431609968	43731950	0	0
T2	15760	13329	0	0
T3	24452	0	0	0
T4	1331	0	0	0
T7	969162	0	0	0
T8	43540	0	0	0
T10	277530	90057	0	0
T11	0	60276	0	0
T12	521309	261314	0	0
T13	91426	5361	0	0
T14	0	148819	0	0
T17	24709	0	0	0
T27	0	14606	0	0
T37	158041	26063	0	0
T38	0	176974	0	0
T76	0	173364	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_i2c_acqfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_i2c_acqfifo

	Total	Covered	Percent
Conditions	26	23	88.46
Logical	26	23	88.46
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (9'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((9'(gen_normal_fifo.wptr_value) - 9'(gen_normal_fifo.rptr_value))) : (((9'(Depth) - 9'(gen_normal_fifo.rptr_value)) + 9'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T51,T52,T53

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((9'(gen_normal_fifo.wptr_value) - 9'(gen_normal_fifo.rptr_value))) : (((9'(Depth) - 9'(gen_normal_fifo.rptr_value)) + 9'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T7,T32,T33
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T7,T32,T33
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T29,T49
1	1	0	Not Covered
1	1	1	Covered	T1,T7,T8

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T73,T74,T75
1	0	1	Covered	T1,T7,T8
1	1	0	Not Covered
1	1	1	Covered	T1,T7,T8

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T51,T52,T53
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T51,T52,T53

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_i2c_acqfifo

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T51,T52,T53
0	1	Covered	T1,T2,T3
0	0	Covered	T7,T32,T33

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T7,T8

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_i2c_acqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	431609968	207103453	0	0
DepthKnown_A	431609968	431443240	0	0
RvalidKnown_A	431609968	431443240	0	0
WreadyKnown_A	431609968	431443240	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	431609968	207103453	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431609968	207103453	0	0
T1	88454	620	0	0
T2	15760	0	0	0
T3	24452	0	0	0
T4	1331	0	0	0
T7	969162	508073	0	0
T8	43540	1056	0	0
T10	277530	0	0	0
T12	521309	0	0	0
T13	91426	0	0	0
T17	24709	0	0	0
T18	0	63199	0	0
T32	0	145999	0	0
T33	0	31475	0	0
T34	0	71246	0	0
T51	0	555976	0	0
T67	0	1750	0	0
T68	0	1018	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431609968	431443240	0	0
T1	88454	88393	0	0
T2	15760	15674	0	0
T3	24452	24382	0	0
T4	1331	1254	0	0
T7	969162	969077	0	0
T8	43540	43467	0	0
T10	277530	277386	0	0
T12	521309	521237	0	0
T13	91426	91329	0	0
T17	24709	24633	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431609968	431443240	0	0
T1	88454	88393	0	0
T2	15760	15674	0	0
T3	24452	24382	0	0
T4	1331	1254	0	0
T7	969162	969077	0	0
T8	43540	43467	0	0
T10	277530	277386	0	0
T12	521309	521237	0	0
T13	91426	91329	0	0
T17	24709	24633	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431609968	431443240	0	0
T1	88454	88393	0	0
T2	15760	15674	0	0
T3	24452	24382	0	0
T4	1331	1254	0	0
T7	969162	969077	0	0
T8	43540	43467	0	0
T10	277530	277386	0	0
T12	521309	521237	0	0
T13	91426	91329	0	0
T17	24709	24633	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	431609968	207103453	0	0
T1	88454	620	0	0
T2	15760	0	0	0
T3	24452	0	0	0
T4	1331	0	0	0
T7	969162	508073	0	0
T8	43540	1056	0	0
T10	277530	0	0	0
T12	521309	0	0	0
T13	91426	0	0	0
T17	24709	0	0	0
T18	0	63199	0	0
T32	0	145999	0	0
T33	0	31475	0	0
T34	0	71246	0	0
T51	0	555976	0	0
T67	0	1750	0	0
T68	0	1018	0	0