Unified Coverage Report :: Module :: i2c_reg_top

Module : i2c_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.91	100.00	99.63			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	99.91	100.00	99.63			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.91	100.00	99.63			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.04	98.57	99.00	100.00		97.64	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_acqdata_abyte	100.00	100.00
u_acqdata_signal	100.00	100.00
u_alert_test	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_ctrl_enablehost	100.00	100.00	100.00			100.00
u_ctrl_enabletarget	100.00	100.00	100.00			100.00
u_ctrl_llpbk	100.00	100.00	100.00			100.00
u_fdata0_qe	100.00	100.00				100.00
u_fdata_fbyte	100.00	100.00	100.00			100.00
u_fdata_nakok	100.00	100.00	100.00			100.00
u_fdata_rcont	100.00	100.00	100.00			100.00
u_fdata_readb	100.00	100.00	100.00			100.00
u_fdata_start	100.00	100.00	100.00			100.00
u_fdata_stop	100.00	100.00	100.00			100.00
u_fifo_ctrl0_qe	100.00	100.00				100.00
u_fifo_ctrl_acqrst	100.00	100.00	100.00			100.00
u_fifo_ctrl_fmtrst	100.00	100.00	100.00			100.00
u_fifo_ctrl_rxrst	100.00	100.00	100.00			100.00
u_fifo_ctrl_txrst	100.00	100.00	100.00			100.00
u_host_fifo_config0_qe	100.00	100.00				100.00
u_host_fifo_config_fmt_thresh	100.00	100.00	100.00			100.00
u_host_fifo_config_rx_thresh	100.00	100.00	100.00			100.00
u_host_fifo_status_fmtlvl	100.00	100.00
u_host_fifo_status_rxlvl	100.00	100.00
u_host_timeout_ctrl	100.00	100.00	100.00			100.00
u_intr_enable_acq_full	100.00	100.00	100.00			100.00
u_intr_enable_acq_threshold	100.00	100.00	100.00			100.00
u_intr_enable_cmd_complete	100.00	100.00	100.00			100.00
u_intr_enable_fmt_threshold	100.00	100.00	100.00			100.00
u_intr_enable_host_timeout	100.00	100.00	100.00			100.00
u_intr_enable_nak	100.00	100.00	100.00			100.00
u_intr_enable_rx_overflow	100.00	100.00	100.00			100.00
u_intr_enable_rx_threshold	100.00	100.00	100.00			100.00
u_intr_enable_scl_interference	100.00	100.00	100.00			100.00
u_intr_enable_sda_interference	100.00	100.00	100.00			100.00
u_intr_enable_sda_unstable	100.00	100.00	100.00			100.00
u_intr_enable_stretch_timeout	100.00	100.00	100.00			100.00
u_intr_enable_tx_stretch	100.00	100.00	100.00			100.00
u_intr_enable_tx_threshold	100.00	100.00	100.00			100.00
u_intr_enable_unexp_stop	100.00	100.00	100.00			100.00
u_intr_state_acq_full	62.59	77.78	50.00			60.00
u_intr_state_acq_threshold	62.59	77.78	50.00			60.00
u_intr_state_cmd_complete	100.00	100.00	100.00			100.00
u_intr_state_fmt_threshold	62.59	77.78	50.00			60.00
u_intr_state_host_timeout	100.00	100.00	100.00			100.00
u_intr_state_nak	100.00	100.00	100.00			100.00
u_intr_state_rx_overflow	100.00	100.00	100.00			100.00
u_intr_state_rx_threshold	62.59	77.78	50.00			60.00
u_intr_state_scl_interference	100.00	100.00	100.00			100.00
u_intr_state_sda_interference	100.00	100.00	100.00			100.00
u_intr_state_sda_unstable	100.00	100.00	100.00			100.00
u_intr_state_stretch_timeout	100.00	100.00	100.00			100.00
u_intr_state_tx_stretch	62.59	77.78	50.00			60.00
u_intr_state_tx_threshold	62.59	77.78	50.00			60.00
u_intr_state_unexp_stop	100.00	100.00	100.00			100.00
u_intr_test_acq_full	100.00	100.00
u_intr_test_acq_threshold	100.00	100.00
u_intr_test_cmd_complete	100.00	100.00
u_intr_test_fmt_threshold	100.00	100.00
u_intr_test_host_timeout	100.00	100.00
u_intr_test_nak	100.00	100.00
u_intr_test_rx_overflow	100.00	100.00
u_intr_test_rx_threshold	100.00	100.00
u_intr_test_scl_interference	100.00	100.00
u_intr_test_sda_interference	100.00	100.00
u_intr_test_sda_unstable	100.00	100.00
u_intr_test_stretch_timeout	100.00	100.00
u_intr_test_tx_stretch	100.00	100.00
u_intr_test_tx_threshold	100.00	100.00
u_intr_test_unexp_stop	100.00	100.00
u_ovrd_sclval	100.00	100.00	100.00			100.00
u_ovrd_sdaval	100.00	100.00	100.00			100.00
u_ovrd_txovrden	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_rdata	100.00	100.00
u_reg_if	98.67	97.14	97.53			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_status_acqempty	100.00	100.00
u_status_acqfull	100.00	100.00
u_status_fmtempty	100.00	100.00
u_status_fmtfull	100.00	100.00
u_status_hostidle	100.00	100.00
u_status_rxempty	100.00	100.00
u_status_rxfull	100.00	100.00
u_status_targetidle	100.00	100.00
u_status_txempty	100.00	100.00
u_status_txfull	100.00	100.00
u_target_fifo_config0_qe	100.00	100.00				100.00
u_target_fifo_config_acq_thresh	100.00	100.00	100.00			100.00
u_target_fifo_config_tx_thresh	100.00	100.00	100.00			100.00
u_target_fifo_status_acqlvl	100.00	100.00
u_target_fifo_status_txlvl	100.00	100.00
u_target_id_address0	100.00	100.00	100.00			100.00
u_target_id_address1	100.00	100.00	100.00			100.00
u_target_id_mask0	100.00	100.00	100.00			100.00
u_target_id_mask1	100.00	100.00	100.00			100.00
u_timeout_ctrl_en	100.00	100.00	100.00			100.00
u_timeout_ctrl_val	100.00	100.00	100.00			100.00
u_timing0_thigh	100.00	100.00	100.00			100.00
u_timing0_tlow	100.00	100.00	100.00			100.00
u_timing1_t_f	100.00	100.00	100.00			100.00
u_timing1_t_r	100.00	100.00	100.00			100.00
u_timing2_thd_sta	100.00	100.00	100.00			100.00
u_timing2_tsu_sta	100.00	100.00	100.00			100.00
u_timing3_thd_dat	100.00	100.00	100.00			100.00
u_timing3_tsu_dat	100.00	100.00	100.00			100.00
u_timing4_t_buf	100.00	100.00	100.00			100.00
u_timing4_tsu_sto	100.00	100.00	100.00			100.00
u_txdata	100.00	100.00	100.00			100.00
u_txdata0_qe	100.00	100.00				100.00
u_val_scl_rx	66.67	66.67
u_val_sda_rx	66.67	66.67

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c_reg_top

	Line No.	Total	Covered	Percent
TOTAL		306	306	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	1122	1	1	100.00
CONT_ASSIGN	1137	1	1	100.00
CONT_ASSIGN	1153	1	1	100.00
CONT_ASSIGN	1169	1	1	100.00
CONT_ASSIGN	1185	1	1	100.00
CONT_ASSIGN	1201	1	1	100.00
CONT_ASSIGN	1217	1	1	100.00
CONT_ASSIGN	1233	1	1	100.00
CONT_ASSIGN	1249	1	1	100.00
CONT_ASSIGN	1265	1	1	100.00
CONT_ASSIGN	1281	1	1	100.00
CONT_ASSIGN	1297	1	1	100.00
CONT_ASSIGN	1313	1	1	100.00
CONT_ASSIGN	1329	1	1	100.00
CONT_ASSIGN	1345	1	1	100.00
CONT_ASSIGN	1361	1	1	100.00
CONT_ASSIGN	1367	1	1	100.00
CONT_ASSIGN	1381	1	1	100.00
CONT_ASSIGN	1673	1	1	100.00
CONT_ASSIGN	1701	1	1	100.00
CONT_ASSIGN	1729	1	1	100.00
CONT_ASSIGN	1757	1	1	100.00
CONT_ASSIGN	1785	1	1	100.00
CONT_ASSIGN	1813	1	1	100.00
CONT_ASSIGN	1854	1	1	100.00
CONT_ASSIGN	1882	1	1	100.00
CONT_ASSIGN	1910	1	1	100.00
CONT_ASSIGN	1938	1	1	100.00
CONT_ASSIGN	1979	1	1	100.00
CONT_ASSIGN	2007	1	1	100.00
CONT_ASSIGN	2048	1	1	100.00
CONT_ASSIGN	2076	1	1	100.00
CONT_ASSIGN	2773	1	1	100.00
ALWAYS	2807	26	26	100.00
CONT_ASSIGN	2835	1	1	100.00
ALWAYS	2839	1	1	100.00
CONT_ASSIGN	2868	1	1	100.00
CONT_ASSIGN	2870	1	1	100.00
CONT_ASSIGN	2872	1	1	100.00
CONT_ASSIGN	2874	1	1	100.00
CONT_ASSIGN	2876	1	1	100.00
CONT_ASSIGN	2878	1	1	100.00
CONT_ASSIGN	2880	1	1	100.00
CONT_ASSIGN	2882	1	1	100.00
CONT_ASSIGN	2884	1	1	100.00
CONT_ASSIGN	2886	1	1	100.00
CONT_ASSIGN	2887	1	1	100.00
CONT_ASSIGN	2889	1	1	100.00
CONT_ASSIGN	2891	1	1	100.00
CONT_ASSIGN	2893	1	1	100.00
CONT_ASSIGN	2895	1	1	100.00
CONT_ASSIGN	2897	1	1	100.00
CONT_ASSIGN	2899	1	1	100.00
CONT_ASSIGN	2901	1	1	100.00
CONT_ASSIGN	2903	1	1	100.00
CONT_ASSIGN	2905	1	1	100.00
CONT_ASSIGN	2907	1	1	100.00
CONT_ASSIGN	2909	1	1	100.00
CONT_ASSIGN	2911	1	1	100.00
CONT_ASSIGN	2913	1	1	100.00
CONT_ASSIGN	2915	1	1	100.00
CONT_ASSIGN	2917	1	1	100.00
CONT_ASSIGN	2918	1	1	100.00
CONT_ASSIGN	2920	1	1	100.00
CONT_ASSIGN	2922	1	1	100.00
CONT_ASSIGN	2924	1	1	100.00
CONT_ASSIGN	2926	1	1	100.00
CONT_ASSIGN	2928	1	1	100.00
CONT_ASSIGN	2930	1	1	100.00
CONT_ASSIGN	2932	1	1	100.00
CONT_ASSIGN	2934	1	1	100.00
CONT_ASSIGN	2936	1	1	100.00
CONT_ASSIGN	2938	1	1	100.00
CONT_ASSIGN	2940	1	1	100.00
CONT_ASSIGN	2942	1	1	100.00
CONT_ASSIGN	2944	1	1	100.00
CONT_ASSIGN	2946	1	1	100.00
CONT_ASSIGN	2948	1	1	100.00
CONT_ASSIGN	2949	1	1	100.00
CONT_ASSIGN	2951	1	1	100.00
CONT_ASSIGN	2952	1	1	100.00
CONT_ASSIGN	2954	1	1	100.00
CONT_ASSIGN	2956	1	1	100.00
CONT_ASSIGN	2958	1	1	100.00
CONT_ASSIGN	2959	1	1	100.00
CONT_ASSIGN	2960	1	1	100.00
CONT_ASSIGN	2961	1	1	100.00
CONT_ASSIGN	2963	1	1	100.00
CONT_ASSIGN	2965	1	1	100.00
CONT_ASSIGN	2967	1	1	100.00
CONT_ASSIGN	2969	1	1	100.00
CONT_ASSIGN	2971	1	1	100.00
CONT_ASSIGN	2973	1	1	100.00
CONT_ASSIGN	2974	1	1	100.00
CONT_ASSIGN	2976	1	1	100.00
CONT_ASSIGN	2978	1	1	100.00
CONT_ASSIGN	2980	1	1	100.00
CONT_ASSIGN	2982	1	1	100.00
CONT_ASSIGN	2983	1	1	100.00
CONT_ASSIGN	2985	1	1	100.00
CONT_ASSIGN	2987	1	1	100.00
CONT_ASSIGN	2988	1	1	100.00
CONT_ASSIGN	2990	1	1	100.00
CONT_ASSIGN	2992	1	1	100.00
CONT_ASSIGN	2993	1	1	100.00
CONT_ASSIGN	2994	1	1	100.00
CONT_ASSIGN	2995	1	1	100.00
CONT_ASSIGN	2997	1	1	100.00
CONT_ASSIGN	2999	1	1	100.00
CONT_ASSIGN	3001	1	1	100.00
CONT_ASSIGN	3002	1	1	100.00
CONT_ASSIGN	3003	1	1	100.00
CONT_ASSIGN	3005	1	1	100.00
CONT_ASSIGN	3007	1	1	100.00
CONT_ASSIGN	3008	1	1	100.00
CONT_ASSIGN	3010	1	1	100.00
CONT_ASSIGN	3012	1	1	100.00
CONT_ASSIGN	3013	1	1	100.00
CONT_ASSIGN	3015	1	1	100.00
CONT_ASSIGN	3017	1	1	100.00
CONT_ASSIGN	3018	1	1	100.00
CONT_ASSIGN	3020	1	1	100.00
CONT_ASSIGN	3022	1	1	100.00
CONT_ASSIGN	3023	1	1	100.00
CONT_ASSIGN	3025	1	1	100.00
CONT_ASSIGN	3027	1	1	100.00
CONT_ASSIGN	3028	1	1	100.00
CONT_ASSIGN	3030	1	1	100.00
CONT_ASSIGN	3032	1	1	100.00
CONT_ASSIGN	3033	1	1	100.00
CONT_ASSIGN	3035	1	1	100.00
CONT_ASSIGN	3037	1	1	100.00
CONT_ASSIGN	3039	1	1	100.00
CONT_ASSIGN	3041	1	1	100.00
CONT_ASSIGN	3042	1	1	100.00
CONT_ASSIGN	3043	1	1	100.00
CONT_ASSIGN	3045	1	1	100.00
CONT_ASSIGN	3046	1	1	100.00
CONT_ASSIGN	3048	1	1	100.00
ALWAYS	3052	26	26	100.00
ALWAYS	3082	105	105	100.00
CONT_ASSIGN	3273	0	0
CONT_ASSIGN	3281	1	1	100.00
CONT_ASSIGN	3282	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
77	1	1
89	1	1
90	1	1
118	1	1
119	1	1
1122	1	1
1137	1	1
1153	1	1
1169	1	1
1185	1	1
1201	1	1
1217	1	1
1233	1	1
1249	1	1
1265	1	1
1281	1	1
1297	1	1
1313	1	1
1329	1	1
1345	1	1
1361	1	1
1367	1	1
1381	1	1
1673	1	1
1701	1	1
1729	1	1
1757	1	1
1785	1	1
1813	1	1
1854	1	1
1882	1	1
1910	1	1
1938	1	1
1979	1	1
2007	1	1
2048	1	1
2076	1	1
2773	1	1
2807	1	1
2808	1	1
2809	1	1
2810	1	1
2811	1	1
2812	1	1
2813	1	1
2814	1	1
2815	1	1
2816	1	1
2817	1	1
2818	1	1
2819	1	1
2820	1	1
2821	1	1
2822	1	1
2823	1	1
2824	1	1
2825	1	1
2826	1	1
2827	1	1
2828	1	1
2829	1	1
2830	1	1
2831	1	1
2832	1	1
2835	1	1
2839	1	1
2868	1	1
2870	1	1
2872	1	1
2874	1	1
2876	1	1
2878	1	1
2880	1	1
2882	1	1
2884	1	1
2886	1	1
2887	1	1
2889	1	1
2891	1	1
2893	1	1
2895	1	1
2897	1	1
2899	1	1
2901	1	1
2903	1	1
2905	1	1
2907	1	1
2909	1	1
2911	1	1
2913	1	1
2915	1	1
2917	1	1
2918	1	1
2920	1	1
2922	1	1
2924	1	1
2926	1	1
2928	1	1
2930	1	1
2932	1	1
2934	1	1
2936	1	1
2938	1	1
2940	1	1
2942	1	1
2944	1	1
2946	1	1
2948	1	1
2949	1	1
2951	1	1
2952	1	1
2954	1	1
2956	1	1
2958	1	1
2959	1	1
2960	1	1
2961	1	1
2963	1	1
2965	1	1
2967	1	1
2969	1	1
2971	1	1
2973	1	1
2974	1	1
2976	1	1
2978	1	1
2980	1	1
2982	1	1
2983	1	1
2985	1	1
2987	1	1
2988	1	1
2990	1	1
2992	1	1
2993	1	1
2994	1	1
2995	1	1
2997	1	1
2999	1	1
3001	1	1
3002	1	1
3003	1	1
3005	1	1
3007	1	1
3008	1	1
3010	1	1
3012	1	1
3013	1	1
3015	1	1
3017	1	1
3018	1	1
3020	1	1
3022	1	1
3023	1	1
3025	1	1
3027	1	1
3028	1	1
3030	1	1
3032	1	1
3033	1	1
3035	1	1
3037	1	1
3039	1	1
3041	1	1
3042	1	1
3043	1	1
3045	1	1
3046	1	1
3048	1	1
3052	1	1
3053	1	1
3054	1	1
3055	1	1
3056	1	1
3057	1	1
3058	1	1
3059	1	1
3060	1	1
3061	1	1
3062	1	1
3063	1	1
3064	1	1
3065	1	1
3066	1	1
3067	1	1
3068	1	1
3069	1	1
3070	1	1
3071	1	1
3072	1	1
3073	1	1
3074	1	1
3075	1	1
3076	1	1
3077	1	1
3082	1	1
3083	1	1
3085	1	1
3086	1	1
3087	1	1
3088	1	1
3089	1	1
3090	1	1
3091	1	1
3092	1	1
3093	1	1
3094	1	1
3095	1	1
3096	1	1
3097	1	1
3098	1	1
3099	1	1
3103	1	1
3104	1	1
3105	1	1
3106	1	1
3107	1	1
3108	1	1
3109	1	1
3110	1	1
3111	1	1
3112	1	1
3113	1	1
3114	1	1
3115	1	1
3116	1	1
3117	1	1
3121	1	1
3122	1	1
3123	1	1
3124	1	1
3125	1	1
3126	1	1
3127	1	1
3128	1	1
3129	1	1
3130	1	1
3131	1	1
3132	1	1
3133	1	1
3134	1	1
3135	1	1
3139	1	1
3143	1	1
3144	1	1
3145	1	1
3149	1	1
3150	1	1
3151	1	1
3152	1	1
3153	1	1
3154	1	1
3155	1	1
3156	1	1
3157	1	1
3158	1	1
3162	1	1
3166	1	1
3167	1	1
3168	1	1
3169	1	1
3170	1	1
3171	1	1
3175	1	1
3176	1	1
3177	1	1
3178	1	1
3182	1	1
3183	1	1
3187	1	1
3188	1	1
3192	1	1
3193	1	1
3197	1	1
3198	1	1
3202	1	1
3203	1	1
3204	1	1
3208	1	1
3209	1	1
3213	1	1
3214	1	1
3218	1	1
3219	1	1
3223	1	1
3224	1	1
3228	1	1
3229	1	1
3233	1	1
3234	1	1
3238	1	1
3239	1	1
3243	1	1
3244	1	1
3245	1	1
3246	1	1
3250	1	1
3251	1	1
3255	1	1
3259	1	1
3273		unreachable
3281	1	1
3282	1	1

---

Cond Coverage for Module : i2c_reg_top

	Total	Covered	Percent
Conditions	273	272	99.63
Logical	273	272	99.63
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T80,T81,T82
1	1	Covered	T1,T2,T3

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T83,T84,T85
1	0	Covered	T78,T86,T87

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T83,T84,T85
0	1	0	Covered	T78,T86,T87
1	0	0	Covered	T83,T84,T85

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T78,T86,T87
0	1	0	Covered	T77,T79,T80
1	0	0	Covered	T80,T81,T82

 LINE       2808
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_INTR_STATE_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2809
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_INTR_ENABLE_OFFSET)
            ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2810
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_INTR_TEST_OFFSET)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T33,T67,T68

 LINE       2811
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_ALERT_TEST_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T33,T67

 LINE       2812
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_CTRL_OFFSET)
            ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2813
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_STATUS_OFFSET)
            ----------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2814
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_RDATA_OFFSET)
            ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T4,T13

 LINE       2815
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_FDATA_OFFSET)
            ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T12

 LINE       2816
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_FIFO_CTRL_OFFSET)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2817
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_HOST_FIFO_CONFIG_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2818
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_FIFO_CONFIG_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2819
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_HOST_FIFO_STATUS_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T4,T33

 LINE       2820
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_FIFO_STATUS_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T7

 LINE       2821
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_OVRD_OFFSET)
            ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T33,T67

 LINE       2822
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_VAL_OFFSET)
            --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T33,T67

 LINE       2823
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING0_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2824
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING1_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2825
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING2_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2826
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING3_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2827
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING4_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2828
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMEOUT_CTRL_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2829
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_ID_OFFSET)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T7

 LINE       2830
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_ACQDATA_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T7

 LINE       2831
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TXDATA_OFFSET)
            ----------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T7

 LINE       2832
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_HOST_TIMEOUT_CTRL_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T8

 LINE       2835
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2835
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       2839
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[2] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[8] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T77,T78,T79

 LINE       2839
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b0011 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b0011 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b0011 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b0011 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1111 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T1,T2,T3
25 (addr_hit[24] & ((|(4'...	Covered	T33,T67,T68
24 (addr_hit[23] & ((|(4'...	Covered	T33,T67,T68
23 (addr_hit[22] & ((|(4'...	Covered	T1,T4,T7
22 (addr_hit[21] & ((|(4'...	Covered	T4,T33,T67
21 (addr_hit[20] & ((|(4'...	Covered	T4,T33,T67
20 (addr_hit[19] & ((|(4'...	Covered	T4,T33,T67
19 (addr_hit[18] & ((|(4'...	Covered	T4,T33,T67
18 (addr_hit[17] & ((|(4'...	Covered	T33,T67,T68
17 (addr_hit[16] & ((|(4'...	Covered	T33,T67,T68
16 (addr_hit[15] & ((|(4'...	Covered	T4,T33,T67
15 (addr_hit[14] & ((|(4'...	Covered	T4,T33,T67
14 (addr_hit[13] & ((|(4'...	Covered	T4,T33,T67
13 (addr_hit[12] & ((|(4'...	Covered	T1,T4,T7
12 (addr_hit[11] & ((|(4'...	Covered	T12,T4,T33
11 (addr_hit[10] & ((|(4'...	Covered	T4,T33,T67
10 (addr_hit[9] & ((|(4'b...	Covered	T12,T4,T33
9 (addr_hit[8] & ((|(4'b...	Covered	T4,T33,T67
8 (addr_hit[7] & ((|(4'b...	Covered	T33,T67,T68
7 (addr_hit[6] & ((|(4'b...	Covered	T12,T4,T13
6 (addr_hit[5] & ((|(4'b...	Covered	T1,T2,T3
5 (addr_hit[4] & ((|(4'b...	Covered	T4,T33,T67
4 (addr_hit[3] & ((|(4'b...	Covered	T33,T67,T68
3 (addr_hit[2] & ((|(4'b...	Covered	T33,T67,T68
2 (addr_hit[1] & ((|(4'b...	Covered	T4,T33,T67
1 (addr_hit[0] & ((|(4'b...	Covered	T1,T2,T3

 LINE       2839
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       2839
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T33,T67

 LINE       2839
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T33,T67,T68
1	1	Covered	T33,T67,T68

 LINE       2839
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T33,T67
1	1	Covered	T33,T67,T68

 LINE       2839
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T33,T67

 LINE       2839
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T12
1	1	Covered	T1,T2,T3

 LINE       2839
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T13,T10
1	1	Covered	T12,T4,T13

 LINE       2839
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T12
1	1	Covered	T33,T67,T68

 LINE       2839
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T33,T67

 LINE       2839
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T12,T4,T33

 LINE       2839
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T33,T67

 LINE       2839
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T33,T67,T68
1	1	Covered	T12,T4,T33

 LINE       2839
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T33,T67,T68
1	1	Covered	T1,T4,T7

 LINE       2839
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T33,T67
1	1	Covered	T4,T33,T67

 LINE       2839
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T33,T67,T68
1	1	Covered	T4,T33,T67

 LINE       2839
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T33,T67

 LINE       2839
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T33,T67,T68

 LINE       2839
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T33,T67,T68

 LINE       2839
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T33,T67

 LINE       2839
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T33,T67

 LINE       2839
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T33,T67

 LINE       2839
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T4,T33,T67

 LINE       2839
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T7
1	1	Covered	T1,T4,T7

 LINE       2839
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T7
1	1	Covered	T33,T67,T68

 LINE       2839
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T33,T67,T68

 LINE       2868
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T77,T81,T82
1	1	1	Covered	T1,T2,T3

 LINE       2887
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T88,T89,T90
1	1	1	Covered	T1,T2,T3

 LINE       2918
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T33,T67,T68
1	1	0	Covered	T81,T82,T91
1	1	1	Covered	T69,T70,T71

 LINE       2949
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T33,T67
1	1	0	Covered	T81,T82,T86
1	1	1	Covered	T92,T93,T94

 LINE       2952
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T80,T95,T96
1	1	1	Covered	T1,T2,T3

 LINE       2959
 EXPRESSION (addr_hit[5] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T87,T97
1	1	1	Covered	T1,T2,T3

 LINE       2960
 EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T12,T4,T13
1	1	0	Covered	T98
1	1	1	Covered	T12,T13,T10

 LINE       2961
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T12
1	1	0	Covered	T79,T81,T82
1	1	1	Covered	T2,T3,T12

 LINE       2974
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T81,T82,T95
1	1	1	Covered	T1,T2,T3

 LINE       2983
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T78,T81,T82
1	1	1	Covered	T1,T2,T3

 LINE       2988
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T81,T95,T91
1	1	1	Covered	T1,T2,T3

 LINE       2993
 EXPRESSION (addr_hit[11] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T12,T4,T33
1	1	0	Covered	T78,T99
1	1	1	Covered	T12,T9,T100

 LINE       2994
 EXPRESSION (addr_hit[12] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T4,T7
1	1	0	Covered	T78,T101
1	1	1	Covered	T1,T7,T8

 LINE       2995
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T33,T67
1	1	0	Covered	T82,T91,T102
1	1	1	Covered	T4,T5,T6

 LINE       3002
 EXPRESSION (addr_hit[14] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T33,T67
1	1	0	Covered	T86,T89,T101
1	1	1	Not Covered

 LINE       3003
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T77,T81,T82
1	1	1	Covered	T1,T2,T3

 LINE       3008
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T77,T79,T81
1	1	1	Covered	T1,T2,T3

 LINE       3013
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T79,T81,T82
1	1	1	Covered	T1,T2,T3

 LINE       3018
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T81,T95,T98
1	1	1	Covered	T1,T2,T3

 LINE       3023
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T82,T91,T96
1	1	1	Covered	T1,T2,T3

 LINE       3028
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T81,T95,T91
1	1	1	Covered	T1,T2,T3

 LINE       3033
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T4,T7
1	1	0	Covered	T77,T82,T91
1	1	1	Covered	T1,T7,T8

 LINE       3042
 EXPRESSION (addr_hit[22] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T4,T7
1	1	0	Covered	T103
1	1	1	Covered	T1,T7,T8

 LINE       3043
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T4,T7
1	1	0	Covered	T77,T79,T81
1	1	1	Covered	T1,T7,T8

 LINE       3046
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T7,T8
1	1	0	Covered	T82,T95,T91
1	1	1	Covered	T1,T7,T8

---

Branch Coverage for Module : i2c_reg_top

	Line No.	Total	Covered	Percent
Branches		31	31	100.00
TERNARY	2835	2	2	100.00
IF	68	3	3	100.00
CASE	3083	26	26	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	2835	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	68	if ((!rst_ni))
-2-:	70	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T83,T84,T85
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	3083	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : i2c_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	432219194	55713561	0	0
reAfterRv	432219194	55713376	0	0
rePulse	432219194	49369804	0	0
wePulse	432219194	6343572	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	432219194	55713561	0	0
T1	88454	41198	0	0
T2	15760	1335	0	0
T3	24452	11539	0	0
T4	1331	36	0	0
T7	969162	8680	0	0
T8	43540	4993	0	0
T10	277530	31119	0	0
T12	521309	50070	0	0
T13	91426	14692	0	0
T17	24709	11985	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	432219194	55713376	0	0
T1	88454	41198	0	0
T2	15760	1335	0	0
T3	24452	11539	0	0
T4	1331	36	0	0
T7	969162	8680	0	0
T8	43540	4993	0	0
T10	277530	31119	0	0
T12	521309	50070	0	0
T13	91426	14692	0	0
T17	24709	11985	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	432219194	49369804	0	0
T1	88454	40751	0	0
T2	15760	1318	0	0
T3	24452	11430	0	0
T4	1331	17	0	0
T7	969162	4054	0	0
T8	43540	4819	0	0
T10	277530	24423	0	0
T12	521309	48679	0	0
T13	91426	13999	0	0
T17	24709	11886	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	432219194	6343572	0	0
T1	88454	447	0	0
T2	15760	17	0	0
T3	24452	109	0	0
T4	1331	19	0	0
T7	969162	4626	0	0
T8	43540	174	0	0
T10	277530	6696	0	0
T12	521309	1391	0	0
T13	91426	693	0	0
T17	24709	99	0	0