Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	432219194	11065	0	0
ctrl_rd_A	432219194	1125	0	0
host_fifo_config_rd_A	432219194	4272	0	0
host_timeout_ctrl_rd_A	432219194	900	0	0
intr_enable_rd_A	432219194	2463	0	0
ovrd_rd_A	432219194	1706	0	0
target_fifo_config_rd_A	432219194	1034	0	0
target_id_rd_A	432219194	1173	0	0
timeout_ctrl_rd_A	432219194	1045	0	0
timing0_rd_A	432219194	1084	0	0
timing1_rd_A	432219194	1108	0	0
timing2_rd_A	432219194	1210	0	0
timing3_rd_A	432219194	874	0	0
timing4_rd_A	432219194	1144	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432219194	11065	0	0
T77	2559	60	0	0
T78	4417	2	0	0
T79	4366	154	0	0
T80	2880	23	0	0
T81	6543	548	0	0
T82	3531	409	0	0
T86	3788	2	0	0
T91	15840	636	0	0
T95	9358	613	0	0
T115	1787	8	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432219194	1125	0	0
T80	2880	20	0	0
T88	7099	23	0	0
T91	15840	53	0	0
T98	6602	91	0	0
T115	1787	7	0	0
T116	3453	17	0	0
T131	1551	15	0	0
T141	2286	6	0	0
T142	2116	10	0	0
T143	8392	15	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432219194	4272	0	0
T4	1331	0	0	0
T7	969162	0	0	0
T8	43540	0	0	0
T10	277530	0	0	0
T12	521309	176	0	0
T13	91426	0	0	0
T14	155078	0	0	0
T17	24709	0	0	0
T32	233456	0	0	0
T37	158041	0	0	0
T44	0	185	0	0
T100	0	146	0	0
T144	0	175	0	0
T145	0	65	0	0
T146	0	160	0	0
T147	0	197	0	0
T148	0	123	0	0
T149	0	165	0	0
T150	0	47	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432219194	900	0	0
T80	2880	18	0	0
T88	7099	9	0	0
T91	15840	33	0	0
T96	7403	8	0	0
T115	1787	9	0	0
T116	3453	20	0	0
T131	1551	12	0	0
T141	2286	8	0	0
T142	2116	1	0	0
T143	8392	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432219194	2463	0	0
T47	12870	0	0	0
T52	262462	0	0	0
T53	148836	0	0	0
T61	2780	0	0	0
T69	123862	17	0	0
T80	0	22	0	0
T100	365564	0	0	0
T146	0	22	0	0
T147	0	39	0	0
T151	0	34	0	0
T152	0	8	0	0
T153	0	17	0	0
T154	0	9	0	0
T155	0	11	0	0
T156	0	19	0	0
T157	239304	0	0	0
T158	13918	0	0	0
T159	139514	0	0	0
T160	3905	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432219194	1706	0	0
T5	1720	33	0	0
T23	968089	0	0	0
T35	151887	0	0	0
T42	3030	0	0	0
T61	2780	0	0	0
T69	123862	0	0	0
T92	953	0	0	0
T157	239304	0	0	0
T158	13918	0	0	0
T161	0	36	0	0
T162	0	38	0	0
T163	0	52	0	0
T164	0	56	0	0
T165	0	63	0	0
T166	0	57	0	0
T167	0	58	0	0
T168	0	59	0	0
T169	0	30	0	0
T170	49997	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432219194	1034	0	0
T80	2880	34	0	0
T88	7099	6	0	0
T91	15840	36	0	0
T96	7403	1	0	0
T115	1787	10	0	0
T116	3453	19	0	0
T131	1551	11	0	0
T141	2286	1	0	0
T142	2116	2	0	0
T143	8392	3	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432219194	1173	0	0
T80	2880	16	0	0
T88	7099	6	0	0
T91	15840	20	0	0
T96	7403	5	0	0
T115	1787	4	0	0
T116	3453	34	0	0
T131	1551	17	0	0
T141	2286	11	0	0
T142	2116	6	0	0
T143	8392	7	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432219194	1045	0	0
T80	2880	24	0	0
T88	7099	10	0	0
T91	15840	55	0	0
T98	6602	86	0	0
T115	1787	12	0	0
T116	3453	10	0	0
T128	46757	471	0	0
T131	1551	16	0	0
T141	2286	1	0	0
T142	2116	11	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432219194	1084	0	0
T80	2880	41	0	0
T91	15840	52	0	0
T96	7403	9	0	0
T98	6602	61	0	0
T115	1787	8	0	0
T116	3453	18	0	0
T131	1551	19	0	0
T141	2286	4	0	0
T142	2116	9	0	0
T143	8392	10	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432219194	1108	0	0
T80	2880	21	0	0
T88	7099	11	0	0
T91	15840	41	0	0
T96	7403	8	0	0
T115	1787	8	0	0
T116	3453	18	0	0
T131	1551	11	0	0
T141	2286	5	0	0
T142	2116	8	0	0
T143	8392	4	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432219194	1210	0	0
T80	2880	33	0	0
T88	7099	7	0	0
T91	15840	36	0	0
T96	7403	10	0	0
T98	6602	51	0	0
T115	1787	7	0	0
T116	3453	30	0	0
T131	1551	18	0	0
T141	2286	8	0	0
T143	8392	11	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432219194	874	0	0
T80	2880	21	0	0
T88	7099	5	0	0
T91	15840	29	0	0
T98	6602	59	0	0
T115	1787	4	0	0
T116	3453	9	0	0
T128	46757	402	0	0
T131	1551	12	0	0
T141	2286	2	0	0
T143	8392	10	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432219194	1144	0	0
T80	2880	29	0	0
T88	7099	27	0	0
T91	15840	38	0	0
T96	7403	23	0	0
T115	1787	12	0	0
T116	3453	21	0	0
T131	1551	11	0	0
T141	2286	6	0	0
T142	2116	17	0	0
T143	8392	11	0	0