Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	23909	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

36756

1

T1

253

T2

10

T3

2674

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	31704	1			T1	106		T2	11		T3	2173
values[0x0]	14263	1			T1	68		T2	8		T3	1073
values[0x1]	14698	1			T1	80		T2	3		T3	1096

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	17065	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

43600

1

T1

254

T2

12

T3

2973

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	195	1			T3	11		T12	13		T13	1
valid_sources[0x01]	361	1			T3	26		T4	6		T7	2
valid_sources[0x02]	216	1			T3	18		T7	8		T12	4
valid_sources[0x03]	209	1			T3	12		T7	2		T12	14
valid_sources[0x04]	238	1			T3	15		T4	8		T7	1
valid_sources[0x05]	490	1			T1	4		T3	12		T4	1
valid_sources[0x06]	297	1			T3	18		T4	1		T7	1
valid_sources[0x07]	213	1			T3	16		T12	6		T13	2
valid_sources[0x08]	397	1			T3	17		T7	1		T12	8
valid_sources[0x09]	226	1			T3	13		T7	3		T12	12
valid_sources[0x0a]	144	1			T3	8		T7	3		T12	7
valid_sources[0x0b]	184	1			T3	16		T7	5		T12	5
valid_sources[0x0c]	280	1			T1	3		T3	16		T7	6
valid_sources[0x0d]	218	1			T1	13		T3	16		T7	3
valid_sources[0x0e]	192	1			T3	18		T7	6		T12	8
valid_sources[0x0f]	249	1			T3	18		T4	10		T7	3
valid_sources[0x10]	211	1			T3	16		T12	20		T13	2
valid_sources[0x11]	285	1			T3	21		T4	7		T7	7
valid_sources[0x12]	245	1			T1	6		T3	19		T4	2
valid_sources[0x13]	160	1			T3	11		T4	1		T7	1
valid_sources[0x14]	202	1			T3	20		T4	3		T7	5
valid_sources[0x15]	213	1			T3	26		T7	1		T12	9
valid_sources[0x16]	259	1			T3	15		T4	2		T12	3
valid_sources[0x17]	208	1			T2	4		T3	13		T4	1
valid_sources[0x18]	191	1			T3	22		T7	4		T12	9
valid_sources[0x19]	185	1			T3	22		T4	3		T7	6
valid_sources[0x1a]	224	1			T1	11		T3	15		T4	3
valid_sources[0x1b]	290	1			T3	20		T4	1		T7	5
valid_sources[0x1c]	201	1			T3	25		T7	3		T12	10
valid_sources[0x1d]	378	1			T3	16		T7	2		T12	9
valid_sources[0x1e]	303	1			T3	14		T4	1		T7	1
valid_sources[0x1f]	202	1			T1	21		T3	13		T4	5
valid_sources[0x20]	289	1			T3	16		T4	8		T7	6
valid_sources[0x21]	212	1			T3	9		T4	1		T7	3
valid_sources[0x22]	201	1			T3	17		T4	8		T12	9
valid_sources[0x23]	308	1			T3	13		T7	2		T12	8
valid_sources[0x24]	198	1			T3	10		T4	5		T12	6
valid_sources[0x25]	253	1			T3	21		T7	1		T12	12
valid_sources[0x26]	183	1			T3	10		T12	6		T13	2
valid_sources[0x27]	255	1			T3	12		T4	2		T7	2
valid_sources[0x28]	264	1			T3	14		T7	2		T12	5
valid_sources[0x29]	198	1			T3	16		T12	6		T24	1
valid_sources[0x2a]	396	1			T3	12		T7	2		T12	12
valid_sources[0x2b]	227	1			T3	21		T4	7		T7	6
valid_sources[0x2c]	209	1			T3	12		T7	2		T12	4
valid_sources[0x2d]	269	1			T3	24		T7	1		T12	3
valid_sources[0x2e]	196	1			T1	10		T3	16		T4	5
valid_sources[0x2f]	163	1			T3	20		T4	4		T7	1
valid_sources[0x30]	162	1			T3	23		T4	10		T12	8
valid_sources[0x31]	248	1			T3	17		T12	9		T13	2
valid_sources[0x32]	345	1			T1	4		T3	11		T4	9
valid_sources[0x33]	207	1			T2	4		T3	26		T12	14
valid_sources[0x34]	312	1			T1	13		T3	18		T7	5
valid_sources[0x35]	308	1			T3	23		T4	2		T12	9
valid_sources[0x36]	212	1			T3	10		T4	3		T7	2
valid_sources[0x37]	195	1			T3	26		T4	2		T7	1
valid_sources[0x38]	232	1			T3	17		T7	3		T12	8
valid_sources[0x39]	170	1			T3	18		T4	5		T12	14
valid_sources[0x3a]	203	1			T3	22		T12	4		T5	12
valid_sources[0x3b]	193	1			T3	17		T4	5		T7	1
valid_sources[0x3c]	209	1			T3	19		T7	3		T12	8
valid_sources[0x3d]	226	1			T3	20		T4	1		T7	1
valid_sources[0x3e]	117	1			T3	9		T7	1		T12	10
valid_sources[0x3f]	220	1			T3	15		T4	1		T7	2
valid_sources[0x40]	260	1			T3	22		T7	2		T12	8
valid_sources[0x41]	216	1			T3	13		T7	2		T12	10
valid_sources[0x42]	380	1			T3	16		T7	1		T12	7
valid_sources[0x43]	276	1			T3	16		T12	9		T13	1
valid_sources[0x44]	483	1			T3	23		T4	1		T7	3
valid_sources[0x45]	173	1			T3	14		T4	4		T7	2
valid_sources[0x46]	224	1			T3	16		T4	4		T12	8
valid_sources[0x47]	188	1			T3	16		T7	2		T12	5
valid_sources[0x48]	181	1			T3	15		T7	1		T12	9
valid_sources[0x49]	168	1			T1	8		T3	8		T7	1
valid_sources[0x4a]	237	1			T3	14		T7	2		T12	8
valid_sources[0x4b]	375	1			T3	13		T4	1		T7	6
valid_sources[0x4c]	240	1			T3	22		T4	3		T7	3
valid_sources[0x4d]	190	1			T3	20		T4	5		T7	1
valid_sources[0x4e]	200	1			T3	19		T7	16		T12	7
valid_sources[0x4f]	209	1			T3	19		T4	5		T12	5
valid_sources[0x50]	269	1			T3	14		T7	3		T12	12
valid_sources[0x51]	259	1			T3	13		T4	3		T7	1
valid_sources[0x52]	339	1			T3	22		T4	2		T7	3
valid_sources[0x53]	265	1			T3	14		T4	2		T7	1
valid_sources[0x54]	252	1			T3	16		T7	1		T12	5
valid_sources[0x55]	232	1			T3	13		T7	5		T12	6
valid_sources[0x56]	191	1			T3	16		T12	16		T13	1
valid_sources[0x57]	220	1			T3	15		T7	1		T12	10
valid_sources[0x58]	318	1			T3	9		T4	4		T7	3
valid_sources[0x59]	183	1			T1	4		T3	21		T7	5
valid_sources[0x5a]	335	1			T3	27		T7	5		T12	9
valid_sources[0x5b]	170	1			T3	14		T4	2		T7	2
valid_sources[0x5c]	346	1			T3	14		T4	1		T7	2
valid_sources[0x5d]	154	1			T3	14		T4	6		T7	2
valid_sources[0x5e]	222	1			T3	16		T4	5		T12	6
valid_sources[0x5f]	269	1			T3	14		T4	5		T7	5
valid_sources[0x60]	242	1			T3	20		T4	9		T7	5
valid_sources[0x61]	247	1			T2	4		T3	14		T4	10
valid_sources[0x62]	198	1			T3	12		T12	6		T13	1
valid_sources[0x63]	176	1			T3	18		T4	1		T7	3
valid_sources[0x64]	206	1			T3	12		T4	12		T12	9
valid_sources[0x65]	191	1			T3	20		T4	6		T12	6
valid_sources[0x66]	247	1			T3	7		T7	3		T12	9
valid_sources[0x67]	188	1			T3	13		T12	13		T5	10
valid_sources[0x68]	198	1			T3	8		T4	1		T12	9
valid_sources[0x69]	218	1			T3	17		T12	18		T26	1
valid_sources[0x6a]	200	1			T3	28		T4	3		T12	5
valid_sources[0x6b]	175	1			T3	14		T4	3		T7	2
valid_sources[0x6c]	210	1			T1	2		T3	18		T4	2
valid_sources[0x6d]	233	1			T1	8		T3	18		T4	12
valid_sources[0x6e]	211	1			T3	27		T4	19		T7	4
valid_sources[0x6f]	228	1			T3	26		T7	4		T12	10
valid_sources[0x70]	195	1			T3	23		T7	2		T12	13
valid_sources[0x71]	192	1			T3	12		T7	1		T12	9
valid_sources[0x72]	244	1			T3	23		T7	3		T12	8
valid_sources[0x73]	260	1			T3	22		T4	2		T7	4
valid_sources[0x74]	304	1			T3	15		T4	3		T7	3
valid_sources[0x75]	179	1			T3	17		T4	11		T7	3
valid_sources[0x76]	239	1			T3	15		T4	4		T7	1
valid_sources[0x77]	353	1			T3	12		T7	4		T12	8
valid_sources[0x78]	139	1			T3	13		T7	2		T12	5
valid_sources[0x79]	202	1			T3	18		T4	3		T12	5
valid_sources[0x7a]	276	1			T1	21		T3	15		T7	2
valid_sources[0x7b]	177	1			T3	16		T12	9		T11	3
valid_sources[0x7c]	319	1			T3	14		T7	1		T12	12
valid_sources[0x7d]	267	1			T3	22		T7	3		T12	4
valid_sources[0x7e]	196	1			T3	13		T4	2		T7	2
valid_sources[0x7f]	366	1			T3	18		T7	7		T12	5
valid_sources[0x80]	312	1			T3	18		T4	2		T7	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

13646

1

T1

105

T2

5

T3

1075

values[0x0]

all_enables

biggest_size

11941

1

T1

68

T2

5

T3

833

values[0x1]

all_enables

biggest_size

11169

1

T1

80

T3

766

T4

78