Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
33.33	0.00	0.00	100.00				dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	665013	9427	0	0
ctrl_rd_A	665013	2122	0	0
host_fifo_config_rd_A	665013	1747	0	0
host_timeout_ctrl_rd_A	665013	1481	0	0
intr_enable_rd_A	665013	4769	0	0
ovrd_rd_A	665013	2035	0	0
target_fifo_config_rd_A	665013	1713	0	0
target_id_rd_A	665013	2225	0	0
timeout_ctrl_rd_A	665013	1635	0	0
timing0_rd_A	665013	1723	0	0
timing1_rd_A	665013	1802	0	0
timing2_rd_A	665013	1811	0	0
timing3_rd_A	665013	1934	0	0
timing4_rd_A	665013	1729	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665013	9427	0	0
T4	4848	4	0	0
T5	6521	1	0	0
T6	0	118	0	0
T7	11306	587	0	0
T8	1954	0	0	0
T9	1591	0	0	0
T10	1866	0	0	0
T12	5240	0	0	0
T13	2391	0	0	0
T14	1808	0	0	0
T15	0	23	0	0
T16	0	847	0	0
T17	0	23	0	0
T18	0	24	0	0
T19	0	3	0	0
T23	1794	0	0	0
T24	0	2	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665013	2122	0	0
T5	6521	60	0	0
T6	2198	0	0	0
T8	1954	0	0	0
T9	1591	0	0	0
T10	1866	0	0	0
T11	1869	0	0	0
T13	2391	0	0	0
T14	1808	0	0	0
T18	0	11	0	0
T19	0	90	0	0
T20	0	35	0	0
T21	0	12	0	0
T23	1794	0	0	0
T27	0	31	0	0
T30	0	15	0	0
T32	0	1	0	0
T57	0	92	0	0
T58	0	17	0	0
T59	1226	0	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665013	1747	0	0
T5	6521	51	0	0
T6	2198	0	0	0
T8	1954	0	0	0
T9	1591	0	0	0
T10	1866	0	0	0
T11	1869	0	0	0
T13	2391	0	0	0
T14	1808	0	0	0
T18	0	20	0	0
T19	0	56	0	0
T20	0	31	0	0
T21	0	24	0	0
T23	1794	0	0	0
T27	0	32	0	0
T32	0	2	0	0
T57	0	92	0	0
T58	0	35	0	0
T59	1226	0	0	0
T60	0	27	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665013	1481	0	0
T5	6521	41	0	0
T6	2198	0	0	0
T8	1954	0	0	0
T9	1591	0	0	0
T10	1866	0	0	0
T11	1869	0	0	0
T13	2391	0	0	0
T14	1808	0	0	0
T18	0	16	0	0
T19	0	43	0	0
T20	0	16	0	0
T21	0	14	0	0
T23	1794	0	0	0
T30	0	4	0	0
T32	0	7	0	0
T57	0	116	0	0
T58	0	2	0	0
T59	1226	0	0	0
T60	0	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665013	4769	0	0
T2	1005	5	0	0
T3	10409	0	0	0
T4	4848	0	0	0
T5	6521	244	0	0
T7	11306	0	0	0
T8	1954	4	0	0
T9	1591	0	0	0
T10	0	15	0	0
T11	0	10	0	0
T12	5240	0	0	0
T13	2391	0	0	0
T14	1808	0	0	0
T18	0	120	0	0
T19	0	447	0	0
T27	0	40	0	0
T30	0	29	0	0
T59	0	2	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665013	2035	0	0
T5	6521	101	0	0
T6	2198	0	0	0
T8	1954	0	0	0
T9	1591	0	0	0
T10	1866	0	0	0
T11	1869	0	0	0
T13	2391	0	0	0
T14	1808	0	0	0
T18	0	23	0	0
T19	0	78	0	0
T20	0	27	0	0
T21	0	21	0	0
T23	1794	0	0	0
T27	0	13	0	0
T30	0	1	0	0
T32	0	9	0	0
T57	0	94	0	0
T58	0	46	0	0
T59	1226	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665013	1713	0	0
T5	6521	66	0	0
T6	2198	0	0	0
T8	1954	0	0	0
T9	1591	0	0	0
T10	1866	0	0	0
T11	1869	0	0	0
T13	2391	0	0	0
T14	1808	0	0	0
T18	0	28	0	0
T19	0	40	0	0
T20	0	23	0	0
T21	0	11	0	0
T23	1794	0	0	0
T27	0	5	0	0
T30	0	2	0	0
T57	0	90	0	0
T58	0	11	0	0
T59	1226	0	0	0
T60	0	30	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665013	2225	0	0
T5	6521	80	0	0
T6	2198	0	0	0
T8	1954	0	0	0
T9	1591	0	0	0
T10	1866	0	0	0
T11	1869	0	0	0
T13	2391	0	0	0
T14	1808	0	0	0
T18	0	27	0	0
T19	0	146	0	0
T20	0	21	0	0
T21	0	5	0	0
T23	1794	0	0	0
T27	0	22	0	0
T30	0	11	0	0
T32	0	25	0	0
T57	0	79	0	0
T58	0	13	0	0
T59	1226	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665013	1635	0	0
T5	6521	48	0	0
T6	2198	0	0	0
T8	1954	0	0	0
T9	1591	0	0	0
T10	1866	0	0	0
T11	1869	0	0	0
T13	2391	0	0	0
T14	1808	0	0	0
T18	0	15	0	0
T19	0	83	0	0
T20	0	17	0	0
T21	0	30	0	0
T23	1794	0	0	0
T30	0	10	0	0
T32	0	8	0	0
T57	0	81	0	0
T58	0	14	0	0
T59	1226	0	0	0
T60	0	17	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665013	1723	0	0
T5	6521	67	0	0
T6	2198	0	0	0
T8	1954	0	0	0
T9	1591	0	0	0
T10	1866	0	0	0
T11	1869	0	0	0
T13	2391	0	0	0
T14	1808	0	0	0
T18	0	23	0	0
T19	0	84	0	0
T20	0	18	0	0
T21	0	3	0	0
T23	1794	0	0	0
T27	0	16	0	0
T30	0	3	0	0
T32	0	9	0	0
T57	0	94	0	0
T58	0	13	0	0
T59	1226	0	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665013	1802	0	0
T5	6521	79	0	0
T6	2198	0	0	0
T8	1954	0	0	0
T9	1591	0	0	0
T10	1866	0	0	0
T11	1869	0	0	0
T13	2391	0	0	0
T14	1808	0	0	0
T18	0	23	0	0
T19	0	67	0	0
T20	0	26	0	0
T21	0	30	0	0
T23	1794	0	0	0
T27	0	7	0	0
T30	0	10	0	0
T32	0	5	0	0
T57	0	114	0	0
T58	0	18	0	0
T59	1226	0	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665013	1811	0	0
T5	6521	43	0	0
T6	2198	0	0	0
T8	1954	0	0	0
T9	1591	0	0	0
T10	1866	0	0	0
T11	1869	0	0	0
T13	2391	0	0	0
T14	1808	0	0	0
T18	0	16	0	0
T19	0	54	0	0
T20	0	28	0	0
T21	0	28	0	0
T23	1794	0	0	0
T27	0	26	0	0
T30	0	1	0	0
T32	0	4	0	0
T57	0	103	0	0
T58	0	62	0	0
T59	1226	0	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665013	1934	0	0
T5	6521	54	0	0
T6	2198	0	0	0
T8	1954	0	0	0
T9	1591	0	0	0
T10	1866	0	0	0
T11	1869	0	0	0
T13	2391	0	0	0
T14	1808	0	0	0
T18	0	32	0	0
T19	0	83	0	0
T20	0	43	0	0
T21	0	10	0	0
T23	1794	0	0	0
T27	0	30	0	0
T30	0	4	0	0
T32	0	10	0	0
T57	0	107	0	0
T59	1226	0	0	0
T60	0	28	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665013	1729	0	0
T5	6521	67	0	0
T6	2198	0	0	0
T8	1954	0	0	0
T9	1591	0	0	0
T10	1866	0	0	0
T11	1869	0	0	0
T13	2391	0	0	0
T14	1808	0	0	0
T18	0	9	0	0
T19	0	69	0	0
T20	0	26	0	0
T21	0	4	0	0
T23	1794	0	0	0
T27	0	26	0	0
T30	0	2	0	0
T32	0	4	0	0
T57	0	83	0	0
T58	0	25	0	0
T59	1226	0	0	0