Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

157718

1

T18

137

T13

523

T15

257

ack

13597

1

T18

19

T13

15

T14

11

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	633	1			T13	1		T15	1		T12	1
high	35341	1			T18	51		T13	113		T14	2
med	64269	1			T18	49		T13	198		T14	3
sml	70418	1			T18	55		T13	224		T14	6
all_zero	654	1			T18	1		T13	2		T15	1

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

85343

1

T18

91

T13

266

T14

3

auto[1]

85972

1

T18

65

T13

272

T14

8

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

117790

1

T18

121

T13

364

T14

11

auto[1]

53525

1

T18

35

T13

174

T15

71

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

164301

1

T18

156

T13

530

T14

6

auto[1]

7014

1

T13

8

T14

5

T12

32

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

162216

1

T18

137

T13

526

T14

5

auto[1]

9099

1

T18

19

T13

12

T14

6

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

162932

1

T18

137

T13

529

T14

6

auto[1]

8383

1

T18

19

T13

9

T14

5

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

85343

1

T18

91

T13

266

T14

3

auto[1]

85972

1

T18

65

T13

272

T14

8

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

117790

1

T18

121

T13

364

T14

11

auto[1]

53525

1

T18

35

T13

174

T15

71

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

164301

1

T18

156

T13

530

T14

6

auto[1]

7014

1

T13

8

T14

5

T12

32

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

162216

1

T18

137

T13

526

T14

5

auto[1]

9099

1

T18

19

T13

12

T14

6

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

162932

1

T18

137

T13

529

T14

6

auto[1]

8383

1

T18

19

T13

9

T14

5

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

8

1

T124

1

T189

1

T190

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

2

1

T191

1

T192

1

-

-

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

2

1

T124

1

T193

1

-

-

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

271

1

T30

4

T124

1

T194

2

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

122

1

T30

2

T124

1

T40

2

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

128

1

T30

3

T124

1

T194

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

514

1

T30

7

T124

2

T194

4

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

232

1

T30

4

T124

2

T40

2

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

238

1

T13

1

T30

2

T124

3

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

504

1

T13

1

T30

11

T124

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

250

1

T56

1

T30

2

T124

2

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

279

1

T13

2

T56

1

T29

1

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

6

1

T195

1

T196

1

T197

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

6

1

T198

1

T130

1

T199

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

5

1

T200

1

T201

1

T202

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	50306	1			T18	45		T13	171		T15	82
write_address_byte	9099	1			T18	19		T13	12		T14	6
read_with_ack	1942	1			T13	2		T12	13		T56	6
read_with_nack	5072	1			T13	6		T14	5		T12	19
stop_byte	8383	1			T18	19		T13	9		T14	5
write_address_byte_nak	4422	1			T13	7		T56	4		T29	3
data_byte_nack	157718	1			T18	137		T13	523		T15	257
stop_byte_nack	4948	1			T18	19		T13	7		T15	2
nakok_byte_nack	79181	1			T18	59		T13	265		T15	147
nakok_addr_byte_nack	2246	1			T13	2		T56	2		T29	1