Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	37221736	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

12643619

1

T1

142

T2

6

T3

326

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	44561788	1			T1	307		T2	1		T3	3097
values[0x0]	2650657	1			T1	90		T2	6		T3	231
values[0x1]	2652910	1			T1	77		T2	5		T3	206

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27103118	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

22762237

1

T1

240

T2

6

T3

1698

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	160908	1			T3	13		T13	8		T14	58
valid_sources[0x01]	163731	1			T3	21		T7	1		T13	4
valid_sources[0x02]	174761	1			T3	14		T17	1		T7	1
valid_sources[0x03]	190180	1			T3	12		T7	1		T13	3
valid_sources[0x04]	194903	1			T3	18		T7	4		T13	3
valid_sources[0x05]	200995	1			T3	9		T7	2		T13	4
valid_sources[0x06]	220482	1			T3	15		T4	1		T7	2
valid_sources[0x07]	187231	1			T1	1		T3	16		T7	1
valid_sources[0x08]	161072	1			T3	15		T7	5		T13	1
valid_sources[0x09]	174543	1			T3	10		T7	8		T13	2
valid_sources[0x0a]	177444	1			T1	13		T3	16		T7	5
valid_sources[0x0b]	249966	1			T1	1		T3	16		T17	1
valid_sources[0x0c]	176443	1			T3	15		T7	3		T13	2
valid_sources[0x0d]	201219	1			T3	15		T13	2		T14	62
valid_sources[0x0e]	185986	1			T3	9		T7	5		T13	6
valid_sources[0x0f]	336065	1			T1	1		T3	13		T7	3
valid_sources[0x10]	230105	1			T3	16		T7	1		T13	33371
valid_sources[0x11]	172920	1			T3	12		T17	3		T7	6
valid_sources[0x12]	158756	1			T3	10		T7	2		T13	5
valid_sources[0x13]	190209	1			T1	16		T3	17		T4	1
valid_sources[0x14]	179392	1			T3	9		T4	2		T13	3
valid_sources[0x15]	312237	1			T3	12		T7	4		T13	7
valid_sources[0x16]	179458	1			T3	24		T7	6		T13	9
valid_sources[0x17]	171342	1			T1	1		T3	14		T7	1
valid_sources[0x18]	275863	1			T3	22		T7	1		T13	13
valid_sources[0x19]	163549	1			T3	7		T17	2		T7	2
valid_sources[0x1a]	184735	1			T1	1		T3	8		T7	1
valid_sources[0x1b]	185771	1			T1	1		T3	18		T7	1
valid_sources[0x1c]	166240	1			T3	4		T7	1		T13	10
valid_sources[0x1d]	161671	1			T3	20		T7	3		T13	4
valid_sources[0x1e]	193075	1			T1	2		T3	9		T4	1
valid_sources[0x1f]	177137	1			T3	6		T17	1		T7	6
valid_sources[0x20]	172329	1			T1	1		T3	14		T17	1
valid_sources[0x21]	168788	1			T3	18		T7	2		T13	6
valid_sources[0x22]	166656	1			T3	25		T7	1		T13	5
valid_sources[0x23]	173080	1			T3	4		T13	5		T14	35
valid_sources[0x24]	158198	1			T3	19		T4	2		T13	6
valid_sources[0x25]	171827	1			T3	8		T17	1		T13	5
valid_sources[0x26]	180444	1			T3	10		T4	1		T17	2
valid_sources[0x27]	231634	1			T3	4		T13	5		T14	41
valid_sources[0x28]	182572	1			T1	1		T3	19		T7	2
valid_sources[0x29]	161059	1			T3	20		T13	8		T14	30
valid_sources[0x2a]	176129	1			T3	14		T4	1		T7	1
valid_sources[0x2b]	197570	1			T3	8		T17	1		T7	1
valid_sources[0x2c]	164529	1			T3	11		T17	1		T7	6
valid_sources[0x2d]	189655	1			T3	21		T17	2		T7	2
valid_sources[0x2e]	666907	1			T1	1		T3	5		T7	1
valid_sources[0x2f]	176775	1			T3	13		T7	1		T13	5
valid_sources[0x30]	162619	1			T3	14		T17	4		T7	2
valid_sources[0x31]	192069	1			T3	14		T17	6		T7	5
valid_sources[0x32]	168092	1			T3	8		T7	6		T13	6
valid_sources[0x33]	175442	1			T3	10		T4	1		T17	1
valid_sources[0x34]	193524	1			T3	18		T13	3		T14	73
valid_sources[0x35]	186261	1			T3	27		T7	5		T13	7
valid_sources[0x36]	221484	1			T1	1		T3	19		T7	2
valid_sources[0x37]	167040	1			T3	6		T7	4		T13	2
valid_sources[0x38]	170095	1			T3	11		T7	1		T13	3
valid_sources[0x39]	196484	1			T1	13		T3	18		T7	1
valid_sources[0x3a]	171376	1			T1	51		T3	13		T17	1
valid_sources[0x3b]	175877	1			T3	8		T13	4		T14	45
valid_sources[0x3c]	238524	1			T3	9		T17	1		T7	1
valid_sources[0x3d]	170218	1			T3	18		T7	1		T13	5
valid_sources[0x3e]	174036	1			T3	16		T7	3		T13	8
valid_sources[0x3f]	175461	1			T3	10		T13	6		T14	71
valid_sources[0x40]	190079	1			T3	21		T7	2		T13	6
valid_sources[0x41]	181335	1			T3	9		T7	5		T13	5
valid_sources[0x42]	171970	1			T3	10		T7	3		T13	6
valid_sources[0x43]	416589	1			T3	11		T13	3		T14	91
valid_sources[0x44]	181866	1			T3	13		T7	4		T13	4
valid_sources[0x45]	166628	1			T3	19		T7	3		T13	3
valid_sources[0x46]	194627	1			T3	10		T13	3		T14	30
valid_sources[0x47]	162806	1			T3	8		T17	2		T7	2
valid_sources[0x48]	164831	1			T3	21		T17	9		T7	5
valid_sources[0x49]	161598	1			T3	8		T17	2		T7	1
valid_sources[0x4a]	169309	1			T3	28		T7	1		T13	6
valid_sources[0x4b]	161542	1			T3	7		T17	3		T7	3
valid_sources[0x4c]	167760	1			T3	12		T17	1		T7	1
valid_sources[0x4d]	201708	1			T3	11		T7	1		T13	5
valid_sources[0x4e]	203511	1			T3	17		T17	2		T7	4
valid_sources[0x4f]	176700	1			T3	18		T7	3		T13	3
valid_sources[0x50]	201049	1			T3	19		T7	7		T13	3
valid_sources[0x51]	183965	1			T2	1		T3	14		T4	1
valid_sources[0x52]	178199	1			T1	60		T3	13		T13	9
valid_sources[0x53]	177712	1			T3	5		T17	2		T7	1
valid_sources[0x54]	164311	1			T3	12		T7	3		T13	22
valid_sources[0x55]	196146	1			T3	8		T7	3		T13	11
valid_sources[0x56]	208603	1			T3	22		T7	1		T13	4
valid_sources[0x57]	171622	1			T3	6		T7	3		T13	11
valid_sources[0x58]	251950	1			T3	17		T13	5		T14	73
valid_sources[0x59]	176199	1			T3	11		T7	3		T13	3
valid_sources[0x5a]	183459	1			T3	15		T17	4		T7	1
valid_sources[0x5b]	195731	1			T1	46		T3	12		T4	1
valid_sources[0x5c]	172297	1			T1	1		T3	17		T4	1
valid_sources[0x5d]	170479	1			T3	18		T7	1		T13	11
valid_sources[0x5e]	174356	1			T3	12		T4	1		T7	1
valid_sources[0x5f]	162449	1			T3	12		T4	1		T13	4
valid_sources[0x60]	189917	1			T1	1		T3	14		T17	3
valid_sources[0x61]	185064	1			T3	11		T7	4		T13	4
valid_sources[0x62]	176127	1			T1	1		T3	20		T7	2
valid_sources[0x63]	171704	1			T3	10		T17	2		T7	1
valid_sources[0x64]	182894	1			T3	7		T17	1		T7	8
valid_sources[0x65]	178300	1			T3	15		T17	1		T7	4
valid_sources[0x66]	187007	1			T2	1		T3	23		T7	2
valid_sources[0x67]	160189	1			T3	17		T7	6		T13	9
valid_sources[0x68]	545095	1			T3	19		T7	3		T13	6
valid_sources[0x69]	172840	1			T3	16		T7	3		T13	10
valid_sources[0x6a]	179461	1			T3	19		T7	6		T13	5
valid_sources[0x6b]	187773	1			T3	8		T7	5		T13	6
valid_sources[0x6c]	159514	1			T3	22		T4	1		T13	16
valid_sources[0x6d]	183898	1			T3	11		T4	1		T7	1
valid_sources[0x6e]	188365	1			T3	15		T7	9		T13	4
valid_sources[0x6f]	168778	1			T3	6		T4	1		T7	2
valid_sources[0x70]	162426	1			T1	1		T3	14		T4	1
valid_sources[0x71]	184928	1			T3	14		T17	3		T7	2
valid_sources[0x72]	165155	1			T3	8		T7	3		T13	6
valid_sources[0x73]	187667	1			T3	11		T4	1		T7	3
valid_sources[0x74]	176880	1			T3	9		T7	3		T13	4
valid_sources[0x75]	169401	1			T1	1		T3	11		T17	5
valid_sources[0x76]	176356	1			T1	31		T3	12		T17	2
valid_sources[0x77]	173084	1			T3	13		T7	4		T13	2
valid_sources[0x78]	166640	1			T1	1		T3	11		T7	2
valid_sources[0x79]	169960	1			T3	13		T17	1		T13	17
valid_sources[0x7a]	174553	1			T3	11		T13	2		T14	44
valid_sources[0x7b]	183549	1			T3	14		T7	3		T13	7
valid_sources[0x7c]	183447	1			T3	6		T13	5		T14	39
valid_sources[0x7d]	173233	1			T3	14		T4	1		T17	4
valid_sources[0x7e]	206654	1			T1	1		T3	16		T7	1
valid_sources[0x7f]	178514	1			T1	1		T3	10		T17	1
valid_sources[0x80]	191682	1			T3	11		T7	2		T13	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

10538743

1

T1

27

T3

169

T4

4

values[0x0]

all_enables

biggest_size

1342828

1

T1

65

T2

5

T3

94

values[0x1]

all_enables

biggest_size

762048

1

T1

50

T2

1

T3

63