Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	424227666	9211	0	0
ctrl_rd_A	424227666	2186	0	0
host_fifo_config_rd_A	424227666	6490	0	0
host_timeout_ctrl_rd_A	424227666	1908	0	0
intr_enable_rd_A	424227666	5556	0	0
ovrd_rd_A	424227666	2893	0	0
target_fifo_config_rd_A	424227666	2118	0	0
target_id_rd_A	424227666	2574	0	0
timeout_ctrl_rd_A	424227666	2114	0	0
timing0_rd_A	424227666	2089	0	0
timing1_rd_A	424227666	2009	0	0
timing2_rd_A	424227666	2049	0	0
timing3_rd_A	424227666	2158	0	0
timing4_rd_A	424227666	2256	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424227666	9211	0	0
T58	6136	300	0	0
T59	1357	33	0	0
T60	3243	9	0	0
T61	6135	1	0	0
T62	7568	324	0	0
T63	12779	6	0	0
T64	1715	17	0	0
T69	2128	44	0	0
T85	2712	16	0	0
T98	2909	13	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424227666	2186	0	0
T60	3243	24	0	0
T61	6135	53	0	0
T62	7568	6	0	0
T63	12779	127	0	0
T84	3039	31	0	0
T85	2712	10	0	0
T98	2909	12	0	0
T113	3288	23	0	0
T115	2005	14	0	0
T117	2580	16	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424227666	6490	0	0
T20	964901	0	0	0
T25	115057	0	0	0
T28	127510	0	0	0
T36	0	113	0	0
T40	0	456	0	0
T44	957277	0	0	0
T121	0	173	0	0
T124	398625	157	0	0
T125	0	168	0	0
T126	0	216	0	0
T127	0	211	0	0
T128	0	141	0	0
T129	0	334	0	0
T130	0	205	0	0
T131	43957	0	0	0
T132	391634	0	0	0
T133	11920	0	0	0
T134	173530	0	0	0
T135	103578	0	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424227666	1908	0	0
T60	3243	15	0	0
T61	6135	48	0	0
T62	7568	10	0	0
T63	12779	79	0	0
T84	3039	6	0	0
T85	2712	1	0	0
T98	2909	14	0	0
T113	3288	16	0	0
T115	2005	2	0	0
T117	2580	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424227666	5556	0	0
T36	0	27	0	0
T40	192534	24	0	0
T121	0	18	0	0
T123	0	12	0	0
T130	0	32	0	0
T136	0	25	0	0
T137	0	3	0	0
T138	0	4	0	0
T139	0	22	0	0
T140	0	16	0	0
T141	604414	0	0	0
T142	24520	0	0	0
T143	295930	0	0	0
T144	977	0	0	0
T145	220669	0	0	0
T146	584944	0	0	0
T147	196909	0	0	0
T148	1059	0	0	0
T149	41323	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424227666	2893	0	0
T4	1302	60	0	0
T5	0	23	0	0
T7	58644	0	0	0
T8	971662	0	0	0
T9	12836	0	0	0
T13	295995	0	0	0
T14	164241	0	0	0
T15	151448	0	0	0
T17	3473	0	0	0
T18	37190	0	0	0
T41	168858	0	0	0
T150	0	40	0	0
T151	0	44	0	0
T152	0	55	0	0
T153	0	50	0	0
T154	0	45	0	0
T155	0	33	0	0
T156	0	51	0	0
T157	0	55	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424227666	2118	0	0
T60	3243	20	0	0
T61	6135	56	0	0
T62	7568	19	0	0
T63	12779	102	0	0
T84	3039	16	0	0
T85	2712	17	0	0
T98	2909	12	0	0
T113	3288	27	0	0
T115	2005	8	0	0
T117	2580	11	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424227666	2574	0	0
T60	3243	28	0	0
T61	6135	27	0	0
T62	7568	10	0	0
T63	12779	216	0	0
T84	3039	19	0	0
T85	2712	14	0	0
T98	2909	29	0	0
T113	3288	2	0	0
T115	2005	11	0	0
T117	2580	24	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424227666	2114	0	0
T60	3243	14	0	0
T61	6135	60	0	0
T62	7568	28	0	0
T63	12779	74	0	0
T84	3039	16	0	0
T85	2712	7	0	0
T98	2909	8	0	0
T113	3288	21	0	0
T117	2580	16	0	0
T118	1526	15	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424227666	2089	0	0
T60	3243	14	0	0
T61	6135	65	0	0
T62	7568	1	0	0
T63	12779	130	0	0
T84	3039	22	0	0
T85	2712	8	0	0
T98	2909	4	0	0
T113	3288	45	0	0
T115	2005	1	0	0
T117	2580	4	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424227666	2009	0	0
T61	6135	46	0	0
T62	7568	9	0	0
T63	12779	142	0	0
T84	3039	17	0	0
T85	2712	8	0	0
T98	2909	14	0	0
T113	3288	18	0	0
T117	2580	11	0	0
T118	1526	6	0	0
T158	1780	2	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424227666	2049	0	0
T60	3243	14	0	0
T61	6135	64	0	0
T62	7568	21	0	0
T63	12779	146	0	0
T84	3039	15	0	0
T85	2712	8	0	0
T98	2909	24	0	0
T113	3288	13	0	0
T115	2005	1	0	0
T117	2580	32	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424227666	2158	0	0
T60	3243	18	0	0
T61	6135	35	0	0
T62	7568	31	0	0
T63	12779	96	0	0
T84	3039	28	0	0
T85	2712	20	0	0
T98	2909	9	0	0
T113	3288	6	0	0
T115	2005	1	0	0
T117	2580	9	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424227666	2256	0	0
T60	3243	14	0	0
T61	6135	44	0	0
T62	7568	18	0	0
T63	12779	126	0	0
T84	3039	30	0	0
T85	2712	15	0	0
T98	2909	8	0	0
T113	3288	10	0	0
T115	2005	5	0	0
T117	2580	25	0	0