Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
94.44	94.44	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	94.44	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.44	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	3	24	88.89

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	3	24	88.89	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

100116

1

T1

794

T10

832

T26

126

ack

6873

1

T1

11

T2

36

T10

26

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	398	1			T1	1		T10	5		T26	2
high	22486	1			T1	168		T2	3		T10	151
med	40080	1			T1	333		T2	1		T10	329
sml	43610	1			T1	297		T2	32		T10	369
all_zero	415	1			T1	6		T10	4		T14	5

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53341

1

T1

395

T2

14

T10

427

auto[1]

53648

1

T1

410

T2

22

T10

431

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

72672

1

T1

541

T2

19

T10

596

auto[1]

34317

1

T1

264

T2

17

T10

262

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

103476

1

T1

803

T2

10

T10

846

auto[1]

3513

1

T1

2

T2

26

T10

12

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

102449

1

T1

794

T2

26

T10

833

auto[1]

4540

1

T1

11

T2

10

T10

25

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

102862

1

T1

801

T2

27

T10

834

auto[1]

4127

1

T1

4

T2

9

T10

24

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53341

1

T1

395

T2

14

T10

427

auto[1]

53648

1

T1

410

T2

22

T10

431

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

72672

1

T1

541

T2

19

T10

596

auto[1]

34317

1

T1

264

T2

17

T10

262

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

103476

1

T1

803

T2

10

T10

846

auto[1]

3513

1

T1

2

T2

26

T10

12

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

102449

1

T1

794

T2

26

T10

833

auto[1]

4540

1

T1

11

T2

10

T10

25

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

102862

1

T1

801

T2

27

T10

834

auto[1]

4127

1

T1

4

T2

9

T10

24

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	3	24	88.89	1
Automatically Generated Cross Bins	15	1	14	93.33	1
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

cp_fbyte	start	stop	read	rcont	nakok	cp_ack	COUNT	AT LEAST	NUMBER	STATUS
[all_ones]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[ack]	0	1	1

Covered bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

3

1

T150

1

T216

1

T217

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

1

1

T218

1

-

-

-

-

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

122

1

T35

1

T219

1

T50

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

58

1

T220

1

T139

1

T148

2

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

50

1

T74

1

T221

1

T220

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

240

1

T10

6

T14

1

T74

2

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

102

1

T74

1

T138

1

T139

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

100

1

T10

3

T74

1

T221

1

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

203

1

T1

1

T10

2

T74

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

110

1

T10

2

T15

1

T74

2

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

113

1

T15

1

T219

1

T220

1

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

1

1

T222

1

-

-

-

-

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

1

1

T223

1

-

-

-

-

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

2

1

T1

1

T224

1

-

-

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	32189	1			T1	261		T10	268		T26	40
write_address_byte	4540	1			T1	11		T2	10		T10	25
read_with_ack	1152	1			T2	17		T14	1		T15	4
read_with_nack	2361	1			T1	2		T2	9		T10	12
stop_byte	4127	1			T1	4		T2	9		T10	24
write_address_byte_nak	1918	1			T1	6		T10	22		T14	6
data_byte_nack	100116	1			T1	794		T10	832		T26	126
stop_byte_nack	2553	1			T1	3		T10	21		T26	15
nakok_byte_nack	50283	1			T1	404		T10	419		T26	57
nakok_addr_byte_nack	927	1			T1	3		T10	13		T14	3