Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	22451637	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5862776

1

T1

2816

T2

7110

T3

722

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	25874791	1			T1	22259		T2	15080		T3	1393
values[0x0]	1218983	1			T1	418		T2	2477		T3	473
values[0x1]	1220639	1			T1	428		T2	2431		T3	500

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16218461	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

12095952

1

T1

9121

T2

10384

T3

1132

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	108555	1			T1	94		T2	60		T3	8
valid_sources[0x01]	88979	1			T1	84		T2	152		T3	11
valid_sources[0x02]	86995	1			T1	100		T2	66		T3	11
valid_sources[0x03]	96351	1			T1	86		T2	75		T3	3
valid_sources[0x04]	92348	1			T1	97		T2	73		T3	17
valid_sources[0x05]	119564	1			T1	96		T2	63		T3	11
valid_sources[0x06]	87369	1			T1	74		T2	78		T3	4
valid_sources[0x07]	97921	1			T1	82		T2	129		T3	13
valid_sources[0x08]	191720	1			T1	79		T2	90		T3	22
valid_sources[0x09]	110467	1			T1	106		T2	69		T3	13
valid_sources[0x0a]	318452	1			T1	101		T2	80		T3	15
valid_sources[0x0b]	97210	1			T1	91		T2	49		T3	3
valid_sources[0x0c]	83403	1			T1	100		T2	88		T3	4
valid_sources[0x0d]	129755	1			T1	94		T2	55		T3	15
valid_sources[0x0e]	95165	1			T1	116		T2	71		T3	6
valid_sources[0x0f]	89400	1			T1	100		T2	40		T3	6
valid_sources[0x10]	87739	1			T1	93		T2	105		T3	5
valid_sources[0x11]	234491	1			T1	90		T2	78		T3	8
valid_sources[0x12]	96751	1			T1	109		T2	82		T3	7
valid_sources[0x13]	90034	1			T1	86		T2	77		T3	14
valid_sources[0x14]	86389	1			T1	83		T2	80		T3	14
valid_sources[0x15]	96741	1			T1	101		T2	64		T3	9
valid_sources[0x16]	90321	1			T1	106		T2	73		T3	3
valid_sources[0x17]	91713	1			T1	98		T2	48		T3	5
valid_sources[0x18]	88312	1			T1	82		T2	98		T3	3
valid_sources[0x19]	111955	1			T1	86		T2	74		T3	21
valid_sources[0x1a]	87345	1			T1	72		T2	59		T3	8
valid_sources[0x1b]	87369	1			T1	97		T2	54		T3	7
valid_sources[0x1c]	100254	1			T1	91		T2	64		T3	4
valid_sources[0x1d]	88913	1			T1	103		T2	61		T3	15
valid_sources[0x1e]	90526	1			T1	94		T2	61		T3	11
valid_sources[0x1f]	92911	1			T1	84		T2	82		T3	2
valid_sources[0x20]	90374	1			T1	66		T2	103		T3	10
valid_sources[0x21]	94318	1			T1	85		T2	76		T4	94
valid_sources[0x22]	88699	1			T1	104		T2	94		T3	2
valid_sources[0x23]	105225	1			T1	83		T2	76		T3	11
valid_sources[0x24]	89335	1			T1	96		T2	100		T3	15
valid_sources[0x25]	98383	1			T1	84		T2	73		T3	1
valid_sources[0x26]	83467	1			T1	73		T2	73		T3	7
valid_sources[0x27]	373640	1			T1	82		T2	91		T3	15
valid_sources[0x28]	83903	1			T1	98		T2	101		T3	8
valid_sources[0x29]	118362	1			T1	82		T2	83		T3	1
valid_sources[0x2a]	87349	1			T1	88		T2	80		T3	5
valid_sources[0x2b]	84383	1			T1	108		T2	95		T3	16
valid_sources[0x2c]	87708	1			T1	87		T2	125		T3	26
valid_sources[0x2d]	81728	1			T1	88		T2	77		T3	10
valid_sources[0x2e]	99744	1			T1	97		T2	38		T3	8
valid_sources[0x2f]	88472	1			T1	106		T2	106		T3	18
valid_sources[0x30]	89297	1			T1	90		T2	64		T3	11
valid_sources[0x31]	91977	1			T1	93		T2	53		T3	8
valid_sources[0x32]	83851	1			T1	93		T2	148		T3	7
valid_sources[0x33]	88698	1			T1	103		T2	90		T3	1
valid_sources[0x34]	92042	1			T1	67		T2	74		T3	12
valid_sources[0x35]	82494	1			T1	96		T2	54		T3	8
valid_sources[0x36]	89020	1			T1	80		T2	55		T3	10
valid_sources[0x37]	90547	1			T1	80		T2	85		T3	15
valid_sources[0x38]	106869	1			T1	73		T2	123		T3	6
valid_sources[0x39]	91505	1			T1	88		T2	58		T3	11
valid_sources[0x3a]	87613	1			T1	81		T2	81		T3	2
valid_sources[0x3b]	292865	1			T1	91		T2	84		T3	16
valid_sources[0x3c]	158530	1			T1	102		T2	87		T3	3
valid_sources[0x3d]	94579	1			T1	106		T2	63		T3	4
valid_sources[0x3e]	93356	1			T1	81		T2	55		T3	2
valid_sources[0x3f]	107772	1			T1	84		T2	85		T3	7
valid_sources[0x40]	85606	1			T1	91		T2	88		T3	7
valid_sources[0x41]	164236	1			T1	84		T2	57		T3	7
valid_sources[0x42]	92947	1			T1	81		T2	85		T3	10
valid_sources[0x43]	85810	1			T1	80		T2	56		T3	10
valid_sources[0x44]	89814	1			T1	80		T2	109		T3	7
valid_sources[0x45]	85975	1			T1	95		T2	55		T3	6
valid_sources[0x46]	101938	1			T1	98		T2	51		T3	15
valid_sources[0x47]	273557	1			T1	81		T2	87		T3	9
valid_sources[0x48]	89573	1			T1	94		T2	71		T3	9
valid_sources[0x49]	87859	1			T1	103		T2	114		T3	10
valid_sources[0x4a]	96884	1			T1	83		T2	57		T3	13
valid_sources[0x4b]	98444	1			T1	92		T2	77		T3	9
valid_sources[0x4c]	84292	1			T1	90		T2	96		T3	9
valid_sources[0x4d]	216786	1			T1	98		T2	83		T3	10
valid_sources[0x4e]	91496	1			T1	68		T2	91		T3	1
valid_sources[0x4f]	92057	1			T1	86		T2	67		T3	15
valid_sources[0x50]	94197	1			T1	69		T2	108		T3	4
valid_sources[0x51]	82356	1			T1	105		T2	104		T3	10
valid_sources[0x52]	96404	1			T1	90		T2	62		T3	6
valid_sources[0x53]	88937	1			T1	91		T2	132		T3	6
valid_sources[0x54]	90056	1			T1	95		T2	80		T3	9
valid_sources[0x55]	87345	1			T1	96		T2	74		T3	8
valid_sources[0x56]	95149	1			T1	90		T2	74		T3	9
valid_sources[0x57]	84923	1			T1	82		T2	74		T3	9
valid_sources[0x58]	100582	1			T1	91		T2	110		T3	2
valid_sources[0x59]	92444	1			T1	101		T2	62		T3	12
valid_sources[0x5a]	87611	1			T1	93		T2	62		T3	9
valid_sources[0x5b]	442356	1			T1	73		T2	106		T3	5
valid_sources[0x5c]	218515	1			T1	87		T2	57		T3	6
valid_sources[0x5d]	122133	1			T1	72		T2	71		T3	17
valid_sources[0x5e]	86563	1			T1	93		T2	89		T3	22
valid_sources[0x5f]	323283	1			T1	100		T2	43		T3	2
valid_sources[0x60]	83222	1			T1	115		T2	84		T3	10
valid_sources[0x61]	199164	1			T1	97		T2	86		T3	8
valid_sources[0x62]	258590	1			T1	95		T2	106		T3	9
valid_sources[0x63]	83249	1			T1	87		T2	47		T3	12
valid_sources[0x64]	94725	1			T1	95		T2	104		T3	7
valid_sources[0x65]	93763	1			T1	78		T2	66		T3	7
valid_sources[0x66]	90355	1			T1	87		T2	86		T3	16
valid_sources[0x67]	204637	1			T1	107		T2	65		T3	11
valid_sources[0x68]	89952	1			T1	93		T2	75		T3	12
valid_sources[0x69]	91134	1			T1	78		T2	82		T3	7
valid_sources[0x6a]	105350	1			T1	103		T2	90		T3	21
valid_sources[0x6b]	85827	1			T1	78		T2	86		T3	4
valid_sources[0x6c]	88103	1			T1	93		T2	101		T3	10
valid_sources[0x6d]	88940	1			T1	75		T2	76		T3	6
valid_sources[0x6e]	95368	1			T1	95		T2	91		T3	10
valid_sources[0x6f]	110712	1			T1	91		T2	63		T3	2
valid_sources[0x70]	100891	1			T1	90		T2	102		T3	7
valid_sources[0x71]	84063	1			T1	98		T2	69		T3	2
valid_sources[0x72]	91824	1			T1	82		T2	97		T3	15
valid_sources[0x73]	85563	1			T1	97		T2	77		T3	9
valid_sources[0x74]	86378	1			T1	104		T2	71		T3	6
valid_sources[0x75]	127926	1			T1	83		T2	71		T3	6
valid_sources[0x76]	250710	1			T1	63		T2	71		T3	7
valid_sources[0x77]	83896	1			T1	92		T2	61		T3	6
valid_sources[0x78]	248040	1			T1	107		T2	124		T3	23
valid_sources[0x79]	93716	1			T1	95		T2	56		T3	7
valid_sources[0x7a]	96515	1			T1	98		T2	89		T3	16
valid_sources[0x7b]	94404	1			T1	112		T2	45		T3	22
valid_sources[0x7c]	353745	1			T1	96		T2	80		T3	10
valid_sources[0x7d]	90313	1			T1	96		T2	59		T3	12
valid_sources[0x7e]	379433	1			T1	116		T2	89		T3	5
valid_sources[0x7f]	108839	1			T1	79		T2	88		T3	12
valid_sources[0x80]	96107	1			T1	69		T2	51		T3	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4906695

1

T1

2467

T2

5062

T3

453

values[0x0]

all_enables

biggest_size

608572

1

T1

215

T2

1290

T3

175

values[0x1]

all_enables

biggest_size

347509

1

T1

134

T2

758

T3

94