Unified Coverage Report :: Module :: i2c_fsm

Module : i2c_fsm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.81	93.66	86.44		45.81	88.12	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core.u_i2c_fsm	82.81	93.66	86.44		45.81	88.12	100.00

---

Module Instance : tb.dut.i2c_core.u_i2c_fsm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.81	93.66	86.44		45.81	88.12	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.81	93.66	86.44		45.81	88.12	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.78	96.77	71.43			90.91	100.00	i2c_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c_fsm

	Line No.	Total	Covered	Percent
TOTAL		647	606	93.66
ALWAYS	178	17	17	100.00
CONT_ASSIGN	201	1	1	100.00
ALWAYS	204	3	3	100.00
ALWAYS	217	9	9	100.00
ALWAYS	235	5	5	100.00
CONT_ASSIGN	257	1	1	100.00
ALWAYS	261	6	6	100.00
ALWAYS	276	6	5	83.33
ALWAYS	287	7	7	100.00
ALWAYS	300	6	6	100.00
ALWAYS	311	5	5	100.00
ALWAYS	318	7	7	100.00
ALWAYS	331	5	5	100.00
ALWAYS	345	8	7	87.50
ALWAYS	357	8	7	87.50
ALWAYS	381	6	6	100.00
ALWAYS	391	6	6	100.00
ALWAYS	401	6	6	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
ALWAYS	423	9	9	100.00
CONT_ASSIGN	438	1	1	100.00
CONT_ASSIGN	439	1	1	100.00
CONT_ASSIGN	440	1	1	100.00
ALWAYS	444	7	7	100.00
ALWAYS	455	5	5	100.00
CONT_ASSIGN	472	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	476	1	1	100.00
CONT_ASSIGN	536	1	1	100.00
ALWAYS	541	6	6	100.00
CONT_ASSIGN	559	1	1	100.00
ALWAYS	564	4	4	100.00
CONT_ASSIGN	581	1	1	100.00
CONT_ASSIGN	585	1	1	100.00
ALWAYS	589	199	183	91.96
CONT_ASSIGN	993	1	1	100.00
CONT_ASSIGN	994	1	1	100.00
CONT_ASSIGN	998	1	1	100.00
CONT_ASSIGN	1007	1	1	100.00
CONT_ASSIGN	1012	1	1	100.00
ALWAYS	1016	272	250	91.91
ALWAYS	1597	3	3	100.00
ALWAYS	1606	5	5	100.00
CONT_ASSIGN	1615	1	1	100.00
CONT_ASSIGN	1616	1	1	100.00
CONT_ASSIGN	1619	1	1	100.00
CONT_ASSIGN	1622	1	1	100.00
CONT_ASSIGN	1626	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
195	1	1
196	1	1
			MISSING_ELSE
201	1	1
204	1	1
205	1	1
207	1	1
217	1	1
218	1	1
219	1	1
221	1	1
222	1	1
224	1	1
225	1	1
226	1	1
228	1	1
235	1	1
236	1	1
237	1	1
238	1	1
240	1	1
257	1	1
261	1	1
262	1	1
264	1	1
265	1	1
266	1	1
267	1	1
			MISSING_ELSE
276	1	1
277	1	1
278	1	1
279	0	1
280	1	1
281	1	1
			MISSING_ELSE
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
294	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
			MISSING_ELSE
311	2	2
312	2	2
313	1	1
318	1	1
319	1	1
320	1	1
321	1	1
322	1	1
323	1	1
325	1	1
331	1	1
332	1	1
333	1	1
335	1	1
336	1	1
345	1	1
346	1	1
347	1	1
348	0	1
349	1	1
350	1	1
351	1	1
352	1	1
			MISSING_ELSE
357	1	1
358	1	1
359	1	1
360	0	1
361	1	1
362	1	1
363	1	1
364	1	1
			MISSING_ELSE
381	1	1
382	1	1
383	1	1
384	1	1
385	1	1
386	1	1
			MISSING_ELSE
391	1	1
392	1	1
393	1	1
394	1	1
395	1	1
396	1	1
			MISSING_ELSE
401	1	1
402	1	1
403	1	1
404	1	1
405	1	1
406	1	1
			MISSING_ELSE
411	1	1
412	1	1
415	1	1
416	1	1
419	1	1
423	1	1
424	1	1
425	1	1
426	1	1
427	1	1
430	2	2
431	1	1
433	1	1
438	1	1
439	1	1
440	1	1
444	1	1
445	1	1
446	1	1
447	1	1
448	1	1
449	2	2
			MISSING_ELSE
			MISSING_ELSE
455	1	1
456	1	1
457	1	1
458	2	2
			MISSING_ELSE
			MISSING_ELSE
472	1	1
475	1	1
476	1	1
536	1	1
541	1	1
542	1	1
543	1	1
547	1	1
548	1	1
549	1	1
			MISSING_ELSE
559	1	1
564	1	1
565	1	1
566	1	1
567	1	1
			MISSING_ELSE
581	1	1
585	1	1
589	1	1
590	1	1
591	1	1
592	1	1
593	1	1
594	1	1
595	1	1
596	1	1
597	1	1
598	1	1
599	1	1
600	1	1
601	1	1
602	1	1
603	1	1
604	1	1
605	1	1
606	1	1
607	1	1
608	1	1
613	1	1
614	1	1
615	0	1
616	0	1
618	1	1
619	1	1
629	1	1
630	1	1
631	1	1
632	2	2
			MISSING_ELSE
636	1	1
637	1	1
638	1	1
642	1	1
643	1	1
644	1	1
647	1	1
648	1	1
649	1	1
651	1	1
653	1	1
657	1	1
658	1	1
659	1	1
660	1	1
661	2	2
			MISSING_ELSE
662	2	2
			MISSING_ELSE
666	1	1
667	1	1
668	1	1
672	1	1
673	1	1
674	1	1
678	1	1
679	1	1
680	1	1
681	2	2
			MISSING_ELSE
682	1	1
683	2	2
			MISSING_ELSE
684	2	2
			MISSING_ELSE
688	1	1
689	1	1
690	1	1
694	1	1
695	1	1
696	1	1
700	1	1
701	1	1
702	1	1
703	2	2
			MISSING_ELSE
704	2	2
			MISSING_ELSE
708	1	1
709	1	1
710	1	1
711	1	1
712	1	1
			MISSING_ELSE
717	1	1
718	1	1
722	2	2
723	2	2
724	1	1
728	1	1
729	2	2
730	2	2
731	1	1
732	1	1
733	1	1
734	2	2
			MISSING_ELSE
735	2	2
			MISSING_ELSE
739	1	1
740	2	2
741	2	2
742	1	1
743	1	1
747	1	1
748	1	1
749	1	1
753	1	1
754	1	1
755	1	1
759	1	1
760	1	1
761	1	1
762	1	1
766	1	1
772	1	1
776	1	1
777	2	2
778	1	1
779	1	1
788	1	1
792	1	1
793	1	1
797	1	1
801	1	1
802	1	1
806	1	1
807	1	1
811	1	1
812	1	1
815	1	1
816	1	1
820	0	1
821	0	1
824	1	1
825	1	1
			==> MISSING_ELSE
831	1	1
835	1	1
836	1	1
840	1	1
843	1	1
847	1	1
850	1	1
854	1	1
857	1	1
858	1	1
860	1	1
			MISSING_ELSE
865	1	1
866	1	1
867	1	1
871	1	1
875	1	1
879	1	1
880	1	1
884	1	1
885	1	1
889	1	1
890	1	1
892	1	1
893	1	1
894	1	1
			==> MISSING_ELSE
899	0	1
903	0	1
904	0	1
908	0	1
909	0	1
913	0	1
914	0	1
916	0	1
922	0	1
923	0	1
927	0	1
928	0	1
			==> MISSING_ELSE
934	1	1
935	1	1
937	1	1
938	1	1
939	1	1
943	1	1
944	1	1
948	1	1
949	1	1
950	1	1
954	1	1
955	1	1
958	1	1
959	1	1
960	1	1
984	1	1
986	1	1
987	1	1
989	1	1
			MISSING_ELSE
993	1	1
994	1	1
998	1	1
1007	1	1
1012	1	1
1016	1	1
1017	1	1
1018	1	1
1019	1	1
1020	1	1
1021	1	1
1022	1	1
1023	1	1
1024	1	1
1025	1	1
1026	1	1
1027	1	1
1028	1	1
1029	1	1
1030	1	1
1031	1	1
1032	1	1
1034	1	1
1037	2	2
1038	1	1
1039	2	2
			MISSING_ELSE
			MISSING_ELSE
1041	1	1
1050	1	1
1051	1	1
1052	1	1
1053	1	1
1054	1	1
			MISSING_ELSE
1059	1	1
1060	1	1
1061	1	1
1062	1	1
			MISSING_ELSE
1067	1	1
1068	1	1
1069	1	1
1070	1	1
			MISSING_ELSE
1075	1	1
1076	1	1
1077	1	1
1078	1	1
1079	1	1
1080	1	1
1082	1	1
1083	1	1
			MISSING_ELSE
1089	1	1
1090	1	1
1092	1	1
1093	1	1
1094	1	1
1095	1	1
1096	1	1
1097	1	1
			MISSING_ELSE
1102	1	1
1103	1	1
1104	1	1
1105	1	1
1106	1	1
1107	1	1
1108	1	1
1109	1	1
1111	1	1
1112	1	1
			MISSING_ELSE
1119	1	1
1120	1	1
1121	1	1
1122	1	1
			MISSING_ELSE
1127	1	1
1129	1	1
1130	1	1
1131	1	1
1132	1	1
1133	1	1
1134	1	1
			MISSING_ELSE
1139	1	1
1140	1	1
1141	1	1
1142	1	1
1143	1	1
1145	1	1
1146	1	1
1147	1	1
			MISSING_ELSE
1153	1	1
1154	1	1
1155	1	1
1156	1	1
			MISSING_ELSE
1161	1	1
1163	1	1
1164	1	1
1165	1	1
1166	1	1
1167	1	1
1168	1	1
1169	1	1
			MISSING_ELSE
1174	1	1
1175	1	1
1176	1	1
1177	1	1
1178	1	1
1179	1	1
1180	1	1
1182	1	1
1183	1	1
			MISSING_ELSE
1190	1	1
1191	1	1
1192	1	1
1193	1	1
1194	1	1
			MISSING_ELSE
1199	1	1
1200	1	1
1202	1	1
1203	1	1
1204	1	1
1205	1	1
1206	1	1
1207	1	1
			MISSING_ELSE
1212	1	1
1213	1	1
1214	1	1
1215	1	1
1216	1	1
1217	1	1
1218	1	1
1219	1	1
1221	1	1
1222	1	1
1223	1	1
1226	1	1
1227	1	1
1228	1	1
1229	1	1
			MISSING_ELSE
1235	1	1
1236	1	1
1237	1	1
1238	1	1
			MISSING_ELSE
1243	1	1
1244	1	1
1245	1	1
1246	1	1
1247	1	1
			MISSING_ELSE
1252	1	1
1253	1	1
1254	1	1
1255	1	1
1256	0	1
1257	0	1
1258	0	1
1260	1	1
1261	1	1
1262	1	1
			MISSING_ELSE
1268	1	1
1269	1	1
1270	1	1
1271	1	1
1272	1	1
1273	1	1
1274	1	1
1275	1	1
1276	1	1
1278	1	1
1279	1	1
1280	1	1
1281	1	1
1286	1	1
1287	0	1
1288	0	1
1289	0	1
1290	1	1
1291	1	1
1292	1	1
1293	1	1
1295	1	1
1296	1	1
1297	1	1
1308	1	1
1310	1	1
1311	1	1
			MISSING_ELSE
1313	1	1
1317	1	1
1318	1	1
1319	1	1
1324	0	1
1325	0	1
1327	0	1
1328	0	1
1331	1	1
1333	1	1
1334	1	1
1337	1	1
			MISSING_ELSE
1343	1	1
1344	1	1
			==> MISSING_ELSE
1349	2	2
			MISSING_ELSE
1353	1	1
1354	1	1
1355	1	1
1356	1	1
			MISSING_ELSE
1361	1	1
1367	1	1
1368	1	1
1369	1	1
1370	1	1
1371	1	1
1372	1	1
			==> MISSING_ELSE
			==> MISSING_ELSE
1378	1	1
1379	1	1
1381	1	1
1382	1	1
1383	1	1
1388	2	2
			MISSING_ELSE
1392	1	1
1393	1	1
1394	1	1
1395	1	1
			MISSING_ELSE
1400	1	1
1401	1	1
1402	1	1
1404	1	1
1405	1	1
1406	1	1
			==> MISSING_ELSE
1412	1	1
1413	1	1
			MISSING_ELSE
1419	1	1
1421	1	1
1422	1	1
1425	1	1
			MISSING_ELSE
1433	1	1
1437	1	1
1444	1	1
1445	0	1
1447	1	1
1449	1	1
1450	1	1
			MISSING_ELSE
1455	1	1
1456	1	1
			==> MISSING_ELSE
1461	2	2
			MISSING_ELSE
1465	1	1
1466	1	1
1467	1	1
1468	1	1
			MISSING_ELSE
1473	1	1
1476	1	1
			==> MISSING_ELSE
1481	0	1
1482	0	1
			==> MISSING_ELSE
1487	0	1
1488	0	1
			==> MISSING_ELSE
1493	0	1
1494	0	1
1495	0	1
1496	0	1
			==> MISSING_ELSE
1501	0	1
1503	0	1
			==> MISSING_ELSE
1513	1	1
1519	1	1
			MISSING_ELSE
1525	1	1
1526	1	1
1533	1	1
1534	1	1
1535	1	1
1538	1	1
			MISSING_ELSE
1543	1	1
1544	1	1
			MISSING_ELSE
1553	1	1
1554	1	1
			MISSING_ELSE
1578	1	1
1587	0	1
1588	1	1
1589	1	1
1590	1	1
1591	1	1
			MISSING_ELSE
1597	1	1
1598	1	1
1600	1	1
1606	1	1
1607	1	1
1608	1	1
1610	1	1
1611	1	1
1615	1	1
1616	1	1
1619	1	1
1622	1	1
1626	1	1

---

Cond Coverage for Module : i2c_fsm

	Total	Covered	Percent
Conditions	295	255	86.44
Logical	295	255	86.44
Non-Logical	0	0
Event	0	0

 LINE       195
 EXPRESSION (host_enable_i || target_enable_i)
             ------1------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T6

 LINE       222
 EXPRESSION (((!target_idle_o)) && event_host_timeout_o)
             ---------1--------    ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T5
1	1	Covered	T7,T8,T9

 LINE       225
 EXPRESSION (((!target_idle_o)) && scl_i)
             ---------1--------    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       264
 EXPRESSION (stretch_idle_cnt == stretch_cnt_threshold)
            ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       312
 EXPRESSION (fmt_byte_i == '0)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T11,T12,T13

 LINE       347
 EXPRESSION (trans_started && ((!host_enable_i)))
             ------1------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T10
1	1	Not Covered

 LINE       359
 EXPRESSION (pend_restart && ((!host_enable_i)))
             ------1-----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T14,T15
1	1	Not Covered

 LINE       383
 EXPRESSION (start_det_trigger || stop_det_trigger)
             --------1--------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       385
 EXPRESSION (start_det_pending || stop_det_pending)
             --------1--------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       395
 EXPRESSION (((!target_enable_i)) || ((!scl_i)) || start_det || stop_det_trigger)
             ----------1---------    -----2----    ----3----    --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T3,T4,T5
0	0	0	1	Covered	T3,T4,T5
0	0	1	0	Covered	T3,T4,T5
0	1	0	0	Covered	T3,T4,T5
1	0	0	0	Covered	T1,T2,T3

 LINE       405
 EXPRESSION (((!target_enable_i)) || ((!scl_i)) || stop_det || start_det_trigger)
             ----------1---------    -----2----    ----3---    --------4--------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T3,T4,T5
0	0	0	1	Covered	T3,T4,T5
0	0	1	0	Covered	T3,T4,T5
0	1	0	0	Covered	T3,T4,T5
1	0	0	0	Covered	T1,T2,T3

 LINE       411
 EXPRESSION (target_enable_i && ((scl_i_q && scl_i) & (sda_i_q && ((!sda_i)))))
             -------1-------    -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       411
 SUB-EXPRESSION ((scl_i_q && scl_i) & (sda_i_q && ((!sda_i))))
                 ---------1--------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       411
 SUB-EXPRESSION (scl_i_q && scl_i)
                 ---1---    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       411
 SUB-EXPRESSION (sda_i_q && ((!sda_i)))
                 ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       412
 EXPRESSION (target_enable_i && start_det_pending && (ctrl_det_count >= thd_dat_i))
             -------1-------    --------2--------    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T5

 LINE       415
 EXPRESSION (target_enable_i && ((scl_i_q && scl_i) & (((!sda_i_q)) && sda_i)))
             -------1-------    -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       415
 SUB-EXPRESSION ((scl_i_q && scl_i) & (((!sda_i_q)) && sda_i))
                 ---------1--------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       415
 SUB-EXPRESSION (scl_i_q && scl_i)
                 ---1---    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       415
 SUB-EXPRESSION (((!sda_i_q)) && sda_i)
                 ------1-----    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       416
 EXPRESSION (target_enable_i && stop_det_pending && (ctrl_det_count >= thd_dat_i))
             -------1-------    --------2-------    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T5

 LINE       419
 EXPRESSION (bit_idx == 4'd8)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       430
 EXPRESSION (input_byte_clr || bit_ack)
             -------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       438
 EXPRESSION ((input_byte[7:1] & target_mask0_i) == target_address0_i)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       439
 EXPRESSION ((input_byte[7:1] & target_mask1_i) == target_address1_i)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       440
 EXPRESSION (address0_match || address1_match)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       448
 EXPRESSION (((!scl_i_q)) && scl_i)
             ------1-----    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       457
 EXPRESSION (((!scl_i_q)) && scl_i)
             ------1-----    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       543
 EXPRESSION (((!en_sda_interf_det)) && ((|sda_rise_cnt)))
             -----------1----------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T10

 LINE       548
 EXPRESSION (en_sda_interf_det && (sda_rise_cnt < sda_rise_latency))
             --------1--------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       559
 EXPRESSION ((host_idle_o & host_enable_i & ((!sda_i))) | ((sda_rise_cnt == sda_rise_latency) & sda_o & ((!sda_i))))
             ---------------------1--------------------   ----------------------------2----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T6
1	0	Covered	T16,T17,T18

 LINE       559
 SUB-EXPRESSION (host_idle_o & host_enable_i & ((!sda_i)))
                 -----1-----   ------2------   -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T6
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T1,T2,T6
1	1	1	Covered	T16,T17,T18

 LINE       559
 SUB-EXPRESSION ((sda_rise_cnt == sda_rise_latency) & sda_o & ((!sda_i)))
                 -----------------1----------------   --2--   -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T6
1	1	0	Covered	T1,T2,T6
1	1	1	Covered	T1,T2,T6

 LINE       559
 SUB-EXPRESSION (sda_rise_cnt == sda_rise_latency)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T6

 LINE       566
 EXPRESSION (bit_ack && address_match)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       585
 EXPRESSION (((!target_idle)) & rw_bit_q & stop_det & ((!expect_stop)))
             --------1-------   ----2---   ----3---   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T19,T20,T21
1	0	1	1	Covered	T3,T5,T22
1	1	0	1	Covered	T3,T4,T5
1	1	1	0	Covered	T3,T4,T5
1	1	1	1	Covered	T23,T24,T25

 LINE       614
 EXPRESSION (host_enable_i && trans_started)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T6
1	1	Not Covered

 LINE       661
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T2,T10
1	1	Covered	T11

 LINE       662
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T2,T26,T27

 LINE       681
 EXPRESSION (((!scl_i_q)) && scl_i && sda_i && ((!fmt_flag_nak_ok_i)))
             ------1-----    --2--    --3--    -----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T28
1	0	1	1	Covered	T1,T2,T10
1	1	0	1	Covered	T1,T2,T10
1	1	1	0	Covered	T29
1	1	1	1	Covered	T30,T28

 LINE       683
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T2,T10
1	1	Covered	T11

 LINE       684
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       703
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T2,T10
1	1	Covered	T11

 LINE       704
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T2,T10,T14

 LINE       710
 EXPRESSION ((bit_index == '0) && (tcount_q == 20'b1))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T2,T10
1	1	Covered	T1,T2,T10

 LINE       710
 SUB-EXPRESSION (bit_index == '0)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       710
 SUB-EXPRESSION (tcount_q == 20'b1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       723
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       730
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       734
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T2,T10
1	1	Covered	T11

 LINE       735
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T2,T27,T31

 LINE       741
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       772
 EXPRESSION (fmt_flag_start_before_i && ((!trans_started)))
             -----------1-----------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T6,T32,T33
1	0	Covered	T1,T14,T15
1	1	Covered	T1,T2,T10

 LINE       815
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T3,T4,T5

 LINE       892
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T3,T5,T22

 LINE       916
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       937
 EXPRESSION (((!stretch_addr)) || nack_timeout)
             --------1--------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T34
0	1	Not Covered
1	0	Covered	T34

 LINE       984
 EXPRESSION (start_det || stop_det)
             ----1----    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       987
 EXPRESSION (start_det ? ({AcqRestart, input_byte}) : ({AcqStop, input_byte}))
             ----1----

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       998
 EXPRESSION (nack_timeout_en_i && (stretch_active_cnt >= nack_timeout_i))
             --------1--------    -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       1007
 EXPRESSION (((~tx_fifo_rvalid_i)) | (acq_fifo_depth_i > 9'(1'b1)))
             ----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T3,T5,T22
1	0	Covered	T1,T2,T3

 LINE       1037
 EXPRESSION (((!host_enable_i)) && ((!target_enable_i)))
             ---------1--------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       1050
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       1059
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       1067
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T35,T36,T13
1	Covered	T1,T2,T10

 LINE       1076
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T10

 LINE       1090
 EXPRESSION (((!scl_i)) && stretch_predict_cnt_expired)
             -----1----    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T2,T10
1	1	Covered	T37,T38,T39

 LINE       1094
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       1103
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       1107
 EXPRESSION (bit_index == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       1119
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       1127
 EXPRESSION (((!scl_i)) && stretch_predict_cnt_expired)
             -----1----    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T2,T10
1	1	Covered	T1,T2,T10

 LINE       1131
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       1139
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       1153
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       1161
 EXPRESSION (((!scl_i)) && stretch_predict_cnt_expired)
             -----1----    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T2,T10
1	1	Covered	T38,T39,T40

 LINE       1165
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       1174
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       1177
 EXPRESSION (bit_index == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       1191
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       1200
 EXPRESSION (((!scl_i)) && stretch_predict_cnt_expired)
             -----1----    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T2,T10
1	1	Covered	T38,T39,T40

 LINE       1204
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       1213
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       1215
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       1235
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       1243
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       1253
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       1273
 EXPRESSION (fmt_flag_start_before_i && ((!trans_started)))
             -----------1-----------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T6,T32,T33
1	0	Covered	T1,T14,T15
1	1	Covered	T1,T2,T10

 LINE       1290
 EXPRESSION (fmt_fifo_depth_i == 7'b1)
            -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       1308
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       1343
 EXPRESSION ((tcount_q == 20'b1) && ((!scl_i)))
             ---------1---------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T3,T4,T5

 LINE       1343
 SUB-EXPRESSION (tcount_q == 20'b1)
                ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T3,T4,T5

 LINE       1361
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T3,T4,T5

 LINE       1367
 EXPRESSION (stretch_addr && ((!nack_next_byte_q)))
             ------1-----    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Not Covered
1	1	Covered	T34

 LINE       1400
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T3,T4,T5

 LINE       1444
 EXPRESSION (acq_fifo_full_or_last_space || nack_next_byte_q)
             -------------1-------------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T22
0	1	Not Covered
1	0	Not Covered

 LINE       1455
 EXPRESSION ((tcount_q == 20'b1) && ((!scl_i)))
             ---------1---------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T3,T5,T22

 LINE       1455
 SUB-EXPRESSION (tcount_q == 20'b1)
                ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T3,T5,T22

 LINE       1473
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T3,T5,T22

 LINE       1476
 EXPRESSION (stretch_rx ? StretchAcqFull : AcquireByte)
             -----1----

-1-	Status	Tests
0	Covered	T3,T5,T22
1	Covered	T41,T34

 LINE       1481
 EXPRESSION ((tcount_q == 20'b1) && ((!scl_i)))
             ---------1---------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1481
 SUB-EXPRESSION (tcount_q == 20'b1)
                ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       1501
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       1513
 EXPRESSION (((!stretch_addr)) || nack_timeout)
             --------1--------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T34
0	1	Not Covered
1	0	Covered	T34

 LINE       1519
 EXPRESSION (rw_bit_q ? StretchTx : AcquireByte)
             ----1---

-1-	Status	Tests
0	Covered	T34
1	Not Covered

 LINE       1543
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T4,T22
1	Covered	T3,T4,T22

 LINE       1553
 EXPRESSION (((~stretch_rx)) || nack_timeout)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T41,T34
0	1	Not Covered
1	0	Covered	T41,T34

 LINE       1578
 EXPRESSION (((!target_idle)) && ((!target_enable_i)))
             --------1-------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Not Covered

 LINE       1619
 EXPRESSION (((!target_idle_o)) & (stretch_idle_cnt > host_timeout_i))
             ---------1--------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T3,T4,T5
1	1	Covered	T7,T8,T9

 LINE       1622
 EXPRESSION (stretch_en && (stretch_idle_cnt[30:0] > stretch_timeout_i) && timeout_enable_i)
             -----1----    ----------------------2---------------------    --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T1,T2,T10
1	1	1	Covered	T1,T2,T10

---

FSM Coverage for Module : i2c_fsm

Summary for FSM :: state_q

	Total	Covered	Percent
States	47	43	91.49	(Not included in score)
Transitions	155	71	45.81
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AcquireAckHold	1466	Covered	T3,T5,T22
AcquireAckPulse	1461	Covered	T3,T5,T22
AcquireAckSetup	1456	Covered	T3,T5,T22
AcquireAckWait	1447	Covered	T3,T5,T22
AcquireByte	1372	Covered	T3,T5,T22
AcquireStart	1589	Covered	T3,T4,T5
Active	1039	Covered	T1,T2,T6
AddrAckHold	1354	Covered	T3,T4,T5
AddrAckPulse	1349	Covered	T3,T4,T5
AddrAckSetup	1344	Covered	T3,T4,T5
AddrAckWait	1327	Covered	T3,T4,T5
AddrRead	1310	Covered	T3,T4,T5
ClockLow	1068	Covered	T1,T2,T6
ClockLowAck	1108	Covered	T1,T2,T10
ClockPulse	1082	Covered	T1,T2,T10
ClockPulseAck	1120	Covered	T1,T2,T10
ClockStart	1060	Covered	T1,T2,T10
ClockStop	1141	Covered	T1,T2,T10
HoldBit	1095	Covered	T1,T2,T10
HoldDevAck	1132	Covered	T1,T2,T10
HoldStart	1051	Covered	T1,T2,T10
HoldStop	1244	Covered	T1,T2,T10
HostClockLowAck	1178	Covered	T1,T2,T10
HostClockPulseAck	1192	Covered	T1,T2,T10
HostHoldBitAck	1205	Covered	T1,T2,T10
Idle	1037	Covered	T1,T2,T3
NackHold	1494	Not Covered
NackPulse	1488	Not Covered
NackSetup	1482	Not Covered
NackWait	1325	Not Covered
PopFmtFifo	1145	Covered	T1,T2,T10
ReadClockLow	1182	Covered	T1,T2,T10
ReadClockPulse	1154	Covered	T1,T2,T10
ReadHoldBit	1166	Covered	T1,T2,T10
SetupStart	1079	Covered	T1,T2,T10
SetupStop	1236	Covered	T1,T2,T10
StretchAcqFull	1476	Covered	T41,T34
StretchAddr	1368	Covered	T34
StretchTx	1379	Covered	T3,T4,T22
StretchTxSetup	1533	Covered	T3,T4,T22
TransmitAck	1402	Covered	T3,T4,T5
TransmitAckPulse	1413	Covered	T3,T4,T5
TransmitHold	1393	Covered	T3,T4,T5
TransmitPulse	1388	Covered	T3,T4,T5
TransmitSetup	1381	Covered	T3,T4,T5
TransmitWait	1370	Covered	T3,T4,T5
WaitForStop	1425	Covered	T3,T4,T5

transitions	Line No.	Covered	Tests
AcquireAckHold->AcquireByte	1476	Covered	T3,T5,T22
AcquireAckHold->AcquireStart	1589	Not Covered
AcquireAckHold->Idle	1587	Not Covered
AcquireAckHold->StretchAcqFull	1476	Covered	T41,T34
AcquireAckPulse->AcquireAckHold	1466	Covered	T3,T5,T22
AcquireAckPulse->AcquireStart	1589	Not Covered
AcquireAckPulse->Idle	1587	Not Covered
AcquireAckSetup->AcquireAckPulse	1461	Covered	T3,T5,T22
AcquireAckSetup->AcquireStart	1589	Not Covered
AcquireAckSetup->Idle	1587	Not Covered
AcquireAckWait->AcquireAckSetup	1456	Covered	T3,T5,T22
AcquireAckWait->AcquireStart	1589	Not Covered
AcquireAckWait->Idle	1587	Not Covered
AcquireByte->AcquireAckWait	1447	Covered	T3,T5,T22
AcquireByte->AcquireStart	1589	Covered	T3,T5,T22
AcquireByte->Idle	1587	Covered	T3,T5,T22
AcquireByte->NackWait	1445	Not Covered
AcquireStart->AddrRead	1310	Covered	T3,T4,T5
AcquireStart->Idle	1587	Not Covered
Active->AcquireStart	1589	Not Covered
Active->ClockLow	1278	Covered	T1,T6,T10
Active->Idle	1587	Not Covered
Active->ReadClockLow	1270	Covered	T1,T2,T10
Active->SetupStart	1274	Covered	T1,T2,T10
AddrAckHold->AcquireByte	1372	Covered	T3,T5,T22
AddrAckHold->AcquireStart	1589	Not Covered
AddrAckHold->Idle	1587	Not Covered
AddrAckHold->StretchAddr	1368	Covered	T34
AddrAckHold->TransmitWait	1370	Covered	T3,T4,T5
AddrAckPulse->AcquireStart	1589	Not Covered
AddrAckPulse->AddrAckHold	1354	Covered	T3,T4,T5
AddrAckPulse->Idle	1587	Not Covered
AddrAckSetup->AcquireStart	1589	Not Covered
AddrAckSetup->AddrAckPulse	1349	Covered	T3,T4,T5
AddrAckSetup->Idle	1587	Not Covered
AddrAckWait->AcquireStart	1589	Not Covered
AddrAckWait->AddrAckSetup	1344	Covered	T3,T4,T5
AddrAckWait->Idle	1587	Not Covered
AddrRead->AcquireStart	1589	Covered	T42,T43,T44
AddrRead->AddrAckWait	1327	Covered	T3,T4,T5
AddrRead->Idle	1337	Covered	T45,T19,T20
AddrRead->NackWait	1325	Not Covered
ClockLow->AcquireStart	1589	Not Covered
ClockLow->ClockPulse	1082	Covered	T1,T2,T10
ClockLow->Idle	1587	Covered	T46,T47,T48
ClockLow->SetupStart	1079	Covered	T1,T14,T15
ClockLowAck->AcquireStart	1589	Not Covered
ClockLowAck->ClockPulseAck	1120	Covered	T1,T2,T10
ClockLowAck->Idle	1587	Not Covered
ClockPulse->AcquireStart	1589	Not Covered
ClockPulse->HoldBit	1095	Covered	T1,T2,T10
ClockPulse->Idle	1587	Covered	T47,T48,T49
ClockPulseAck->AcquireStart	1589	Not Covered
ClockPulseAck->HoldDevAck	1132	Covered	T1,T2,T10
ClockPulseAck->Idle	1587	Covered	T46,T47,T48
ClockStart->AcquireStart	1589	Not Covered
ClockStart->ClockLow	1068	Covered	T1,T2,T10
ClockStart->Idle	1587	Not Covered
ClockStop->AcquireStart	1589	Not Covered
ClockStop->Idle	1587	Not Covered
ClockStop->SetupStop	1236	Covered	T1,T2,T10
HoldBit->AcquireStart	1589	Not Covered
HoldBit->ClockLow	1111	Covered	T1,T2,T10
HoldBit->ClockLowAck	1108	Covered	T1,T2,T10
HoldBit->Idle	1587	Covered	T50,T49,T51
HoldDevAck->AcquireStart	1589	Not Covered
HoldDevAck->ClockStop	1141	Covered	T1,T10,T26
HoldDevAck->Idle	1587	Not Covered
HoldDevAck->PopFmtFifo	1145	Covered	T1,T2,T10
HoldStart->AcquireStart	1589	Not Covered
HoldStart->ClockStart	1060	Covered	T1,T2,T10
HoldStart->Idle	1587	Not Covered
HoldStop->AcquireStart	1589	Not Covered
HoldStop->Idle	1256	Not Covered
HoldStop->PopFmtFifo	1260	Covered	T1,T2,T10
HostClockLowAck->AcquireStart	1589	Not Covered
HostClockLowAck->HostClockPulseAck	1192	Covered	T1,T2,T10
HostClockLowAck->Idle	1587	Not Covered
HostClockPulseAck->AcquireStart	1589	Not Covered
HostClockPulseAck->HostHoldBitAck	1205	Covered	T1,T2,T10
HostClockPulseAck->Idle	1587	Not Covered
HostHoldBitAck->AcquireStart	1589	Not Covered
HostHoldBitAck->ClockStop	1217	Covered	T1,T2,T10
HostHoldBitAck->Idle	1587	Not Covered
HostHoldBitAck->PopFmtFifo	1221	Covered	T2,T14,T15
HostHoldBitAck->ReadClockLow	1226	Covered	T1,T2,T10
Idle->AcquireStart	1589	Covered	T3,T4,T5
Idle->Active	1039	Covered	T1,T2,T6
NackHold->AcquireStart	1589	Not Covered
NackHold->Idle	1503	Not Covered
NackPulse->AcquireStart	1589	Not Covered
NackPulse->Idle	1587	Not Covered
NackPulse->NackHold	1494	Not Covered
NackSetup->AcquireStart	1589	Not Covered
NackSetup->Idle	1587	Not Covered
NackSetup->NackPulse	1488	Not Covered
NackWait->AcquireStart	1589	Not Covered
NackWait->Idle	1587	Not Covered
NackWait->NackSetup	1482	Not Covered
PopFmtFifo->AcquireStart	1589	Not Covered
PopFmtFifo->Active	1295	Covered	T1,T2,T10
PopFmtFifo->ClockStop	1287	Not Covered
PopFmtFifo->Idle	1291	Covered	T1,T2,T10
ReadClockLow->AcquireStart	1589	Not Covered
ReadClockLow->Idle	1587	Not Covered
ReadClockLow->ReadClockPulse	1154	Covered	T1,T2,T10
ReadClockPulse->AcquireStart	1589	Not Covered
ReadClockPulse->Idle	1587	Not Covered
ReadClockPulse->ReadHoldBit	1166	Covered	T1,T2,T10
ReadHoldBit->AcquireStart	1589	Not Covered
ReadHoldBit->HostClockLowAck	1178	Covered	T1,T2,T10
ReadHoldBit->Idle	1587	Not Covered
ReadHoldBit->ReadClockLow	1182	Covered	T1,T2,T10
SetupStart->AcquireStart	1589	Not Covered
SetupStart->HoldStart	1051	Covered	T1,T2,T10
SetupStart->Idle	1587	Not Covered
SetupStop->AcquireStart	1589	Not Covered
SetupStop->HoldStop	1244	Covered	T1,T2,T10
SetupStop->Idle	1587	Not Covered
StretchAcqFull->AcquireByte	1554	Covered	T41,T34
StretchAcqFull->AcquireStart	1589	Not Covered
StretchAcqFull->Idle	1587	Not Covered
StretchAddr->AcquireByte	1519	Covered	T34
StretchAddr->AcquireStart	1589	Not Covered
StretchAddr->Idle	1587	Not Covered
StretchAddr->StretchTx	1519	Not Covered
StretchTx->AcquireStart	1589	Not Covered
StretchTx->Idle	1587	Not Covered
StretchTx->StretchTxSetup	1533	Covered	T3,T4,T22
StretchTxSetup->AcquireStart	1589	Not Covered
StretchTxSetup->Idle	1587	Not Covered
StretchTxSetup->TransmitSetup	1544	Covered	T3,T4,T22
TransmitAck->AcquireStart	1589	Not Covered
TransmitAck->Idle	1587	Not Covered
TransmitAck->TransmitAckPulse	1413	Covered	T3,T4,T5
TransmitAckPulse->AcquireStart	1589	Covered	T52,T53
TransmitAckPulse->Idle	1587	Not Covered
TransmitAckPulse->TransmitWait	1422	Covered	T3,T4,T5
TransmitAckPulse->WaitForStop	1425	Covered	T3,T4,T5
TransmitHold->AcquireStart	1589	Not Covered
TransmitHold->Idle	1587	Not Covered
TransmitHold->TransmitAck	1402	Covered	T3,T4,T5
TransmitHold->TransmitSetup	1406	Covered	T3,T4,T5
TransmitPulse->AcquireStart	1589	Covered	T24,T25,T54
TransmitPulse->Idle	1587	Covered	T24,T25,T54
TransmitPulse->TransmitHold	1393	Covered	T3,T4,T5
TransmitSetup->AcquireStart	1589	Not Covered
TransmitSetup->Idle	1587	Not Covered
TransmitSetup->TransmitPulse	1388	Covered	T3,T4,T5
TransmitWait->AcquireStart	1589	Not Covered
TransmitWait->Idle	1587	Not Covered
TransmitWait->StretchTx	1379	Covered	T3,T4,T22
TransmitWait->TransmitSetup	1381	Covered	T3,T4,T5
WaitForStop->AcquireStart	1589	Covered	T3,T4,T5
WaitForStop->Idle	1587	Covered	T3,T4,T5

---

Branch Coverage for Module : i2c_fsm

	Line No.	Total	Covered	Percent
Branches		303	267	88.12
IF	179	15	14	93.33
IF	204	2	2	100.00
IF	217	5	5	100.00
IF	235	3	3	100.00
IF	261	4	4	100.00
IF	276	4	3	75.00
IF	287	4	4	100.00
IF	300	4	4	100.00
IF	311	3	3	100.00
IF	318	4	4	100.00
IF	331	2	2	100.00
IF	345	5	4	80.00
IF	357	5	4	80.00
IF	381	4	4	100.00
IF	391	4	4	100.00
IF	401	4	4	100.00
IF	423	5	5	100.00
IF	444	5	5	100.00
IF	455	4	4	100.00
IF	541	4	4	100.00
IF	564	3	3	100.00
CASE	608	79	69	87.34
IF	984	3	3	100.00
CASE	1034	120	99	82.50
IF	1578	4	3	75.00
IF	1597	2	2	100.00
IF	1606	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	179	if (load_tcount)
-2-:	180	case (tcount_sel)
-3-:	195	if ((host_enable_i || target_enable_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	tSetupStart	-	Covered	T1,T2,T10
1	tHoldStart	-	Covered	T1,T2,T10
1	tSetupData	-	Covered	T3,T4,T22
1	tClockStart	-	Covered	T1,T2,T3
1	tClockLow	-	Covered	T1,T2,T6
1	tClockPulse	-	Covered	T1,T2,T10
1	tClockHigh	-	Covered	T1,T2,T10
1	tHoldBit	-	Covered	T1,T2,T10
1	tClockStop	-	Covered	T1,T2,T10
1	tSetupStop	-	Covered	T1,T2,T10
1	tHoldStop	-	Covered	T1,T2,T10
1	tNoDelay	-	Covered	T1,T2,T10
1	default	-	Not Covered
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	204	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	217	if ((!rst_ni))
-2-:	219	if (stretch_en)
-3-:	222	if (((!target_idle_o) && event_host_timeout_o))
-4-:	225	if (((!target_idle_o) && scl_i))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T2,T10
0	0	1	-	Covered	T7,T8,T9
0	0	0	1	Covered	T3,T4,T5
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	235	if ((!rst_ni))
-2-:	237	if (actively_stretching)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T41,T34
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	261	if ((!rst_ni))
-2-:	264	if ((stretch_idle_cnt == stretch_cnt_threshold))
-3-:	266	if ((!stretch_en))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T10

	LineNo.	Expression
-1-:	276	if ((!rst_ni))
-2-:	278	if (set_nack_next_byte)
-3-:	280	if (clear_nack_next_byte)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	287	if ((!rst_ni))
-2-:	289	if (bit_clr)
-3-:	291	if (bit_decr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T10
0	0	1	Covered	T1,T2,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))
-2-:	302	if (read_byte_clr)
-3-:	304	if (shift_data_en)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T10
0	0	1	Covered	T1,T2,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	311	if ((!fmt_flag_read_bytes_i))
-2-:	312	if ((fmt_byte_i == '0))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
0	0	Covered	T1,T2,T10

	LineNo.	Expression
-1-:	318	if ((!rst_ni))
-2-:	320	if (byte_clr)
-3-:	322	if (byte_decr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T10
0	0	1	Covered	T1,T2,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	331	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	345	if ((!rst_ni))
-2-:	347	if ((trans_started && (!host_enable_i)))
-3-:	349	if (log_start)
-4-:	351	if (log_stop)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	-	Covered	T1,T2,T10
0	0	0	1	Covered	T1,T2,T10
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	357	if ((!rst_ni))
-2-:	359	if ((pend_restart && (!host_enable_i)))
-3-:	361	if (req_restart)
-4-:	363	if (log_start)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	-	Covered	T1,T14,T15
0	0	0	1	Covered	T1,T2,T10
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	381	if ((!rst_ni))
-2-:	383	if ((start_det_trigger || stop_det_trigger))
-3-:	385	if ((start_det_pending || stop_det_pending))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T5
0	0	1	Covered	T3,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	391	if ((!rst_ni))
-2-:	393	if (start_det_trigger)
-3-:	395	if (((((!target_enable_i) || (!scl_i)) || start_det) || stop_det_trigger))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T5
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	401	if ((!rst_ni))
-2-:	403	if (stop_det_trigger)
-3-:	405	if (((((!target_enable_i) || (!scl_i)) || stop_det) || start_det_trigger))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T5
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	423	if ((!rst_ni))
-2-:	425	if (start_det)
-3-:	427	if ((scl_i_q && (!scl_i)))
-4-:	430	if ((input_byte_clr || bit_ack))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T3,T4,T5
0	0	1	1	Covered	T1,T2,T3
0	0	1	0	Covered	T1,T2,T3
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	444	if ((!rst_ni))
-2-:	446	if (input_byte_clr)
-3-:	448	if (((!scl_i_q) && scl_i))
-4-:	449	if ((!bit_ack))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T3,T4,T5
0	0	1	1	Covered	T1,T2,T3
0	0	1	0	Covered	T1,T2,T3
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	455	if ((!rst_ni))
-2-:	457	if (((!scl_i_q) && scl_i))
-3-:	458	if (bit_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	541	if ((!rst_ni))
-2-:	543	if (((!en_sda_interf_det) && (|sda_rise_cnt)))
-3-:	548	if ((en_sda_interf_det && (sda_rise_cnt < sda_rise_latency)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T10
0	0	1	Covered	T1,T2,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	564	if ((!rst_ni))
-2-:	566	if ((bit_ack && address_match))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	608	case (state_q)
-2-:	614	if ((host_enable_i && trans_started))
-3-:	632	if (log_start)
-4-:	648	if (pend_restart)
-5-:	661	if ((scl_i_q && (!scl_i)))
-6-:	662	if ((sda_i_q != sda_i))
-7-:	681	if (((((!scl_i_q) && scl_i) && sda_i) && (!fmt_flag_nak_ok_i)))
-8-:	683	if ((scl_i_q && (!scl_i)))
-9-:	684	if ((sda_i_q != sda_i))
-10-:	703	if ((scl_i_q && (!scl_i)))
-11-:	704	if ((sda_i_q != sda_i))
-12-:	710	if (((bit_index == '0) && (tcount_q == 20'b1)))
-13-:	722	if (fmt_flag_read_continue_i)
-14-:	723	if ((byte_index == 9'b1))
-15-:	729	if (fmt_flag_read_continue_i)
-16-:	730	if ((byte_index == 9'b1))
-17-:	734	if ((scl_i_q && (!scl_i)))
-18-:	735	if ((sda_i_q != sda_i))
-19-:	740	if (fmt_flag_read_continue_i)
-20-:	741	if ((byte_index == 9'b1))
-21-:	777	if (fmt_flag_stop_after_i)
-22-:	815	if ((tcount_q == 20'b1))
-23-:	816	if (nack_next_byte_q)
-24-:	858	if ((!scl_i))
-25-:	892	if ((tcount_q == 20'b1))
-26-:	916	if ((tcount_q == 20'b1))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
Idle	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
SetupStart	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
SetupStart	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
HoldStart	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
ClockStart	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
ClockLow	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T14,T15
ClockLow	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
ClockPulse	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11
ClockPulse	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
ClockPulse	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T26,T27
ClockPulse	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
HoldBit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
ClockLowAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
ClockPulseAck	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T30,T28
ClockPulseAck	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
ClockPulseAck	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11
ClockPulseAck	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
ClockPulseAck	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
ClockPulseAck	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
HoldDevAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
ReadClockLow	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
ReadClockPulse	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11
ReadClockPulse	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
ReadClockPulse	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T14
ReadClockPulse	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
ReadHoldBit	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
ReadHoldBit	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T14,T15
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T14,T15
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T11
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T27,T31
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T2,T14,T15
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	Covered	T1,T2,T10
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	Covered	T1,T2,T10
ClockStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
SetupStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
HoldStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
Active	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
PopFmtFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T2,T10
PopFmtFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T10
AcquireStart	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
AddrRead	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
AddrAckWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
AddrAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
AddrAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
AddrAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	Not Covered
AddrAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	Covered	T3,T4,T5
AddrAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Not Covered
TransmitWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
TransmitSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
TransmitPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
TransmitHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
TransmitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
TransmitAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T3,T4,T5
TransmitAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T3,T4,T5
WaitForStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
AcquireByte	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T22
AcquireAckWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T22
AcquireAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T22
AcquireAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T22
AcquireAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T5,T22
AcquireAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Not Covered
NackWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
NackSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
NackPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
NackHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Not Covered
NackHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Not Covered
StretchAddr	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T34
StretchTx	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T22
StretchTxSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T22
StretchAcqFull	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T41,T34
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	984	if ((start_det || stop_det))
-2-:	987	(start_det) ? 

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1034	case (state_q)
-2-:	1037	if (((!host_enable_i) && (!target_enable_i)))
-3-:	1038	if (host_enable_i)
-4-:	1039	if (fmt_fifo_rvalid_i)
-5-:	1050	if ((tcount_q == 20'b1))
-6-:	1059	if ((tcount_q == 20'b1))
-7-:	1067	if ((tcount_q == 20'b1))
-8-:	1076	if ((tcount_q == 20'b1))
-9-:	1078	if (pend_restart)
-10-:	1090	if (((!scl_i) && stretch_predict_cnt_expired))
-11-:	1094	if ((tcount_q == 20'b1))
-12-:	1103	if ((tcount_q == 20'b1))
-13-:	1107	if ((bit_index == '0))
-14-:	1119	if ((tcount_q == 20'b1))
-15-:	1127	if (((!scl_i) && stretch_predict_cnt_expired))
-16-:	1131	if ((tcount_q == 20'b1))
-17-:	1139	if ((tcount_q == 20'b1))
-18-:	1140	if (fmt_flag_stop_after_i)
-19-:	1153	if ((tcount_q == 20'b1))
-20-:	1161	if (((!scl_i) && stretch_predict_cnt_expired))
-21-:	1165	if ((tcount_q == 20'b1))
-22-:	1174	if ((tcount_q == 20'b1))
-23-:	1177	if ((bit_index == '0))
-24-:	1191	if ((tcount_q == 20'b1))
-25-:	1200	if (((!scl_i) && stretch_predict_cnt_expired))
-26-:	1204	if ((tcount_q == 20'b1))
-27-:	1213	if ((tcount_q == 20'b1))
-28-:	1215	if ((byte_index == 9'b1))
-29-:	1216	if (fmt_flag_stop_after_i)
-30-:	1235	if ((tcount_q == 20'b1))
-31-:	1243	if ((tcount_q == 20'b1))
-32-:	1253	if ((tcount_q == 20'b1))
-33-:	1255	if ((!host_enable_i))
-34-:	1268	if (fmt_flag_read_bytes_i)
-35-:	1273	if ((fmt_flag_start_before_i && (!trans_started)))
-36-:	1286	if ((!host_enable_i))
-37-:	1290	if ((fmt_fifo_depth_i == 7'b1))
-38-:	1308	if ((scl_i_q && (!scl_i)))
-39-:	1317	if (bit_ack)
-40-:	1318	if (address_match)
-41-:	1319	if (acq_fifo_full_or_last_space)
-42-:	1324	if (rw_bit_q)
-43-:	1343	if (((tcount_q == 20'b1) && (!scl_i)))
-44-:	1349	if (scl_i)
-45-:	1353	if ((!scl_i))
-46-:	1361	if ((tcount_q == 20'b1))
-47-:	1367	if ((stretch_addr && (!nack_next_byte_q)))
-48-:	1369	if (rw_bit_q)
-49-:	1371	if ((!rw_bit_q))
-50-:	1378	if (stretch_tx)
-51-:	1388	if (scl_i)
-52-:	1392	if ((!scl_i))
-53-:	1400	if ((tcount_q == 20'b1))
-54-:	1401	if (bit_ack)
-55-:	1412	if (scl_i)
-56-:	1419	if ((!scl_i))
-57-:	1421	if (host_ack)
-58-:	1437	if (bit_ack)
-59-:	1444	if ((acq_fifo_full_or_last_space || nack_next_byte_q))
-60-:	1455	if (((tcount_q == 20'b1) && (!scl_i)))
-61-:	1461	if (scl_i)
-62-:	1465	if ((!scl_i))
-63-:	1473	if ((tcount_q == 20'b1))
-64-:	1476	(stretch_rx) ? 
-65-:	1481	if (((tcount_q == 20'b1) && (!scl_i)))
-66-:	1487	if (scl_i)
-67-:	1493	if ((!scl_i))
-68-:	1501	if ((tcount_q == 20'b1))
-69-:	1513	if (((!stretch_addr) || nack_timeout))
-70-:	1519	(rw_bit_q) ? 
-71-:	1526	if ((!stretch_tx))
-72-:	1543	if ((tcount_q == 20'b1))
-73-:	1553	if (((~stretch_rx) || nack_timeout))

Branches:

Branch	Status	Tests
(1.Idle )->(2)	Covered	T1,T2,T3
(1.Idle )->(!2)->(3)->(4)	Covered	T1,T2,T6
(1.Idle )->(!2)->(3)->(!4)	Covered	T1,T2,T6
(1.Idle )->(!2)->(!3)	Covered	T3,T4,T5
(1.SetupStart )->(5)	Covered	T1,T2,T10
(1.SetupStart )->(!5)	Covered	T1,T2,T10
(1.HoldStart )->(6)	Covered	T1,T2,T10
(1.HoldStart )->(!6)	Covered	T1,T2,T10
(1.ClockStart )->(7)	Covered	T1,T2,T10
(1.ClockStart )->(!7)	Covered	T35,T36,T13
(1.ClockLow )->(8)->(9)	Covered	T1,T14,T15
(1.ClockLow )->(8)->(!9)	Covered	T1,T2,T10
(1.ClockLow )->(!8)	Covered	T1,T2,T6
(1.ClockPulse )->(10)	Covered	T37,T38,T39
(1.ClockPulse )->(!10)->(11)	Covered	T1,T2,T10
(1.ClockPulse )->(!10)->(!11)	Covered	T1,T2,T10
(1.HoldBit )->(12)->(13)	Covered	T1,T2,T10
(1.HoldBit )->(12)->(!13)	Covered	T1,T2,T10
(1.HoldBit )->(!12)	Covered	T1,T2,T10
(1.ClockLowAck )->(14)	Covered	T1,T2,T10
(1.ClockLowAck )->(!14)	Covered	T1,T2,T10
(1.ClockPulseAck )->(15)	Covered	T1,T2,T10
(1.ClockPulseAck )->(!15)->(16)	Covered	T1,T2,T10
(1.ClockPulseAck )->(!15)->(!16)	Covered	T1,T2,T10
(1.HoldDevAck )->(17)->(18)	Covered	T1,T10,T26
(1.HoldDevAck )->(17)->(!18)	Covered	T1,T2,T10
(1.HoldDevAck )->(!17)	Covered	T1,T2,T10
(1.ReadClockLow )->(19)	Covered	T1,T2,T10
(1.ReadClockLow )->(!19)	Covered	T1,T2,T10
(1.ReadClockPulse )->(20)	Covered	T38,T39,T40
(1.ReadClockPulse )->(!20)->(21)	Covered	T1,T2,T10
(1.ReadClockPulse )->(!20)->(!21)	Covered	T1,T2,T10
(1.ReadHoldBit )->(22)->(23)	Covered	T1,T2,T10
(1.ReadHoldBit )->(22)->(!23)	Covered	T1,T2,T10
(1.ReadHoldBit )->(!22)	Covered	T1,T2,T10
(1.HostClockLowAck )->(24)	Covered	T1,T2,T10
(1.HostClockLowAck )->(!24)	Covered	T1,T2,T10
(1.HostClockPulseAck )->(25)	Covered	T38,T39,T40
(1.HostClockPulseAck )->(!25)->(26)	Covered	T1,T2,T10
(1.HostClockPulseAck )->(!25)->(!26)	Covered	T1,T2,T10
(1.HostHoldBitAck )->(27)->(28)->(29)	Covered	T1,T2,T10
(1.HostHoldBitAck )->(27)->(28)->(!29)	Covered	T2,T14,T15
(1.HostHoldBitAck )->(27)->(!28)	Covered	T1,T2,T10
(1.HostHoldBitAck )->(!27)	Covered	T1,T2,T10
(1.ClockStop )->(30)	Covered	T1,T2,T10
(1.ClockStop )->(!30)	Covered	T1,T2,T10
(1.SetupStop )->(31)	Covered	T1,T2,T10
(1.SetupStop )->(!31)	Covered	T1,T2,T10
(1.HoldStop )->(32)->(33)	Not Covered
(1.HoldStop )->(32)->(!33)	Covered	T1,T2,T10
(1.HoldStop )->(!32)	Covered	T1,T2,T10
(1.Active )->(34)	Covered	T1,T2,T10
(1.Active )->(!34)->(35)	Covered	T1,T2,T10
(1.Active )->(!34)->(!35)	Covered	T1,T6,T10
(1.PopFmtFifo )->(36)	Not Covered
(1.PopFmtFifo )->(!36)->(37)	Covered	T1,T2,T10
(1.PopFmtFifo )->(!36)->(!37)	Covered	T1,T2,T10
(1.AcquireStart )->(38)	Covered	T3,T4,T5
(1.AcquireStart )->(!38)	Covered	T3,T4,T5
(1.AddrRead )->(39)->(40)->(41)->(42)	Not Covered
(1.AddrRead )->(39)->(40)->(41)->(!42)	Not Covered
(1.AddrRead )->(39)->(40)->(!41)	Covered	T3,T4,T5
(1.AddrRead )->(39)->(!40)	Covered	T19,T20,T21
(1.AddrRead )->(!39)	Covered	T3,T4,T5
(1.AddrAckWait )->(43)	Covered	T3,T4,T5
(1.AddrAckWait )->(!43)	Not Covered
(1.AddrAckSetup )->(44)	Covered	T3,T4,T5
(1.AddrAckSetup )->(!44)	Covered	T3,T4,T5
(1.AddrAckPulse )->(45)	Covered	T3,T4,T5
(1.AddrAckPulse )->(!45)	Covered	T3,T4,T5
(1.AddrAckHold )->(46)->(47)	Covered	T34
(1.AddrAckHold )->(46)->(!47)->(48)	Covered	T3,T4,T5
(1.AddrAckHold )->(46)->(!47)->(!48)->(49)	Covered	T3,T5,T22
(1.AddrAckHold )->(46)->(!47)->(!48)->(!49)	Not Covered
(1.AddrAckHold )->(!46)	Not Covered
(1.TransmitWait )->(50)	Covered	T3,T4,T22
(1.TransmitWait )->(!50)	Covered	T3,T4,T5
(1.TransmitSetup )->(51)	Covered	T3,T4,T5
(1.TransmitSetup )->(!51)	Covered	T3,T4,T5
(1.TransmitPulse )->(52)	Covered	T3,T4,T5
(1.TransmitPulse )->(!52)	Covered	T3,T4,T5
(1.TransmitHold )->(53)->(54)	Covered	T3,T4,T5
(1.TransmitHold )->(53)->(!54)	Covered	T3,T4,T5
(1.TransmitHold )->(!53)	Not Covered
(1.TransmitAck )->(55)	Covered	T3,T4,T5
(1.TransmitAck )->(!55)	Covered	T3,T4,T5
(1.TransmitAckPulse )->(56)->(57)	Covered	T3,T4,T5
(1.TransmitAckPulse )->(56)->(!57)	Covered	T3,T4,T5
(1.TransmitAckPulse )->(!56)	Covered	T3,T4,T5
(1.WaitForStop )	Covered	T3,T4,T5
(1.AcquireByte )->(58)->(59)	Not Covered
(1.AcquireByte )->(58)->(!59)	Covered	T3,T5,T22
(1.AcquireByte )->(!58)	Covered	T3,T5,T22
(1.AcquireAckWait )->(60)	Covered	T3,T5,T22
(1.AcquireAckWait )->(!60)	Not Covered
(1.AcquireAckSetup )->(61)	Covered	T3,T5,T22
(1.AcquireAckSetup )->(!61)	Covered	T3,T5,T22
(1.AcquireAckPulse )->(62)	Covered	T3,T5,T22
(1.AcquireAckPulse )->(!62)	Covered	T3,T5,T22
(1.AcquireAckHold )->(63)->(64)	Covered	T41,T34
(1.AcquireAckHold )->(63)->(!64)	Covered	T3,T5,T22
(1.AcquireAckHold )->(!63)	Not Covered
(1.NackWait )->(65)	Not Covered
(1.NackWait )->(!65)	Not Covered
(1.NackSetup )->(66)	Not Covered
(1.NackSetup )->(!66)	Not Covered
(1.NackPulse )->(67)	Not Covered
(1.NackPulse )->(!67)	Not Covered
(1.NackHold )->(68)	Not Covered
(1.NackHold )->(!68)	Not Covered
(1.StretchAddr )->(69)->(70)	Not Covered
(1.StretchAddr )->(69)->(!70)	Covered	T34
(1.StretchAddr )->(!69)	Covered	T34
(1.StretchTx )->(71)	Covered	T3,T4,T22
(1.StretchTx )->(!71)	Covered	T3,T4,T22
(1.StretchTxSetup )->(72)	Covered	T3,T4,T22
(1.StretchTxSetup )->(!72)	Covered	T3,T4,T22
(1.StretchAcqFull )->(73)	Covered	T41,T34
(1.StretchAcqFull )->(!73)	Covered	T41,T34
(1.default)	Not Covered

	LineNo.	Expression
-1-:	1578	if (((!target_idle) && (!target_enable_i)))
-2-:	1588	if (start_det)
-3-:	1590	if (stop_det)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T3,T4,T5
0	0	1	Covered	T3,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1597	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1606	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : i2c_fsm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AcqDepthRdCheck_A	216922019	2552386	0	0
AcqFifoDeepEnough_A	216922019	216796821	0	0
SclInputGlitch_A	208640474	6620609	0	0
SclOutputGlitch_A	216922019	2954384	0	0
SclSdaChangeNotSimultaneous_A	216922019	216796821	0	0

AcqDepthRdCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216922019	2552386	0	0
T3	268484	6330	0	0
T4	64514	279	0	0
T5	70467	368	0	0
T6	13556	0	0	0
T10	286489	0	0	0
T22	845299	17180	0	0
T45	53419	215	0	0
T55	965772	39704	0	0
T56	242539	8962	0	0
T57	523299	9563	0	0
T58	0	16975	0	0
T59	0	685	0	0

AcqFifoDeepEnough_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216922019	216796821	0	0
T1	160834	160781	0	0
T2	124125	124037	0	0
T3	268484	268424	0	0
T4	64514	64455	0	0
T5	70467	70374	0	0
T6	13556	13467	0	0
T10	286489	286389	0	0
T22	845299	845203	0	0
T55	965772	965714	0	0
T56	242539	242446	0	0

SclInputGlitch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208640474	6620609	0	0
T1	160834	8408	0	0
T2	124125	7047	0	0
T3	268484	13134	0	0
T4	64514	3603	0	0
T5	70467	4306	0	0
T6	13556	0	0	0
T10	286489	15236	0	0
T22	845299	6508	0	0
T45	0	2653	0	0
T55	965772	38960	0	0
T56	242539	8969	0	0

SclOutputGlitch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216922019	2954384	0	0
T1	160834	8408	0	0
T2	124125	7047	0	0
T3	268484	66	0	0
T4	64514	147	0	0
T5	70467	0	0	0
T6	13556	0	0	0
T10	286489	15236	0	0
T22	845299	176	0	0
T45	0	16	0	0
T55	965772	351	0	0
T56	242539	68	0	0
T57	0	125	0	0

SclSdaChangeNotSimultaneous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216922019	216796821	0	0
T1	160834	160781	0	0
T2	124125	124037	0	0
T3	268484	268424	0	0
T4	64514	64455	0	0
T5	70467	70374	0	0
T6	13556	13467	0	0
T10	286489	286389	0	0
T22	845299	845203	0	0
T55	965772	965714	0	0
T56	242539	242446	0	0