Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	217546889	9042	0	0
ctrl_rd_A	217546889	1335	0	0
host_fifo_config_rd_A	217546889	4009	0	0
host_timeout_ctrl_rd_A	217546889	800	0	0
intr_enable_rd_A	217546889	4319	0	0
ovrd_rd_A	217546889	2076	0	0
target_fifo_config_rd_A	217546889	1133	0	0
target_id_rd_A	217546889	1641	0	0
target_timeout_ctrl_rd_A	217546889	1168	0	0
timeout_ctrl_rd_A	217546889	1069	0	0
timing0_rd_A	217546889	1137	0	0
timing1_rd_A	217546889	1070	0	0
timing2_rd_A	217546889	1041	0	0
timing3_rd_A	217546889	1037	0	0
timing4_rd_A	217546889	1062	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217546889	9042	0	0
T75	4401	603	0	0
T76	6719	191	0	0
T77	1411	15	0	0
T78	9711	489	0	0
T79	4433	4	0	0
T83	12546	5	0	0
T85	2185	15	0	0
T86	7246	216	0	0
T94	2192	358	0	0
T113	1762	32	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217546889	1335	0	0
T83	12546	155	0	0
T84	13695	143	0	0
T85	2185	6	0	0
T86	7246	5	0	0
T88	11509	5	0	0
T95	6709	85	0	0
T130	6193	49	0	0
T131	4697	18	0	0
T133	3753	6	0	0
T137	2814	45	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217546889	4009	0	0
T13	502075	0	0	0
T138	344505	68	0	0
T139	384328	208	0	0
T140	277330	75	0	0
T141	0	162	0	0
T142	0	105	0	0
T143	0	142	0	0
T144	0	134	0	0
T145	0	207	0	0
T146	0	80	0	0
T147	0	186	0	0
T148	193183	0	0	0
T149	846985	0	0	0
T150	194494	0	0	0
T151	149852	0	0	0
T152	8911	0	0	0
T153	145025	0	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217546889	800	0	0
T83	12546	63	0	0
T84	13695	73	0	0
T85	2185	13	0	0
T86	7246	1	0	0
T88	11509	6	0	0
T95	6709	46	0	0
T130	6193	65	0	0
T131	4697	19	0	0
T133	3753	30	0	0
T137	2814	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217546889	4319	0	0
T28	4947	0	0	0
T83	0	540	0	0
T85	0	13	0	0
T86	0	20	0	0
T102	154473	66	0	0
T130	0	49	0	0
T131	0	26	0	0
T154	0	6	0	0
T155	0	16	0	0
T156	0	19	0	0
T157	0	11	0	0
T158	159820	0	0	0
T159	33361	0	0	0
T160	1054	0	0	0
T161	114003	0	0	0
T162	90533	0	0	0
T163	154634	0	0	0
T164	265578	0	0	0
T165	114399	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217546889	2076	0	0
T18	1326	27	0	0
T27	107290	0	0	0
T31	170763	0	0	0
T32	12303	0	0	0
T47	5119	0	0	0
T166	0	46	0	0
T167	0	30	0	0
T168	0	80	0	0
T169	0	75	0	0
T170	0	41	0	0
T171	0	67	0	0
T172	0	55	0	0
T173	0	40	0	0
T174	0	39	0	0
T175	99519	0	0	0
T176	168888	0	0	0
T177	22150	0	0	0
T178	1255	0	0	0
T179	488381	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217546889	1133	0	0
T83	12546	114	0	0
T84	13695	99	0	0
T85	2185	11	0	0
T88	11509	23	0	0
T95	6709	25	0	0
T130	6193	50	0	0
T131	4697	18	0	0
T133	3753	45	0	0
T137	2814	30	0	0
T180	2537	13	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217546889	1641	0	0
T83	12546	263	0	0
T84	13695	197	0	0
T85	2185	15	0	0
T86	7246	26	0	0
T88	11509	8	0	0
T95	6709	105	0	0
T130	6193	59	0	0
T131	4697	25	0	0
T133	3753	15	0	0
T137	2814	36	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217546889	1168	0	0
T83	12546	119	0	0
T84	13695	106	0	0
T85	2185	2	0	0
T86	7246	25	0	0
T88	11509	8	0	0
T95	6709	80	0	0
T130	6193	60	0	0
T131	4697	47	0	0
T133	3753	8	0	0
T137	2814	13	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217546889	1069	0	0
T83	12546	166	0	0
T84	13695	152	0	0
T85	2185	10	0	0
T86	7246	11	0	0
T88	11509	1	0	0
T95	6709	59	0	0
T130	6193	42	0	0
T131	4697	6	0	0
T133	3753	30	0	0
T137	2814	35	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217546889	1137	0	0
T83	12546	92	0	0
T84	13695	139	0	0
T85	2185	20	0	0
T86	7246	48	0	0
T88	11509	19	0	0
T95	6709	95	0	0
T130	6193	28	0	0
T131	4697	34	0	0
T137	2814	11	0	0
T180	2537	8	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217546889	1070	0	0
T83	12546	120	0	0
T84	13695	120	0	0
T85	2185	9	0	0
T86	7246	13	0	0
T88	11509	16	0	0
T95	6709	59	0	0
T130	6193	25	0	0
T131	4697	8	0	0
T133	3753	62	0	0
T137	2814	22	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217546889	1041	0	0
T83	12546	122	0	0
T84	13695	135	0	0
T85	2185	2	0	0
T86	7246	8	0	0
T88	11509	3	0	0
T95	6709	44	0	0
T130	6193	48	0	0
T131	4697	22	0	0
T133	3753	13	0	0
T137	2814	24	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217546889	1037	0	0
T83	12546	110	0	0
T84	13695	135	0	0
T85	2185	13	0	0
T86	7246	13	0	0
T88	11509	16	0	0
T95	6709	48	0	0
T130	6193	84	0	0
T131	4697	12	0	0
T133	3753	2	0	0
T137	2814	31	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217546889	1062	0	0
T83	12546	138	0	0
T84	13695	100	0	0
T85	2185	10	0	0
T88	11509	13	0	0
T95	6709	45	0	0
T130	6193	16	0	0
T131	4697	32	0	0
T133	3753	20	0	0
T137	2814	15	0	0
T180	2537	6	0	0