Unified Coverage Report :: Module :: i2c_reg_top

Module : i2c_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.91	100.00	99.66			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	99.91	100.00	99.66			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.91	100.00	99.66			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.97	98.63	98.63	100.00		97.59	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.72	100.00	100.00	94.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_acqdata_abyte	100.00	100.00
u_acqdata_signal	100.00	100.00
u_alert_test	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_ctrl_enablehost	100.00	100.00	100.00			100.00
u_ctrl_enabletarget	100.00	100.00	100.00			100.00
u_ctrl_llpbk	100.00	100.00	100.00			100.00
u_fdata0_qe	100.00	100.00				100.00
u_fdata_fbyte	100.00	100.00	100.00			100.00
u_fdata_nakok	100.00	100.00	100.00			100.00
u_fdata_rcont	100.00	100.00	100.00			100.00
u_fdata_readb	100.00	100.00	100.00			100.00
u_fdata_start	100.00	100.00	100.00			100.00
u_fdata_stop	100.00	100.00	100.00			100.00
u_fifo_ctrl0_qe	100.00	100.00				100.00
u_fifo_ctrl_acqrst	100.00	100.00	100.00			100.00
u_fifo_ctrl_fmtrst	100.00	100.00	100.00			100.00
u_fifo_ctrl_rxrst	100.00	100.00	100.00			100.00
u_fifo_ctrl_txrst	100.00	100.00	100.00			100.00
u_host_fifo_config0_qe	100.00	100.00				100.00
u_host_fifo_config_fmt_thresh	100.00	100.00	100.00			100.00
u_host_fifo_config_rx_thresh	100.00	100.00	100.00			100.00
u_host_fifo_status_fmtlvl	100.00	100.00
u_host_fifo_status_rxlvl	100.00	100.00
u_host_timeout_ctrl	100.00	100.00	100.00			100.00
u_intr_enable_acq_full	100.00	100.00	100.00			100.00
u_intr_enable_acq_threshold	100.00	100.00	100.00			100.00
u_intr_enable_cmd_complete	100.00	100.00	100.00			100.00
u_intr_enable_fmt_threshold	100.00	100.00	100.00			100.00
u_intr_enable_host_timeout	100.00	100.00	100.00			100.00
u_intr_enable_nak	100.00	100.00	100.00			100.00
u_intr_enable_rx_overflow	100.00	100.00	100.00			100.00
u_intr_enable_rx_threshold	100.00	100.00	100.00			100.00
u_intr_enable_scl_interference	100.00	100.00	100.00			100.00
u_intr_enable_sda_interference	100.00	100.00	100.00			100.00
u_intr_enable_sda_unstable	100.00	100.00	100.00			100.00
u_intr_enable_stretch_timeout	100.00	100.00	100.00			100.00
u_intr_enable_tx_stretch	100.00	100.00	100.00			100.00
u_intr_enable_tx_threshold	100.00	100.00	100.00			100.00
u_intr_enable_unexp_stop	100.00	100.00	100.00			100.00
u_intr_state_acq_full	62.59	77.78	50.00			60.00
u_intr_state_acq_threshold	62.59	77.78	50.00			60.00
u_intr_state_cmd_complete	100.00	100.00	100.00			100.00
u_intr_state_fmt_threshold	62.59	77.78	50.00			60.00
u_intr_state_host_timeout	100.00	100.00	100.00			100.00
u_intr_state_nak	100.00	100.00	100.00			100.00
u_intr_state_rx_overflow	100.00	100.00	100.00			100.00
u_intr_state_rx_threshold	62.59	77.78	50.00			60.00
u_intr_state_scl_interference	100.00	100.00	100.00			100.00
u_intr_state_sda_interference	100.00	100.00	100.00			100.00
u_intr_state_sda_unstable	100.00	100.00	100.00			100.00
u_intr_state_stretch_timeout	100.00	100.00	100.00			100.00
u_intr_state_tx_stretch	62.59	77.78	50.00			60.00
u_intr_state_tx_threshold	62.59	77.78	50.00			60.00
u_intr_state_unexp_stop	100.00	100.00	100.00			100.00
u_intr_test_acq_full	100.00	100.00
u_intr_test_acq_threshold	100.00	100.00
u_intr_test_cmd_complete	100.00	100.00
u_intr_test_fmt_threshold	100.00	100.00
u_intr_test_host_timeout	100.00	100.00
u_intr_test_nak	100.00	100.00
u_intr_test_rx_overflow	100.00	100.00
u_intr_test_rx_threshold	100.00	100.00
u_intr_test_scl_interference	100.00	100.00
u_intr_test_sda_interference	100.00	100.00
u_intr_test_sda_unstable	100.00	100.00
u_intr_test_stretch_timeout	100.00	100.00
u_intr_test_tx_stretch	100.00	100.00
u_intr_test_tx_threshold	100.00	100.00
u_intr_test_unexp_stop	100.00	100.00
u_ovrd_sclval	100.00	100.00	100.00			100.00
u_ovrd_sdaval	100.00	100.00	100.00			100.00
u_ovrd_txovrden	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_rdata	100.00	100.00
u_reg_if	98.67	97.14	97.53			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_status_acqempty	100.00	100.00
u_status_acqfull	100.00	100.00
u_status_fmtempty	100.00	100.00
u_status_fmtfull	100.00	100.00
u_status_hostidle	100.00	100.00
u_status_rxempty	100.00	100.00
u_status_rxfull	100.00	100.00
u_status_targetidle	100.00	100.00
u_status_txempty	100.00	100.00
u_status_txfull	100.00	100.00
u_target_fifo_config0_qe	100.00	100.00				100.00
u_target_fifo_config_acq_thresh	100.00	100.00	100.00			100.00
u_target_fifo_config_tx_thresh	100.00	100.00	100.00			100.00
u_target_fifo_config_txrst_on_cond	100.00	100.00	100.00			100.00
u_target_fifo_status_acqlvl	100.00	100.00
u_target_fifo_status_txlvl	100.00	100.00
u_target_id_address0	100.00	100.00	100.00			100.00
u_target_id_address1	100.00	100.00	100.00			100.00
u_target_id_mask0	100.00	100.00	100.00			100.00
u_target_id_mask1	100.00	100.00	100.00			100.00
u_target_nack_count	81.90	100.00	60.00			85.71
u_target_timeout_ctrl_en	100.00	100.00	100.00			100.00
u_target_timeout_ctrl_val	100.00	100.00	100.00			100.00
u_timeout_ctrl_en	100.00	100.00	100.00			100.00
u_timeout_ctrl_val	100.00	100.00	100.00			100.00
u_timing0_thigh	100.00	100.00	100.00			100.00
u_timing0_tlow	100.00	100.00	100.00			100.00
u_timing1_t_f	100.00	100.00	100.00			100.00
u_timing1_t_r	100.00	100.00	100.00			100.00
u_timing2_thd_sta	100.00	100.00	100.00			100.00
u_timing2_tsu_sta	100.00	100.00	100.00			100.00
u_timing3_thd_dat	100.00	100.00	100.00			100.00
u_timing3_tsu_dat	100.00	100.00	100.00			100.00
u_timing4_t_buf	100.00	100.00	100.00			100.00
u_timing4_tsu_sto	100.00	100.00	100.00			100.00
u_txdata	100.00	100.00	100.00			100.00
u_txdata0_qe	100.00	100.00				100.00
u_val_scl_rx	66.67	66.67
u_val_sda_rx	66.67	66.67

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c_reg_top

	Line No.	Total	Covered	Percent
TOTAL		320	320	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	1132	1	1	100.00
CONT_ASSIGN	1147	1	1	100.00
CONT_ASSIGN	1163	1	1	100.00
CONT_ASSIGN	1179	1	1	100.00
CONT_ASSIGN	1195	1	1	100.00
CONT_ASSIGN	1211	1	1	100.00
CONT_ASSIGN	1227	1	1	100.00
CONT_ASSIGN	1243	1	1	100.00
CONT_ASSIGN	1259	1	1	100.00
CONT_ASSIGN	1275	1	1	100.00
CONT_ASSIGN	1291	1	1	100.00
CONT_ASSIGN	1307	1	1	100.00
CONT_ASSIGN	1323	1	1	100.00
CONT_ASSIGN	1339	1	1	100.00
CONT_ASSIGN	1355	1	1	100.00
CONT_ASSIGN	1371	1	1	100.00
CONT_ASSIGN	1377	1	1	100.00
CONT_ASSIGN	1391	1	1	100.00
CONT_ASSIGN	1683	1	1	100.00
CONT_ASSIGN	1711	1	1	100.00
CONT_ASSIGN	1739	1	1	100.00
CONT_ASSIGN	1767	1	1	100.00
CONT_ASSIGN	1795	1	1	100.00
CONT_ASSIGN	1823	1	1	100.00
CONT_ASSIGN	1864	1	1	100.00
CONT_ASSIGN	1892	1	1	100.00
CONT_ASSIGN	1920	1	1	100.00
CONT_ASSIGN	1948	1	1	100.00
CONT_ASSIGN	1989	1	1	100.00
CONT_ASSIGN	2017	1	1	100.00
CONT_ASSIGN	2058	1	1	100.00
CONT_ASSIGN	2086	1	1	100.00
CONT_ASSIGN	2114	1	1	100.00
CONT_ASSIGN	2811	1	1	100.00
ALWAYS	2929	28	28	100.00
CONT_ASSIGN	2959	1	1	100.00
ALWAYS	2963	1	1	100.00
CONT_ASSIGN	2994	1	1	100.00
CONT_ASSIGN	2996	1	1	100.00
CONT_ASSIGN	2998	1	1	100.00
CONT_ASSIGN	3000	1	1	100.00
CONT_ASSIGN	3002	1	1	100.00
CONT_ASSIGN	3004	1	1	100.00
CONT_ASSIGN	3006	1	1	100.00
CONT_ASSIGN	3008	1	1	100.00
CONT_ASSIGN	3010	1	1	100.00
CONT_ASSIGN	3012	1	1	100.00
CONT_ASSIGN	3013	1	1	100.00
CONT_ASSIGN	3015	1	1	100.00
CONT_ASSIGN	3017	1	1	100.00
CONT_ASSIGN	3019	1	1	100.00
CONT_ASSIGN	3021	1	1	100.00
CONT_ASSIGN	3023	1	1	100.00
CONT_ASSIGN	3025	1	1	100.00
CONT_ASSIGN	3027	1	1	100.00
CONT_ASSIGN	3029	1	1	100.00
CONT_ASSIGN	3031	1	1	100.00
CONT_ASSIGN	3033	1	1	100.00
CONT_ASSIGN	3035	1	1	100.00
CONT_ASSIGN	3037	1	1	100.00
CONT_ASSIGN	3039	1	1	100.00
CONT_ASSIGN	3041	1	1	100.00
CONT_ASSIGN	3043	1	1	100.00
CONT_ASSIGN	3044	1	1	100.00
CONT_ASSIGN	3046	1	1	100.00
CONT_ASSIGN	3048	1	1	100.00
CONT_ASSIGN	3050	1	1	100.00
CONT_ASSIGN	3052	1	1	100.00
CONT_ASSIGN	3054	1	1	100.00
CONT_ASSIGN	3056	1	1	100.00
CONT_ASSIGN	3058	1	1	100.00
CONT_ASSIGN	3060	1	1	100.00
CONT_ASSIGN	3062	1	1	100.00
CONT_ASSIGN	3064	1	1	100.00
CONT_ASSIGN	3066	1	1	100.00
CONT_ASSIGN	3068	1	1	100.00
CONT_ASSIGN	3070	1	1	100.00
CONT_ASSIGN	3072	1	1	100.00
CONT_ASSIGN	3074	1	1	100.00
CONT_ASSIGN	3075	1	1	100.00
CONT_ASSIGN	3077	1	1	100.00
CONT_ASSIGN	3078	1	1	100.00
CONT_ASSIGN	3080	1	1	100.00
CONT_ASSIGN	3082	1	1	100.00
CONT_ASSIGN	3084	1	1	100.00
CONT_ASSIGN	3085	1	1	100.00
CONT_ASSIGN	3086	1	1	100.00
CONT_ASSIGN	3087	1	1	100.00
CONT_ASSIGN	3089	1	1	100.00
CONT_ASSIGN	3091	1	1	100.00
CONT_ASSIGN	3093	1	1	100.00
CONT_ASSIGN	3095	1	1	100.00
CONT_ASSIGN	3097	1	1	100.00
CONT_ASSIGN	3099	1	1	100.00
CONT_ASSIGN	3100	1	1	100.00
CONT_ASSIGN	3102	1	1	100.00
CONT_ASSIGN	3104	1	1	100.00
CONT_ASSIGN	3106	1	1	100.00
CONT_ASSIGN	3108	1	1	100.00
CONT_ASSIGN	3109	1	1	100.00
CONT_ASSIGN	3111	1	1	100.00
CONT_ASSIGN	3113	1	1	100.00
CONT_ASSIGN	3114	1	1	100.00
CONT_ASSIGN	3116	1	1	100.00
CONT_ASSIGN	3118	1	1	100.00
CONT_ASSIGN	3120	1	1	100.00
CONT_ASSIGN	3121	1	1	100.00
CONT_ASSIGN	3122	1	1	100.00
CONT_ASSIGN	3123	1	1	100.00
CONT_ASSIGN	3125	1	1	100.00
CONT_ASSIGN	3127	1	1	100.00
CONT_ASSIGN	3129	1	1	100.00
CONT_ASSIGN	3130	1	1	100.00
CONT_ASSIGN	3131	1	1	100.00
CONT_ASSIGN	3133	1	1	100.00
CONT_ASSIGN	3135	1	1	100.00
CONT_ASSIGN	3136	1	1	100.00
CONT_ASSIGN	3138	1	1	100.00
CONT_ASSIGN	3140	1	1	100.00
CONT_ASSIGN	3141	1	1	100.00
CONT_ASSIGN	3143	1	1	100.00
CONT_ASSIGN	3145	1	1	100.00
CONT_ASSIGN	3146	1	1	100.00
CONT_ASSIGN	3148	1	1	100.00
CONT_ASSIGN	3150	1	1	100.00
CONT_ASSIGN	3151	1	1	100.00
CONT_ASSIGN	3153	1	1	100.00
CONT_ASSIGN	3155	1	1	100.00
CONT_ASSIGN	3156	1	1	100.00
CONT_ASSIGN	3158	1	1	100.00
CONT_ASSIGN	3160	1	1	100.00
CONT_ASSIGN	3161	1	1	100.00
CONT_ASSIGN	3163	1	1	100.00
CONT_ASSIGN	3165	1	1	100.00
CONT_ASSIGN	3167	1	1	100.00
CONT_ASSIGN	3169	1	1	100.00
CONT_ASSIGN	3170	1	1	100.00
CONT_ASSIGN	3171	1	1	100.00
CONT_ASSIGN	3173	1	1	100.00
CONT_ASSIGN	3174	1	1	100.00
CONT_ASSIGN	3176	1	1	100.00
CONT_ASSIGN	3177	1	1	100.00
CONT_ASSIGN	3179	1	1	100.00
CONT_ASSIGN	3181	1	1	100.00
CONT_ASSIGN	3182	1	1	100.00
ALWAYS	3188	28	28	100.00
ALWAYS	3220	109	109	100.00
CONT_ASSIGN	3421	0	0
CONT_ASSIGN	3429	1	1	100.00
CONT_ASSIGN	3430	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
77	1	1
89	1	1
90	1	1
118	1	1
119	1	1
1132	1	1
1147	1	1
1163	1	1
1179	1	1
1195	1	1
1211	1	1
1227	1	1
1243	1	1
1259	1	1
1275	1	1
1291	1	1
1307	1	1
1323	1	1
1339	1	1
1355	1	1
1371	1	1
1377	1	1
1391	1	1
1683	1	1
1711	1	1
1739	1	1
1767	1	1
1795	1	1
1823	1	1
1864	1	1
1892	1	1
1920	1	1
1948	1	1
1989	1	1
2017	1	1
2058	1	1
2086	1	1
2114	1	1
2811	1	1
2929	1	1
2930	1	1
2931	1	1
2932	1	1
2933	1	1
2934	1	1
2935	1	1
2936	1	1
2937	1	1
2938	1	1
2939	1	1
2940	1	1
2941	1	1
2942	1	1
2943	1	1
2944	1	1
2945	1	1
2946	1	1
2947	1	1
2948	1	1
2949	1	1
2950	1	1
2951	1	1
2952	1	1
2953	1	1
2954	1	1
2955	1	1
2956	1	1
2959	1	1
2963	1	1
2994	1	1
2996	1	1
2998	1	1
3000	1	1
3002	1	1
3004	1	1
3006	1	1
3008	1	1
3010	1	1
3012	1	1
3013	1	1
3015	1	1
3017	1	1
3019	1	1
3021	1	1
3023	1	1
3025	1	1
3027	1	1
3029	1	1
3031	1	1
3033	1	1
3035	1	1
3037	1	1
3039	1	1
3041	1	1
3043	1	1
3044	1	1
3046	1	1
3048	1	1
3050	1	1
3052	1	1
3054	1	1
3056	1	1
3058	1	1
3060	1	1
3062	1	1
3064	1	1
3066	1	1
3068	1	1
3070	1	1
3072	1	1
3074	1	1
3075	1	1
3077	1	1
3078	1	1
3080	1	1
3082	1	1
3084	1	1
3085	1	1
3086	1	1
3087	1	1
3089	1	1
3091	1	1
3093	1	1
3095	1	1
3097	1	1
3099	1	1
3100	1	1
3102	1	1
3104	1	1
3106	1	1
3108	1	1
3109	1	1
3111	1	1
3113	1	1
3114	1	1
3116	1	1
3118	1	1
3120	1	1
3121	1	1
3122	1	1
3123	1	1
3125	1	1
3127	1	1
3129	1	1
3130	1	1
3131	1	1
3133	1	1
3135	1	1
3136	1	1
3138	1	1
3140	1	1
3141	1	1
3143	1	1
3145	1	1
3146	1	1
3148	1	1
3150	1	1
3151	1	1
3153	1	1
3155	1	1
3156	1	1
3158	1	1
3160	1	1
3161	1	1
3163	1	1
3165	1	1
3167	1	1
3169	1	1
3170	1	1
3171	1	1
3173	1	1
3174	1	1
3176	1	1
3177	1	1
3179	1	1
3181	1	1
3182	1	1
3188	1	1
3189	1	1
3190	1	1
3191	1	1
3192	1	1
3193	1	1
3194	1	1
3195	1	1
3196	1	1
3197	1	1
3198	1	1
3199	1	1
3200	1	1
3201	1	1
3202	1	1
3203	1	1
3204	1	1
3205	1	1
3206	1	1
3207	1	1
3208	1	1
3209	1	1
3210	1	1
3211	1	1
3212	1	1
3213	1	1
3214	1	1
3215	1	1
3220	1	1
3221	1	1
3223	1	1
3224	1	1
3225	1	1
3226	1	1
3227	1	1
3228	1	1
3229	1	1
3230	1	1
3231	1	1
3232	1	1
3233	1	1
3234	1	1
3235	1	1
3236	1	1
3237	1	1
3241	1	1
3242	1	1
3243	1	1
3244	1	1
3245	1	1
3246	1	1
3247	1	1
3248	1	1
3249	1	1
3250	1	1
3251	1	1
3252	1	1
3253	1	1
3254	1	1
3255	1	1
3259	1	1
3260	1	1
3261	1	1
3262	1	1
3263	1	1
3264	1	1
3265	1	1
3266	1	1
3267	1	1
3268	1	1
3269	1	1
3270	1	1
3271	1	1
3272	1	1
3273	1	1
3277	1	1
3281	1	1
3282	1	1
3283	1	1
3287	1	1
3288	1	1
3289	1	1
3290	1	1
3291	1	1
3292	1	1
3293	1	1
3294	1	1
3295	1	1
3296	1	1
3300	1	1
3304	1	1
3305	1	1
3306	1	1
3307	1	1
3308	1	1
3309	1	1
3313	1	1
3314	1	1
3315	1	1
3316	1	1
3320	1	1
3321	1	1
3325	1	1
3326	1	1
3327	1	1
3331	1	1
3332	1	1
3336	1	1
3337	1	1
3341	1	1
3342	1	1
3343	1	1
3347	1	1
3348	1	1
3352	1	1
3353	1	1
3357	1	1
3358	1	1
3362	1	1
3363	1	1
3367	1	1
3368	1	1
3372	1	1
3373	1	1
3377	1	1
3378	1	1
3382	1	1
3383	1	1
3384	1	1
3385	1	1
3389	1	1
3390	1	1
3394	1	1
3398	1	1
3402	1	1
3403	1	1
3407	1	1
3421		unreachable
3429	1	1
3430	1	1

---

Cond Coverage for Module : i2c_reg_top

	Total	Covered	Percent
Conditions	293	292	99.66
Logical	293	292	99.66
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T97,T98,T106
1	1	Covered	T1,T2,T3

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T96,T99,T100
1	0	Covered	T107,T108,T109

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T96,T99,T100
0	1	0	Covered	T107,T108,T109
1	0	0	Covered	T96,T99,T100

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T107,T108,T109
0	1	0	Covered	T97,T72,T98
1	0	0	Covered	T97,T98,T105

 LINE       2930
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_INTR_STATE_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2931
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_INTR_ENABLE_OFFSET)
            ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2932
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_INTR_TEST_OFFSET)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T14,T50

 LINE       2933
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_ALERT_TEST_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T14,T50

 LINE       2934
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_CTRL_OFFSET)
            ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2935
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_STATUS_OFFSET)
            ----------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2936
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_RDATA_OFFSET)
            ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T14

 LINE       2937
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_FDATA_OFFSET)
            ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       2938
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_FIFO_CTRL_OFFSET)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2939
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_HOST_FIFO_CONFIG_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2940
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_FIFO_CONFIG_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2941
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_HOST_FIFO_STATUS_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T14

 LINE       2942
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_FIFO_STATUS_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       2943
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_OVRD_OFFSET)
            ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T9,T14

 LINE       2944
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_VAL_OFFSET)
            --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T14,T50

 LINE       2945
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING0_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2946
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING1_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2947
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING2_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2948
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING3_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2949
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING4_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2950
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMEOUT_CTRL_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2951
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_ID_OFFSET)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       2952
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_ACQDATA_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       2953
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TXDATA_OFFSET)
            ----------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       2954
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_HOST_TIMEOUT_CTRL_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       2955
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_TIMEOUT_CTRL_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T14,T50

 LINE       2956
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_NACK_COUNT_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T14,T50

 LINE       2959
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2959
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       2963
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[2] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[8] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T97,T72,T98

 LINE       2963
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b0011 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b0011 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b0011 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b0011 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T1,T2,T3
27 (addr_hit[26] & ((|(4'...	Covered	T4,T14,T50
26 (addr_hit[25] & ((|(4'...	Covered	T4,T14,T50
25 (addr_hit[24] & ((|(4'...	Covered	T4,T14,T50
24 (addr_hit[23] & ((|(4'...	Covered	T4,T14,T50
23 (addr_hit[22] & ((|(4'...	Covered	T2,T4,T5
22 (addr_hit[21] & ((|(4'...	Covered	T4,T14,T50
21 (addr_hit[20] & ((|(4'...	Covered	T4,T14,T50
20 (addr_hit[19] & ((|(4'...	Covered	T4,T14,T50
19 (addr_hit[18] & ((|(4'...	Covered	T4,T14,T50
18 (addr_hit[17] & ((|(4'...	Covered	T4,T14,T50
17 (addr_hit[16] & ((|(4'...	Covered	T4,T14,T50
16 (addr_hit[15] & ((|(4'...	Covered	T4,T14,T50
15 (addr_hit[14] & ((|(4'...	Covered	T4,T14,T50
14 (addr_hit[13] & ((|(4'...	Covered	T4,T9,T14
13 (addr_hit[12] & ((|(4'...	Covered	T4,T5,T7
12 (addr_hit[11] & ((|(4'...	Covered	T4,T8,T14
11 (addr_hit[10] & ((|(4'...	Covered	T4,T14,T50
10 (addr_hit[9] & ((|(4'b...	Covered	T4,T14,T50
9 (addr_hit[8] & ((|(4'b...	Covered	T4,T14,T50
8 (addr_hit[7] & ((|(4'b...	Covered	T4,T14,T50
7 (addr_hit[6] & ((|(4'b...	Covered	T1,T4,T14
6 (addr_hit[5] & ((|(4'b...	Covered	T1,T2,T3
5 (addr_hit[4] & ((|(4'b...	Covered	T4,T14,T50
4 (addr_hit[3] & ((|(4'b...	Covered	T4,T14,T50
3 (addr_hit[2] & ((|(4'b...	Covered	T4,T14,T50
2 (addr_hit[1] & ((|(4'b...	Covered	T4,T14,T50
1 (addr_hit[0] & ((|(4'b...	Covered	T1,T2,T3

 LINE       2963
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       2963
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T14,T50

 LINE       2963
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T14,T50
1	1	Covered	T4,T14,T50

 LINE       2963
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T14,T50
1	1	Covered	T4,T14,T50

 LINE       2963
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T14,T50

 LINE       2963
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       2963
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T14
1	1	Covered	T1,T4,T14

 LINE       2963
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T4,T14,T50

 LINE       2963
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T14,T50

 LINE       2963
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T14,T50

 LINE       2963
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T14,T50

 LINE       2963
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T14,T50
1	1	Covered	T4,T8,T14

 LINE       2963
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T14,T50
1	1	Covered	T4,T5,T7

 LINE       2963
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T9,T14
1	1	Covered	T4,T9,T14

 LINE       2963
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T14,T50
1	1	Covered	T4,T14,T50

 LINE       2963
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T14,T50

 LINE       2963
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T14,T50

 LINE       2963
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T14,T50

 LINE       2963
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T14,T50

 LINE       2963
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T14,T50

 LINE       2963
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T14,T50

 LINE       2963
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T4,T14,T50

 LINE       2963
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       2963
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T14,T50

 LINE       2963
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T4,T14,T50

 LINE       2963
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T14,T50
1	1	Covered	T4,T14,T50

 LINE       2963
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T14,T50
1	1	Covered	T4,T14,T50

 LINE       2994
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T97,T72,T106
1	1	1	Covered	T1,T2,T3

 LINE       3013
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T97,T98,T106
1	1	1	Covered	T1,T2,T3

 LINE       3044
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T14,T50
1	1	0	Covered	T97,T98,T107
1	1	1	Covered	T74,T75,T76

 LINE       3075
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T14,T50
1	1	0	Covered	T97,T98,T107
1	1	1	Covered	T93,T94,T95

 LINE       3078
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T98,T106,T110
1	1	1	Covered	T1,T2,T3

 LINE       3085
 EXPRESSION (addr_hit[5] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T111,T112,T113
1	1	1	Covered	T1,T2,T3

 LINE       3086
 EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T4,T14
1	1	0	Covered	T114,T115,T116
1	1	1	Covered	T1,T14,T15

 LINE       3087
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T97,T98,T107
1	1	1	Covered	T1,T3,T6

 LINE       3100
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T98,T106,T117
1	1	1	Covered	T1,T2,T3

 LINE       3109
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T72,T98,T106
1	1	1	Covered	T1,T2,T3

 LINE       3114
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T72,T98,T106
1	1	1	Covered	T1,T2,T3

 LINE       3121
 EXPRESSION (addr_hit[11] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T8,T14
1	1	0	Covered	T107
1	1	1	Covered	T8,T34,T78

 LINE       3122
 EXPRESSION (addr_hit[12] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T7
1	1	0	Covered	T118,T119
1	1	1	Covered	T4,T5,T7

 LINE       3123
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T9,T14
1	1	0	Covered	T98,T106,T120
1	1	1	Covered	T9,T21,T55

 LINE       3130
 EXPRESSION (addr_hit[14] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T14,T50
1	1	0	Covered	T121,T122,T123
1	1	1	Not Covered

 LINE       3131
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T98,T106,T108
1	1	1	Covered	T1,T2,T3

 LINE       3136
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T97,T98,T107
1	1	1	Covered	T1,T2,T3

 LINE       3141
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T72,T98,T106
1	1	1	Covered	T1,T2,T3

 LINE       3146
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T98,T106,T124
1	1	1	Covered	T1,T2,T3

 LINE       3151
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T98,T106,T117
1	1	1	Covered	T1,T2,T3

 LINE       3156
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T98,T107,T125
1	1	1	Covered	T1,T2,T3

 LINE       3161
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T4,T5
1	1	0	Covered	T97,T98,T117
1	1	1	Covered	T2,T4,T5

 LINE       3170
 EXPRESSION (addr_hit[22] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T4,T5
1	1	0	Covered	T120,T121,T116
1	1	1	Covered	T2,T4,T5

 LINE       3171
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T7
1	1	0	Covered	T98,T106,T126
1	1	1	Covered	T4,T5,T7

 LINE       3174
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T4,T5
1	1	0	Covered	T98,T120,T125
1	1	1	Covered	T2,T4,T5

 LINE       3177
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T14,T50
1	1	0	Covered	T97,T72,T98
1	1	1	Covered	T71,T72,T73

 LINE       3182
 EXPRESSION (addr_hit[26] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T14,T50
1	1	0	Covered	T110,T122,T127
1	1	1	Covered	T71,T72,T73

---

Branch Coverage for Module : i2c_reg_top

	Line No.	Total	Covered	Percent
Branches		33	33	100.00
TERNARY	2959	2	2	100.00
IF	68	3	3	100.00
CASE	3221	28	28	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	2959	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	68	if ((!rst_ni))
-2-:	70	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T96,T99,T100
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	3221	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : i2c_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	220772187	33189923	0	0
reAfterRv	220772187	33189797	0	0
rePulse	220772187	30326001	0	0
wePulse	220772187	2863796	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	220772187	33189923	0	0
T1	125124	17613	0	0
T2	883956	260	0	0
T3	25003	2208	0	0
T4	121015	18767	0	0
T5	32099	651	0	0
T6	15274	2094	0	0
T7	54908	720	0	0
T8	15704	259	0	0
T9	1652	29	0	0
T10	786050	306456	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	220772187	33189797	0	0
T1	125124	17613	0	0
T2	883956	260	0	0
T3	25003	2208	0	0
T4	121015	18767	0	0
T5	32099	651	0	0
T6	15274	2094	0	0
T7	54908	720	0	0
T8	15704	259	0	0
T9	1652	29	0	0
T10	786050	306456	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	220772187	30326001	0	0
T1	125124	17497	0	0
T2	883956	243	0	0
T3	25003	2004	0	0
T4	121015	18391	0	0
T5	32099	495	0	0
T6	15274	1993	0	0
T7	54908	493	0	0
T8	15704	133	0	0
T9	1652	14	0	0
T10	786050	306332	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	220772187	2863796	0	0
T1	125124	116	0	0
T2	883956	17	0	0
T3	25003	204	0	0
T4	121015	376	0	0
T5	32099	156	0	0
T6	15274	101	0	0
T7	54908	227	0	0
T8	15704	126	0	0
T9	1652	15	0	0
T10	786050	124	0	0