Unified Coverage Report :: Module :: i2c

Module : i2c

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.72	100.00	100.00	94.87			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	98.72	100.00	100.00	94.87			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.72	100.00	100.00	94.87			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.17	97.38	90.88	97.65	43.87	94.77	98.44

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
i2c_core	82.24	96.43	84.57		43.87	92.48	93.86
i2c_csr_assert	100.00						100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_reg	98.97	98.63	98.63	100.00		97.59	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	130	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
129	1	1
130	1	1

---

Cond Coverage for Module : i2c

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       68
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T93,T94,T95
1	0	Covered	T1,T2,T3
1	1	Covered	T93,T94,T95

---

Toggle Coverage for Module : i2c

	Total	Covered	Percent
Totals	49	45	91.84
Total Bits	390	370	94.87
Total Bits 0->1	195	185	94.87
Total Bits 1->0	195	185	94.87

Ports	49	45	91.84
Port Bits	390	370	94.87
Port Bits 0->1	195	185	94.87
Port Bits 1->0	195	185	94.87

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T96,T43,T44	Yes	T1,T2,T3	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T14,T50	Yes	T4,T14,T50	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T97,T72,T98	Yes	T97,T72,T98	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T96,T93,T94	Yes	T96,T93,T94	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T96,T93,T94	Yes	T96,T93,T94	OUTPUT
cio_scl_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	OUTPUT
cio_sda_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T3,T6,T47	Yes	T1,T2,T3	OUTPUT
intr_rx_threshold_o	Yes	Yes	T1,T14,T33	Yes	T1,T14,T33	OUTPUT
intr_acq_threshold_o	Yes	Yes	T5,T7,T11	Yes	T5,T7,T11	OUTPUT
intr_rx_overflow_o	Yes	Yes	T1,T14,T33	Yes	T1,T14,T33	OUTPUT
intr_nak_o	Yes	Yes	T18,T75,T31	Yes	T18,T75,T31	OUTPUT
intr_scl_interference_o	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
intr_sda_interference_o	Yes	Yes	T1,T3,T6	Yes	T1,T3,T6	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T1,T3,T6	Yes	T1,T3,T6	OUTPUT
intr_sda_unstable_o	Yes	Yes	T1,T3,T6	Yes	T1,T3,T6	OUTPUT
intr_cmd_complete_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_tx_stretch_o	Yes	Yes	T5,T7,T10	Yes	T5,T7,T10	OUTPUT
intr_tx_threshold_o	Yes	Yes	T4,T7,T22	Yes	T1,T2,T3	OUTPUT
intr_acq_full_o	Yes	Yes	T39,T74,T75	Yes	T39,T74,T75	OUTPUT
intr_unexp_stop_o	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
intr_host_timeout_o	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : i2c

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	23	23	100.00	23	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	23	23	100.00	23	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	220118717	219995382	0	0
CioSclEnKnownO_A	220118717	219995382	0	0
CioSclKnownO_A	220118717	219995382	0	0
CioSdaEnKnownO_A	220118717	219995382	0	0
CioSdaKnownO_A	220118717	219995382	0	0
FpvSecCmRegWeOnehotCheck_A	220118717	70	0	0
IntrAcqFulllwKnownO_A	220118717	219995382	0	0
IntrAcqWtmkKnownO_A	220118717	219995382	0	0
IntrCommandCompleteKnownO_A	220118717	219995382	0	0
IntrFmtWtmkKnownO_A	220118717	219995382	0	0
IntrHostTimeoutKnownO_A	220118717	219995382	0	0
IntrNakKnownO_A	220118717	219995382	0	0
IntrRxOflwKnownO_A	220118717	219995382	0	0
IntrRxWtmkKnownO_A	220118717	219995382	0	0
IntrSclInterfKnownO_A	220118717	219995382	0	0
IntrSdaInterfKnownO_A	220118717	219995382	0	0
IntrSdaUnstableKnownO_A	220118717	219995382	0	0
IntrStretchTimeoutKnownO_A	220118717	219995382	0	0
IntrTxStretchKnownO_A	220118717	219995382	0	0
IntrTxWtmkKnownO_A	220118717	219995382	0	0
IntrUnexpStopKnownO_A	220118717	219995382	0	0
TlAReadyKnownO_A	220118717	219995382	0	0
TlDValidKnownO_A	220118717	219995382	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220118717	219995382	0	0
T1	125124	125035	0	0
T2	883956	883867	0	0
T3	25003	24943	0	0
T4	121015	120955	0	0
T5	32099	32022	0	0
T6	15274	15213	0	0
T7	54908	54810	0	0
T8	15704	15640	0	0
T9	1652	1569	0	0
T10	786050	785974	0	0

CioSclEnKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220118717	219995382	0	0
T1	125124	125035	0	0
T2	883956	883867	0	0
T3	25003	24943	0	0
T4	121015	120955	0	0
T5	32099	32022	0	0
T6	15274	15213	0	0
T7	54908	54810	0	0
T8	15704	15640	0	0
T9	1652	1569	0	0
T10	786050	785974	0	0

CioSclKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220118717	219995382	0	0
T1	125124	125035	0	0
T2	883956	883867	0	0
T3	25003	24943	0	0
T4	121015	120955	0	0
T5	32099	32022	0	0
T6	15274	15213	0	0
T7	54908	54810	0	0
T8	15704	15640	0	0
T9	1652	1569	0	0
T10	786050	785974	0	0

CioSdaEnKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220118717	219995382	0	0
T1	125124	125035	0	0
T2	883956	883867	0	0
T3	25003	24943	0	0
T4	121015	120955	0	0
T5	32099	32022	0	0
T6	15274	15213	0	0
T7	54908	54810	0	0
T8	15704	15640	0	0
T9	1652	1569	0	0
T10	786050	785974	0	0

CioSdaKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220118717	219995382	0	0
T1	125124	125035	0	0
T2	883956	883867	0	0
T3	25003	24943	0	0
T4	121015	120955	0	0
T5	32099	32022	0	0
T6	15274	15213	0	0
T7	54908	54810	0	0
T8	15704	15640	0	0
T9	1652	1569	0	0
T10	786050	785974	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220118717	70	0	0
T20	130665	0	0	0
T43	3224	0	0	0
T61	971847	0	0	0
T65	498637	0	0	0
T66	964348	0	0	0
T67	970731	0	0	0
T93	1366	0	0	0
T96	6199	20	0	0
T99	0	10	0	0
T100	0	10	0	0
T101	0	10	0	0
T102	0	20	0	0
T103	987	0	0	0
T104	101697	0	0	0

IntrAcqFulllwKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220118717	219995382	0	0
T1	125124	125035	0	0
T2	883956	883867	0	0
T3	25003	24943	0	0
T4	121015	120955	0	0
T5	32099	32022	0	0
T6	15274	15213	0	0
T7	54908	54810	0	0
T8	15704	15640	0	0
T9	1652	1569	0	0
T10	786050	785974	0	0

IntrAcqWtmkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220118717	219995382	0	0
T1	125124	125035	0	0
T2	883956	883867	0	0
T3	25003	24943	0	0
T4	121015	120955	0	0
T5	32099	32022	0	0
T6	15274	15213	0	0
T7	54908	54810	0	0
T8	15704	15640	0	0
T9	1652	1569	0	0
T10	786050	785974	0	0

IntrCommandCompleteKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220118717	219995382	0	0
T1	125124	125035	0	0
T2	883956	883867	0	0
T3	25003	24943	0	0
T4	121015	120955	0	0
T5	32099	32022	0	0
T6	15274	15213	0	0
T7	54908	54810	0	0
T8	15704	15640	0	0
T9	1652	1569	0	0
T10	786050	785974	0	0

IntrFmtWtmkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220118717	219995382	0	0
T1	125124	125035	0	0
T2	883956	883867	0	0
T3	25003	24943	0	0
T4	121015	120955	0	0
T5	32099	32022	0	0
T6	15274	15213	0	0
T7	54908	54810	0	0
T8	15704	15640	0	0
T9	1652	1569	0	0
T10	786050	785974	0	0

IntrHostTimeoutKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220118717	219995382	0	0
T1	125124	125035	0	0
T2	883956	883867	0	0
T3	25003	24943	0	0
T4	121015	120955	0	0
T5	32099	32022	0	0
T6	15274	15213	0	0
T7	54908	54810	0	0
T8	15704	15640	0	0
T9	1652	1569	0	0
T10	786050	785974	0	0

IntrNakKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220118717	219995382	0	0
T1	125124	125035	0	0
T2	883956	883867	0	0
T3	25003	24943	0	0
T4	121015	120955	0	0
T5	32099	32022	0	0
T6	15274	15213	0	0
T7	54908	54810	0	0
T8	15704	15640	0	0
T9	1652	1569	0	0
T10	786050	785974	0	0

IntrRxOflwKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220118717	219995382	0	0
T1	125124	125035	0	0
T2	883956	883867	0	0
T3	25003	24943	0	0
T4	121015	120955	0	0
T5	32099	32022	0	0
T6	15274	15213	0	0
T7	54908	54810	0	0
T8	15704	15640	0	0
T9	1652	1569	0	0
T10	786050	785974	0	0

IntrRxWtmkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220118717	219995382	0	0
T1	125124	125035	0	0
T2	883956	883867	0	0
T3	25003	24943	0	0
T4	121015	120955	0	0
T5	32099	32022	0	0
T6	15274	15213	0	0
T7	54908	54810	0	0
T8	15704	15640	0	0
T9	1652	1569	0	0
T10	786050	785974	0	0

IntrSclInterfKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220118717	219995382	0	0
T1	125124	125035	0	0
T2	883956	883867	0	0
T3	25003	24943	0	0
T4	121015	120955	0	0
T5	32099	32022	0	0
T6	15274	15213	0	0
T7	54908	54810	0	0
T8	15704	15640	0	0
T9	1652	1569	0	0
T10	786050	785974	0	0

IntrSdaInterfKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220118717	219995382	0	0
T1	125124	125035	0	0
T2	883956	883867	0	0
T3	25003	24943	0	0
T4	121015	120955	0	0
T5	32099	32022	0	0
T6	15274	15213	0	0
T7	54908	54810	0	0
T8	15704	15640	0	0
T9	1652	1569	0	0
T10	786050	785974	0	0

IntrSdaUnstableKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220118717	219995382	0	0
T1	125124	125035	0	0
T2	883956	883867	0	0
T3	25003	24943	0	0
T4	121015	120955	0	0
T5	32099	32022	0	0
T6	15274	15213	0	0
T7	54908	54810	0	0
T8	15704	15640	0	0
T9	1652	1569	0	0
T10	786050	785974	0	0

IntrStretchTimeoutKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220118717	219995382	0	0
T1	125124	125035	0	0
T2	883956	883867	0	0
T3	25003	24943	0	0
T4	121015	120955	0	0
T5	32099	32022	0	0
T6	15274	15213	0	0
T7	54908	54810	0	0
T8	15704	15640	0	0
T9	1652	1569	0	0
T10	786050	785974	0	0

IntrTxStretchKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220118717	219995382	0	0
T1	125124	125035	0	0
T2	883956	883867	0	0
T3	25003	24943	0	0
T4	121015	120955	0	0
T5	32099	32022	0	0
T6	15274	15213	0	0
T7	54908	54810	0	0
T8	15704	15640	0	0
T9	1652	1569	0	0
T10	786050	785974	0	0

IntrTxWtmkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220118717	219995382	0	0
T1	125124	125035	0	0
T2	883956	883867	0	0
T3	25003	24943	0	0
T4	121015	120955	0	0
T5	32099	32022	0	0
T6	15274	15213	0	0
T7	54908	54810	0	0
T8	15704	15640	0	0
T9	1652	1569	0	0
T10	786050	785974	0	0

IntrUnexpStopKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220118717	219995382	0	0
T1	125124	125035	0	0
T2	883956	883867	0	0
T3	25003	24943	0	0
T4	121015	120955	0	0
T5	32099	32022	0	0
T6	15274	15213	0	0
T7	54908	54810	0	0
T8	15704	15640	0	0
T9	1652	1569	0	0
T10	786050	785974	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220118717	219995382	0	0
T1	125124	125035	0	0
T2	883956	883867	0	0
T3	25003	24943	0	0
T4	121015	120955	0	0
T5	32099	32022	0	0
T6	15274	15213	0	0
T7	54908	54810	0	0
T8	15704	15640	0	0
T9	1652	1569	0	0
T10	786050	785974	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220118717	219995382	0	0
T1	125124	125035	0	0
T2	883956	883867	0	0
T3	25003	24943	0	0
T4	121015	120955	0	0
T5	32099	32022	0	0
T6	15274	15213	0	0
T7	54908	54810	0	0
T8	15704	15640	0	0
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