Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.72	100.00	100.00	94.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	220772187	7646	0	0
ctrl_rd_A	220772187	1553	0	0
host_fifo_config_rd_A	220772187	3118	0	0
host_timeout_ctrl_rd_A	220772187	968	0	0
intr_enable_rd_A	220772187	4687	0	0
ovrd_rd_A	220772187	2243	0	0
target_fifo_config_rd_A	220772187	1455	0	0
target_id_rd_A	220772187	1667	0	0
target_timeout_ctrl_rd_A	220772187	1302	0	0
timeout_ctrl_rd_A	220772187	1222	0	0
timing0_rd_A	220772187	1277	0	0
timing1_rd_A	220772187	1296	0	0
timing2_rd_A	220772187	1167	0	0
timing3_rd_A	220772187	1289	0	0
timing4_rd_A	220772187	1432	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220772187	7646	0	0
T72	2948	80	0	0
T97	7404	544	0	0
T98	4339	419	0	0
T105	3626	21	0	0
T106	6410	349	0	0
T107	7922	3	0	0
T108	5540	2	0	0
T109	5572	1	0	0
T114	13486	2	0	0
T117	6004	245	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220772187	1553	0	0
T71	5368	50	0	0
T105	3626	2	0	0
T114	13486	174	0	0
T120	7683	112	0	0
T128	2656	19	0	0
T131	2420	18	0	0
T144	4685	18	0	0
T150	3620	18	0	0
T152	1338	10	0	0
T153	2021	2	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220772187	3118	0	0
T13	118239	0	0	0
T44	3019	0	0	0
T57	157025	0	0	0
T78	250781	92	0	0
T84	152948	0	0	0
T90	73930	0	0	0
T154	0	88	0	0
T155	0	155	0	0
T156	0	121	0	0
T157	0	127	0	0
T158	0	117	0	0
T159	0	205	0	0
T160	0	183	0	0
T161	0	115	0	0
T162	0	103	0	0
T163	1953	0	0	0
T164	205495	0	0	0
T165	430590	0	0	0
T166	136558	0	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220772187	968	0	0
T71	5368	26	0	0
T105	3626	11	0	0
T114	13486	61	0	0
T120	7683	47	0	0
T128	2656	8	0	0
T131	2420	8	0	0
T133	1969	4	0	0
T144	4685	22	0	0
T150	3620	22	0	0
T152	1338	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220772187	4687	0	0
T71	5368	43	0	0
T105	3626	41	0	0
T114	13486	727	0	0
T120	7683	342	0	0
T144	4685	86	0	0
T167	1838	19	0	0
T168	1384	17	0	0
T169	2105	29	0	0
T170	1142	8	0	0
T171	1373	3	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220772187	2243	0	0
T13	118239	0	0	0
T44	3019	0	0	0
T84	152948	0	0	0
T90	73930	0	0	0
T163	1953	91	0	0
T164	205495	0	0	0
T165	430590	0	0	0
T166	136558	0	0	0
T172	0	55	0	0
T173	0	40	0	0
T174	0	55	0	0
T175	0	52	0	0
T176	0	19	0	0
T177	0	53	0	0
T178	0	79	0	0
T179	0	50	0	0
T180	0	29	0	0
T181	11152	0	0	0
T182	156529	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220772187	1455	0	0
T71	5368	23	0	0
T105	3626	24	0	0
T114	13486	143	0	0
T120	7683	65	0	0
T128	2656	34	0	0
T131	2420	11	0	0
T144	4685	76	0	0
T150	3620	26	0	0
T152	1338	10	0	0
T153	2021	5	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220772187	1667	0	0
T71	5368	32	0	0
T105	3626	23	0	0
T114	13486	197	0	0
T120	7683	92	0	0
T128	2656	42	0	0
T133	1969	18	0	0
T135	1497	16	0	0
T144	4685	53	0	0
T152	1338	6	0	0
T153	2021	6	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220772187	1302	0	0
T71	5368	37	0	0
T105	3626	15	0	0
T114	13486	114	0	0
T120	7683	73	0	0
T125	11709	29	0	0
T128	2656	25	0	0
T133	1969	21	0	0
T144	4685	24	0	0
T150	3620	23	0	0
T153	2021	3	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220772187	1222	0	0
T71	5368	15	0	0
T105	3626	20	0	0
T114	13486	80	0	0
T120	7683	53	0	0
T128	2656	14	0	0
T133	1969	12	0	0
T135	1497	2	0	0
T144	4685	81	0	0
T150	3620	21	0	0
T153	2021	3	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220772187	1277	0	0
T71	5368	22	0	0
T105	3626	3	0	0
T114	13486	95	0	0
T120	7683	45	0	0
T128	2656	16	0	0
T133	1969	11	0	0
T144	4685	37	0	0
T150	3620	7	0	0
T152	1338	3	0	0
T153	2021	22	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220772187	1296	0	0
T71	5368	19	0	0
T105	3626	21	0	0
T114	13486	138	0	0
T120	7683	60	0	0
T128	2656	35	0	0
T131	2420	5	0	0
T133	1969	3	0	0
T144	4685	61	0	0
T150	3620	19	0	0
T153	2021	9	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220772187	1167	0	0
T71	5368	7	0	0
T105	3626	13	0	0
T114	13486	94	0	0
T120	7683	61	0	0
T128	2656	11	0	0
T131	2420	7	0	0
T133	1969	17	0	0
T135	1497	1	0	0
T144	4685	23	0	0
T153	2021	6	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220772187	1289	0	0
T71	5368	59	0	0
T105	3626	7	0	0
T114	13486	127	0	0
T120	7683	66	0	0
T128	2656	15	0	0
T131	2420	4	0	0
T144	4685	43	0	0
T150	3620	19	0	0
T152	1338	5	0	0
T153	2021	1	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220772187	1432	0	0
T71	5368	87	0	0
T105	3626	22	0	0
T114	13486	130	0	0
T120	7683	70	0	0
T128	2656	24	0	0
T131	2420	3	0	0
T133	1969	10	0	0
T144	4685	46	0	0
T150	3620	22	0	0
T153	2021	8	0	0