Unified Coverage Report :: Module :: i2c_fsm

Module : i2c_fsm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.82	90.57	82.12		42.58	83.83	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core.u_i2c_fsm	79.82	90.57	82.12		42.58	83.83	100.00

---

Module Instance : tb.dut.i2c_core.u_i2c_fsm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.82	90.57	82.12		42.58	83.83	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.82	90.57	82.12		42.58	83.83	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.36	96.81	69.74			90.91	100.00	i2c_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c_fsm

	Line No.	Total	Covered	Percent
TOTAL		647	586	90.57
ALWAYS	175	17	17	100.00
ALWAYS	198	3	3	100.00
ALWAYS	211	9	9	100.00
ALWAYS	229	5	4	80.00
CONT_ASSIGN	251	1	1	100.00
ALWAYS	255	6	6	100.00
ALWAYS	270	6	5	83.33
ALWAYS	281	7	7	100.00
ALWAYS	294	6	6	100.00
ALWAYS	305	5	5	100.00
ALWAYS	312	7	7	100.00
ALWAYS	325	5	5	100.00
ALWAYS	339	8	7	87.50
ALWAYS	351	8	7	87.50
ALWAYS	375	6	6	100.00
ALWAYS	385	6	6	100.00
ALWAYS	395	6	6	100.00
CONT_ASSIGN	405	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
ALWAYS	417	9	9	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	434	1	1	100.00
ALWAYS	438	7	7	100.00
ALWAYS	449	5	5	100.00
CONT_ASSIGN	466	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	470	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
ALWAYS	535	6	6	100.00
CONT_ASSIGN	553	1	1	100.00
ALWAYS	558	4	4	100.00
CONT_ASSIGN	575	1	1	100.00
CONT_ASSIGN	579	1	1	100.00
ALWAYS	583	199	169	84.92
CONT_ASSIGN	987	1	1	100.00
CONT_ASSIGN	988	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	1001	1	1	100.00
CONT_ASSIGN	1006	1	1	100.00
ALWAYS	1010	272	245	90.07
CONT_ASSIGN	1592	1	1	100.00
ALWAYS	1596	3	3	100.00
ALWAYS	1605	5	5	100.00
CONT_ASSIGN	1614	1	1	100.00
CONT_ASSIGN	1615	1	1	100.00
CONT_ASSIGN	1618	1	1	100.00
CONT_ASSIGN	1621	1	1	100.00
CONT_ASSIGN	1625	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
187	1	1
188	1	1
189	1	1
192	1	1
193	1	1
			MISSING_ELSE
198	1	1
199	1	1
201	1	1
211	1	1
212	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
222	1	1
229	1	1
230	1	1
231	1	1
232	0	1
234	1	1
251	1	1
255	1	1
256	1	1
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
270	1	1
271	1	1
272	1	1
273	0	1
274	1	1
275	1	1
			MISSING_ELSE
281	1	1
282	1	1
283	1	1
284	1	1
285	1	1
286	1	1
288	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
299	1	1
			MISSING_ELSE
305	2	2
306	2	2
307	1	1
312	1	1
313	1	1
314	1	1
315	1	1
316	1	1
317	1	1
319	1	1
325	1	1
326	1	1
327	1	1
329	1	1
330	1	1
339	1	1
340	1	1
341	1	1
342	0	1
343	1	1
344	1	1
345	1	1
346	1	1
			MISSING_ELSE
351	1	1
352	1	1
353	1	1
354	0	1
355	1	1
356	1	1
357	1	1
358	1	1
			MISSING_ELSE
375	1	1
376	1	1
377	1	1
378	1	1
379	1	1
380	1	1
			MISSING_ELSE
385	1	1
386	1	1
387	1	1
388	1	1
389	1	1
390	1	1
			MISSING_ELSE
395	1	1
396	1	1
397	1	1
398	1	1
399	1	1
400	1	1
			MISSING_ELSE
405	1	1
406	1	1
409	1	1
410	1	1
413	1	1
417	1	1
418	1	1
419	1	1
420	1	1
421	1	1
424	2	2
425	1	1
427	1	1
432	1	1
433	1	1
434	1	1
438	1	1
439	1	1
440	1	1
441	1	1
442	1	1
443	2	2
			MISSING_ELSE
			MISSING_ELSE
449	1	1
450	1	1
451	1	1
452	2	2
			MISSING_ELSE
			MISSING_ELSE
466	1	1
469	1	1
470	1	1
530	1	1
535	1	1
536	1	1
537	1	1
541	1	1
542	1	1
543	1	1
			MISSING_ELSE
553	1	1
558	1	1
559	1	1
560	1	1
561	1	1
			MISSING_ELSE
575	1	1
579	1	1
583	1	1
584	1	1
585	1	1
586	1	1
587	1	1
588	1	1
589	1	1
590	1	1
591	1	1
592	1	1
593	1	1
594	1	1
595	1	1
596	1	1
597	1	1
598	1	1
599	1	1
600	1	1
601	1	1
602	1	1
607	1	1
608	1	1
609	0	1
610	0	1
612	1	1
613	1	1
623	1	1
624	1	1
625	1	1
626	2	2
			MISSING_ELSE
630	1	1
631	1	1
632	1	1
636	1	1
637	1	1
638	1	1
641	1	1
642	1	1
643	1	1
645	1	1
647	1	1
651	1	1
652	1	1
653	1	1
654	1	1
655	1	2
			MISSING_ELSE
656	2	2
			MISSING_ELSE
660	1	1
661	1	1
662	1	1
666	1	1
667	1	1
668	1	1
672	1	1
673	1	1
674	1	1
675	2	2
			MISSING_ELSE
676	1	1
677	1	2
			MISSING_ELSE
678	2	2
			MISSING_ELSE
682	1	1
683	1	1
684	1	1
688	1	1
689	1	1
690	1	1
694	1	1
695	1	1
696	1	1
697	1	2
			MISSING_ELSE
698	2	2
			MISSING_ELSE
702	1	1
703	1	1
704	1	1
705	1	1
706	1	1
			MISSING_ELSE
711	1	1
712	1	1
716	2	2
717	2	2
718	1	1
722	1	1
723	2	2
724	2	2
725	1	1
726	1	1
727	1	1
728	1	2
			MISSING_ELSE
729	2	2
			MISSING_ELSE
733	1	1
734	2	2
735	2	2
736	1	1
737	1	1
741	1	1
742	1	1
743	1	1
747	1	1
748	1	1
749	1	1
753	1	1
754	1	1
755	1	1
756	1	1
760	1	1
766	1	1
770	1	1
771	2	2
772	1	1
773	1	1
782	1	1
786	1	1
787	1	1
791	1	1
795	1	1
796	1	1
800	1	1
801	1	1
805	1	1
806	1	1
809	1	1
810	1	1
814	0	1
815	0	1
818	1	1
819	1	1
			==> MISSING_ELSE
825	1	1
829	1	1
830	1	1
834	1	1
837	1	1
841	1	1
844	1	1
848	1	1
851	1	1
852	1	1
854	1	1
			MISSING_ELSE
859	1	1
860	1	1
861	1	1
865	1	1
869	1	1
873	1	1
874	1	1
878	1	1
879	1	1
883	1	1
884	1	1
886	1	1
887	1	1
888	1	1
			==> MISSING_ELSE
893	0	1
897	0	1
898	0	1
902	0	1
903	0	1
907	0	1
908	0	1
910	0	1
916	0	1
917	0	1
921	0	1
922	0	1
			==> MISSING_ELSE
928	0	1
929	0	1
931	0	1
932	0	1
933	0	1
937	1	1
938	1	1
942	1	1
943	1	1
944	1	1
948	0	1
949	0	1
952	0	1
953	0	1
954	0	1
978	1	1
980	1	1
981	1	1
983	1	1
			MISSING_ELSE
987	1	1
988	1	1
992	1	1
1001	1	1
1006	1	1
1010	1	1
1011	1	1
1012	1	1
1013	1	1
1014	1	1
1015	1	1
1016	1	1
1017	1	1
1018	1	1
1019	1	1
1020	1	1
1021	1	1
1022	1	1
1023	1	1
1024	1	1
1025	1	1
1026	1	1
1028	1	1
1031	2	2
1032	1	1
1033	2	2
			MISSING_ELSE
			MISSING_ELSE
1035	1	1
1044	1	1
1045	1	1
1046	1	1
1047	1	1
1048	1	1
			MISSING_ELSE
1053	1	1
1054	1	1
1055	1	1
1056	1	1
			MISSING_ELSE
1061	1	1
1062	1	1
1063	1	1
1064	1	1
			MISSING_ELSE
1069	1	1
1070	1	1
1071	1	1
1072	1	1
1073	1	1
1074	1	1
1076	1	1
1077	1	1
			MISSING_ELSE
1083	1	1
1084	1	1
1086	1	1
1087	1	1
1088	1	1
1089	1	1
1090	1	1
1091	1	1
			MISSING_ELSE
1096	1	1
1097	1	1
1098	1	1
1099	1	1
1100	1	1
1101	1	1
1102	1	1
1103	1	1
1105	1	1
1106	1	1
			MISSING_ELSE
1113	1	1
1114	1	1
1115	1	1
1116	1	1
			MISSING_ELSE
1121	1	1
1123	1	1
1124	1	1
1125	1	1
1126	1	1
1127	1	1
1128	1	1
			MISSING_ELSE
1133	1	1
1134	1	1
1135	1	1
1136	1	1
1137	1	1
1139	1	1
1140	1	1
1141	1	1
			MISSING_ELSE
1147	1	1
1148	1	1
1149	1	1
1150	1	1
			MISSING_ELSE
1155	1	1
1157	1	1
1158	1	1
1159	1	1
1160	1	1
1161	1	1
1162	1	1
1163	1	1
			MISSING_ELSE
1168	1	1
1169	1	1
1170	1	1
1171	1	1
1172	1	1
1173	1	1
1174	1	1
1176	1	1
1177	1	1
			MISSING_ELSE
1184	1	1
1185	1	1
1186	1	1
1187	1	1
1188	1	1
			MISSING_ELSE
1193	1	1
1194	1	1
1196	1	1
1197	1	1
1198	1	1
1199	1	1
1200	1	1
1201	1	1
			MISSING_ELSE
1206	1	1
1207	1	1
1208	1	1
1209	1	1
1210	1	1
1211	1	1
1212	1	1
1213	1	1
1215	1	1
1216	1	1
1217	1	1
1220	1	1
1221	1	1
1222	1	1
1223	1	1
			MISSING_ELSE
1229	1	1
1230	1	1
1231	1	1
1232	1	1
			MISSING_ELSE
1237	1	1
1238	1	1
1239	1	1
1240	1	1
1241	1	1
			MISSING_ELSE
1246	1	1
1247	1	1
1248	1	1
1249	1	1
1250	0	1
1251	0	1
1252	0	1
1254	1	1
1255	1	1
1256	1	1
			MISSING_ELSE
1262	1	1
1263	1	1
1264	1	1
1265	1	1
1266	1	1
1267	1	1
1268	1	1
1269	1	1
1270	1	1
1272	1	1
1273	1	1
1274	1	1
1275	1	1
1280	1	1
1281	0	1
1282	0	1
1283	0	1
1284	1	1
1285	1	1
1286	1	1
1287	1	1
1289	1	1
1290	1	1
1291	1	1
1302	1	1
1304	1	1
1305	1	1
			MISSING_ELSE
1307	1	1
1311	1	1
1312	1	1
1313	1	1
1318	0	1
1319	0	1
1321	0	1
1322	0	1
1325	1	1
1327	1	1
1328	1	1
1331	1	1
			MISSING_ELSE
1337	1	1
1338	1	1
			==> MISSING_ELSE
1343	2	2
			MISSING_ELSE
1347	1	1
1348	1	1
1349	1	1
1350	1	1
			MISSING_ELSE
1355	1	1
1361	1	1
1362	0	1
1363	1	1
1364	1	1
1365	1	1
1366	1	1
			==> MISSING_ELSE
			==> MISSING_ELSE
1372	1	1
1373	1	1
1375	1	1
1376	1	1
1377	1	1
1382	2	2
			MISSING_ELSE
1386	1	1
1387	1	1
1388	1	1
1389	1	1
			MISSING_ELSE
1394	1	1
1395	1	1
1396	1	1
1398	1	1
1399	1	1
1400	1	1
			==> MISSING_ELSE
1406	1	1
1407	1	1
			MISSING_ELSE
1413	1	1
1415	1	1
1416	1	1
1419	1	1
			MISSING_ELSE
1427	1	1
1431	1	1
1438	1	1
1439	0	1
1441	1	1
1443	1	1
1444	1	1
			MISSING_ELSE
1449	1	1
1450	1	1
			==> MISSING_ELSE
1455	2	2
			MISSING_ELSE
1459	1	1
1460	1	1
1461	1	1
1462	1	1
			MISSING_ELSE
1467	1	1
1470	1	1
			==> MISSING_ELSE
1475	0	1
1476	0	1
			==> MISSING_ELSE
1481	0	1
1482	0	1
			==> MISSING_ELSE
1487	0	1
1488	0	1
1489	0	1
1490	0	1
			==> MISSING_ELSE
1495	0	1
1497	0	1
			==> MISSING_ELSE
1507	0	1
1513	0	1
			==> MISSING_ELSE
1519	1	1
1520	1	1
1527	1	1
1528	1	1
1529	1	1
1532	1	1
			MISSING_ELSE
1537	1	1
1538	1	1
			MISSING_ELSE
1547	0	1
1548	0	1
			==> MISSING_ELSE
1572	1	1
1581	0	1
1582	1	1
1583	1	1
1584	1	1
1585	1	1
			MISSING_ELSE
1592	1	1
1596	1	1
1597	1	1
1599	1	1
1605	1	1
1606	1	1
1607	1	1
1609	1	1
1610	1	1
1614	1	1
1615	1	1
1618	1	1
1621	1	1
1625	1	1

---

Cond Coverage for Module : i2c_fsm

	Total	Covered	Percent
Conditions	302	248	82.12
Logical	302	248	82.12
Non-Logical	0	0
Event	0	0

 LINE       192
 EXPRESSION (host_enable_i || target_enable_i)
             ------1------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T2,T6,T7

 LINE       216
 EXPRESSION (((!target_idle_o)) && event_host_timeout_o)
             ---------1--------    ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T5
1	1	Covered	T8,T9,T10

 LINE       219
 EXPRESSION (((!target_idle_o)) && scl_i)
             ---------1--------    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       258
 EXPRESSION (stretch_idle_cnt == stretch_cnt_threshold)
            ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       306
 EXPRESSION (fmt_byte_i == '0)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T11,T12
1	Covered	T13,T14,T15

 LINE       341
 EXPRESSION (trans_started && ((!host_enable_i)))
             ------1------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T7
1	1	Not Covered

 LINE       353
 EXPRESSION (pend_restart && ((!host_enable_i)))
             ------1-----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T16,T17
1	1	Not Covered

 LINE       377
 EXPRESSION (start_det_trigger || stop_det_trigger)
             --------1--------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       379
 EXPRESSION (start_det_pending || stop_det_pending)
             --------1--------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       389
 EXPRESSION (((!target_enable_i)) || ((!scl_i)) || start_det || stop_det_trigger)
             ----------1---------    -----2----    ----3----    --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T3,T4,T5
0	0	0	1	Covered	T3,T4,T5
0	0	1	0	Covered	T3,T4,T5
0	1	0	0	Covered	T3,T4,T5
1	0	0	0	Covered	T1,T2,T3

 LINE       399
 EXPRESSION (((!target_enable_i)) || ((!scl_i)) || stop_det || start_det_trigger)
             ----------1---------    -----2----    ----3---    --------4--------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T3,T4,T5
0	0	0	1	Covered	T3,T4,T5
0	0	1	0	Covered	T3,T4,T5
0	1	0	0	Covered	T3,T4,T5
1	0	0	0	Covered	T1,T2,T3

 LINE       405
 EXPRESSION (target_enable_i && ((scl_i_q && scl_i) & (sda_i_q && ((!sda_i)))))
             -------1-------    -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       405
 SUB-EXPRESSION ((scl_i_q && scl_i) & (sda_i_q && ((!sda_i))))
                 ---------1--------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       405
 SUB-EXPRESSION (scl_i_q && scl_i)
                 ---1---    --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       405
 SUB-EXPRESSION (sda_i_q && ((!sda_i)))
                 ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       406
 EXPRESSION (target_enable_i && start_det_pending && (ctrl_det_count >= thd_dat_i))
             -------1-------    --------2--------    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T5

 LINE       409
 EXPRESSION (target_enable_i && ((scl_i_q && scl_i) & (((!sda_i_q)) && sda_i)))
             -------1-------    -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       409
 SUB-EXPRESSION ((scl_i_q && scl_i) & (((!sda_i_q)) && sda_i))
                 ---------1--------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       409
 SUB-EXPRESSION (scl_i_q && scl_i)
                 ---1---    --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       409
 SUB-EXPRESSION (((!sda_i_q)) && sda_i)
                 ------1-----    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T2,T3,T6

 LINE       410
 EXPRESSION (target_enable_i && stop_det_pending && (ctrl_det_count >= thd_dat_i))
             -------1-------    --------2-------    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T5

 LINE       413
 EXPRESSION (bit_idx == 4'd8)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       421
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       424
 EXPRESSION (input_byte_clr || bit_ack)
             -------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T2,T3,T6
1	0	Covered	T3,T4,T5

 LINE       432
 EXPRESSION ((input_byte[7:1] & target_mask0_i) == target_address0_i)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       433
 EXPRESSION ((input_byte[7:1] & target_mask1_i) == target_address1_i)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       434
 EXPRESSION (address0_match || address1_match)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       442
 EXPRESSION (((!scl_i_q)) && scl_i)
             ------1-----    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T2,T3,T6

 LINE       451
 EXPRESSION (((!scl_i_q)) && scl_i)
             ------1-----    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T2,T3,T6

 LINE       537
 EXPRESSION (((!en_sda_interf_det)) && ((|sda_rise_cnt)))
             -----------1----------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T6,T7

 LINE       542
 EXPRESSION (en_sda_interf_det && (sda_rise_cnt < sda_rise_latency))
             --------1--------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       553
 EXPRESSION ((host_idle_o & host_enable_i & ((!sda_i))) | ((sda_rise_cnt == sda_rise_latency) & sda_o & ((!sda_i))))
             ---------------------1--------------------   ----------------------------2----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T18,T11
1	0	Covered	T2,T19,T20

 LINE       553
 SUB-EXPRESSION (host_idle_o & host_enable_i & ((!sda_i)))
                 -----1-----   ------2------   -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T6,T7
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T2,T6,T7
1	1	1	Covered	T2,T19,T20

 LINE       553
 SUB-EXPRESSION ((sda_rise_cnt == sda_rise_latency) & sda_o & ((!sda_i)))
                 -----------------1----------------   --2--   -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T6
1	0	1	Covered	T2,T6,T7
1	1	0	Covered	T2,T6,T7
1	1	1	Covered	T6,T18,T11

 LINE       553
 SUB-EXPRESSION (sda_rise_cnt == sda_rise_latency)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T7

 LINE       560
 EXPRESSION (bit_ack && address_match)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T2,T3,T6

 LINE       579
 EXPRESSION (((!target_idle)) & rw_bit_q & stop_det & ((!expect_stop)))
             --------1-------   ----2---   ----3---   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T21,T22,T23
1	0	1	1	Covered	T5,T21,T8
1	1	0	1	Covered	T3,T4,T5
1	1	1	0	Covered	T3,T4,T5
1	1	1	1	Covered	T24,T25,T26

 LINE       608
 EXPRESSION (host_enable_i && trans_started)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T6,T7
1	1	Not Covered

 LINE       655
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T2,T6,T7
1	1	Not Covered

 LINE       656
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T6,T7
1	Covered	T6,T18,T27

 LINE       675
 EXPRESSION (((!scl_i_q)) && scl_i && sda_i && ((!fmt_flag_nak_ok_i)))
             ------1-----    --2--    --3--    -----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T28,T29
1	0	1	1	Covered	T2,T7,T18
1	1	0	1	Covered	T2,T7,T11
1	1	1	0	Covered	T30,T31,T32
1	1	1	1	Covered	T18,T28,T29

 LINE       677
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T2,T7,T11
1	1	Not Covered

 LINE       678
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T6,T7
1	Covered	T2,T6,T7

 LINE       697
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T11,T12
1	0	Covered	T2,T11,T12
1	1	Not Covered

 LINE       698
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T11,T12
1	Covered	T11,T12,T33

 LINE       704
 EXPRESSION ((bit_index == '0) && (tcount_q == 20'b1))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T11,T12
1	0	Covered	T2,T11,T12
1	1	Covered	T2,T11,T12

 LINE       704
 SUB-EXPRESSION (bit_index == '0)
                --------1--------

-1-	Status	Tests
0	Covered	T2,T11,T12
1	Covered	T2,T11,T12

 LINE       704
 SUB-EXPRESSION (tcount_q == 20'b1)
                ---------1---------

-1-	Status	Tests
0	Covered	T2,T11,T12
1	Covered	T2,T11,T12

 LINE       717
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T11,T12
1	Covered	T2,T11,T12

 LINE       724
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T11,T12
1	Covered	T2,T11,T12

 LINE       728
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T11,T12
1	0	Covered	T2,T11,T12
1	1	Not Covered

 LINE       729
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T11,T12
1	Covered	T34,T35,T36

 LINE       735
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T11,T12
1	Covered	T2,T11,T12

 LINE       766
 EXPRESSION (fmt_flag_start_before_i && ((!trans_started)))
             -----------1-----------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T37,T38,T39
1	0	Covered	T2,T16,T17
1	1	Covered	T2,T6,T7

 LINE       809
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T3,T4,T5

 LINE       886
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T5,T21,T8

 LINE       910
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       931
 EXPRESSION (((!stretch_addr)) || nack_timeout)
             --------1--------    ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       978
 EXPRESSION (start_det || stop_det)
             ----1----    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       981
 EXPRESSION (start_det ? ({AcqRestart, input_byte}) : ({AcqStop, input_byte}))
             ----1----

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       992
 EXPRESSION (nack_timeout_en_i && (stretch_active_cnt >= nack_timeout_i))
             --------1--------    -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       1001
 EXPRESSION (((~tx_fifo_rvalid_i)) | (acq_fifo_depth_i > 9'(1'b1)))
             ----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T5,T21,T8
1	0	Covered	T1,T2,T3

 LINE       1031
 EXPRESSION (((!host_enable_i)) && ((!target_enable_i)))
             ---------1--------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       1044
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T6,T7
1	Covered	T2,T6,T7

 LINE       1053
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T6,T7
1	Covered	T2,T6,T7

 LINE       1061
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T15,T40,T41
1	Covered	T2,T6,T7

 LINE       1070
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T6,T7
1	Covered	T2,T6,T7

 LINE       1084
 EXPRESSION (((!scl_i)) && stretch_predict_cnt_expired)
             -----1----    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T2,T6,T7
1	1	Covered	T42,T43,T44

 LINE       1088
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T6,T7
1	Covered	T2,T6,T7

 LINE       1097
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T6,T7
1	Covered	T2,T6,T7

 LINE       1101
 EXPRESSION (bit_index == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T2,T6,T7
1	Covered	T2,T6,T7

 LINE       1113
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T6,T7
1	Covered	T2,T6,T7

 LINE       1121
 EXPRESSION (((!scl_i)) && stretch_predict_cnt_expired)
             -----1----    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T18
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       1125
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T6,T7
1	Covered	T2,T7,T11

 LINE       1133
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T7,T11
1	Covered	T2,T7,T11

 LINE       1147
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T11,T12
1	Covered	T2,T11,T12

 LINE       1155
 EXPRESSION (((!scl_i)) && stretch_predict_cnt_expired)
             -----1----    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T11,T12
1	0	Covered	T2,T11,T12
1	1	Covered	T43,T44,T45

 LINE       1159
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T11,T12
1	Covered	T2,T11,T12

 LINE       1168
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T11,T12
1	Covered	T2,T11,T12

 LINE       1171
 EXPRESSION (bit_index == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T2,T11,T12
1	Covered	T2,T11,T12

 LINE       1185
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T11,T12
1	Covered	T2,T11,T12

 LINE       1194
 EXPRESSION (((!scl_i)) && stretch_predict_cnt_expired)
             -----1----    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T11,T12
1	0	Covered	T2,T11,T12
1	1	Covered	T43,T44,T45

 LINE       1198
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T11,T12
1	Covered	T2,T11,T12

 LINE       1207
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T11,T12
1	Covered	T2,T11,T12

 LINE       1209
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T11,T12
1	Covered	T2,T11,T12

 LINE       1229
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T7,T11
1	Covered	T2,T7,T11

 LINE       1237
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T7,T11
1	Covered	T2,T7,T11

 LINE       1247
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T7,T11,T12
1	Covered	T2,T7,T11

 LINE       1267
 EXPRESSION (fmt_flag_start_before_i && ((!trans_started)))
             -----------1-----------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T37,T38,T39
1	0	Covered	T2,T16,T17
1	1	Covered	T2,T6,T7

 LINE       1284
 EXPRESSION (fmt_fifo_depth_i == 7'b1)
            -------------1------------

-1-	Status	Tests
0	Covered	T2,T7,T11
1	Covered	T2,T7,T11

 LINE       1302
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       1337
 EXPRESSION ((tcount_q == 20'b1) && ((!scl_i)))
             ---------1---------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T3,T4,T5

 LINE       1337
 SUB-EXPRESSION (tcount_q == 20'b1)
                ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T3,T4,T5

 LINE       1355
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T3,T4,T5

 LINE       1361
 EXPRESSION (stretch_addr && ((!nack_next_byte_q)))
             ------1-----    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Not Covered
1	1	Not Covered

 LINE       1394
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T3,T4,T5

 LINE       1438
 EXPRESSION (acq_fifo_full_or_last_space || nack_next_byte_q)
             -------------1-------------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T5,T21,T8
0	1	Not Covered
1	0	Not Covered

 LINE       1449
 EXPRESSION ((tcount_q == 20'b1) && ((!scl_i)))
             ---------1---------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T5,T21,T8

 LINE       1449
 SUB-EXPRESSION (tcount_q == 20'b1)
                ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T5,T21,T8

 LINE       1467
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T5,T21,T8

 LINE       1470
 EXPRESSION (stretch_rx ? StretchAcqFull : AcquireByte)
             -----1----

-1-	Status	Tests
0	Covered	T5,T21,T8
1	Not Covered

 LINE       1475
 EXPRESSION ((tcount_q == 20'b1) && ((!scl_i)))
             ---------1---------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1475
 SUB-EXPRESSION (tcount_q == 20'b1)
                ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       1495
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       1507
 EXPRESSION (((!stretch_addr)) || nack_timeout)
             --------1--------    ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       1513
 EXPRESSION (rw_bit_q ? StretchTx : AcquireByte)
             ----1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       1537
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       1547
 EXPRESSION (((~stretch_rx)) || nack_timeout)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       1572
 EXPRESSION (((!target_idle)) && ((!target_enable_i)))
             --------1-------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Not Covered

 LINE       1592
 EXPRESSION (target_enable_i && ((!target_idle)) && (stop_det | start_det))
             -------1-------    --------2-------    -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T3,T4,T5
1	1	1	Covered	T3,T4,T5

 LINE       1592
 SUB-EXPRESSION (stop_det | start_det)
                 ----1---   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       1618
 EXPRESSION (((!target_idle_o)) & (stretch_idle_cnt > host_timeout_i))
             ---------1--------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T3,T4,T5
1	1	Covered	T8,T9,T10

 LINE       1621
 EXPRESSION (stretch_en && (stretch_idle_cnt[30:0] > stretch_timeout_i) && timeout_enable_i)
             -----1----    ----------------------2---------------------    --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T6,T7
1	0	1	Covered	T6,T7,T18
1	1	0	Covered	T2,T18,T11
1	1	1	Covered	T6,T7,T18

---

FSM Coverage for Module : i2c_fsm

Summary for FSM :: state_q

	Total	Covered	Percent
States	47	41	87.23	(Not included in score)
Transitions	155	66	42.58
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AcquireAckHold	1460	Covered	T5,T21,T8
AcquireAckPulse	1455	Covered	T5,T21,T8
AcquireAckSetup	1450	Covered	T5,T21,T8
AcquireAckWait	1441	Covered	T5,T21,T8
AcquireByte	1366	Covered	T5,T21,T8
AcquireStart	1583	Covered	T3,T4,T5
Active	1033	Covered	T2,T6,T7
AddrAckHold	1348	Covered	T3,T4,T5
AddrAckPulse	1343	Covered	T3,T4,T5
AddrAckSetup	1338	Covered	T3,T4,T5
AddrAckWait	1321	Covered	T3,T4,T5
AddrRead	1304	Covered	T3,T4,T5
ClockLow	1062	Covered	T2,T6,T7
ClockLowAck	1102	Covered	T2,T6,T7
ClockPulse	1076	Covered	T2,T6,T7
ClockPulseAck	1114	Covered	T2,T6,T7
ClockStart	1054	Covered	T2,T6,T7
ClockStop	1135	Covered	T2,T7,T11
HoldBit	1089	Covered	T2,T6,T7
HoldDevAck	1126	Covered	T2,T7,T11
HoldStart	1045	Covered	T2,T6,T7
HoldStop	1238	Covered	T2,T7,T11
HostClockLowAck	1172	Covered	T2,T11,T12
HostClockPulseAck	1186	Covered	T2,T11,T12
HostHoldBitAck	1199	Covered	T2,T11,T12
Idle	1031	Covered	T1,T2,T3
NackHold	1488	Not Covered
NackPulse	1482	Not Covered
NackSetup	1476	Not Covered
NackWait	1319	Not Covered
PopFmtFifo	1139	Covered	T2,T7,T11
ReadClockLow	1176	Covered	T2,T11,T12
ReadClockPulse	1148	Covered	T2,T11,T12
ReadHoldBit	1160	Covered	T2,T11,T12
SetupStart	1073	Covered	T2,T6,T7
SetupStop	1230	Covered	T2,T7,T11
StretchAcqFull	1470	Not Covered
StretchAddr	1362	Not Covered
StretchTx	1373	Covered	T3,T4,T5
StretchTxSetup	1527	Covered	T3,T4,T5
TransmitAck	1396	Covered	T3,T4,T5
TransmitAckPulse	1407	Covered	T3,T4,T5
TransmitHold	1387	Covered	T3,T4,T5
TransmitPulse	1382	Covered	T3,T4,T5
TransmitSetup	1375	Covered	T3,T4,T5
TransmitWait	1364	Covered	T3,T4,T5
WaitForStop	1419	Covered	T3,T4,T5

transitions	Line No.	Covered	Tests
AcquireAckHold->AcquireByte	1470	Covered	T5,T21,T8
AcquireAckHold->AcquireStart	1583	Not Covered
AcquireAckHold->Idle	1581	Not Covered
AcquireAckHold->StretchAcqFull	1470	Not Covered
AcquireAckPulse->AcquireAckHold	1460	Covered	T5,T21,T8
AcquireAckPulse->AcquireStart	1583	Not Covered
AcquireAckPulse->Idle	1581	Not Covered
AcquireAckSetup->AcquireAckPulse	1455	Covered	T5,T21,T8
AcquireAckSetup->AcquireStart	1583	Not Covered
AcquireAckSetup->Idle	1581	Not Covered
AcquireAckWait->AcquireAckSetup	1450	Covered	T5,T21,T8
AcquireAckWait->AcquireStart	1583	Not Covered
AcquireAckWait->Idle	1581	Not Covered
AcquireByte->AcquireAckWait	1441	Covered	T5,T21,T8
AcquireByte->AcquireStart	1583	Covered	T5,T21,T8
AcquireByte->Idle	1581	Covered	T5,T21,T8
AcquireByte->NackWait	1439	Not Covered
AcquireStart->AddrRead	1304	Covered	T3,T4,T5
AcquireStart->Idle	1581	Not Covered
Active->AcquireStart	1583	Not Covered
Active->ClockLow	1272	Covered	T2,T7,T11
Active->Idle	1581	Not Covered
Active->ReadClockLow	1264	Covered	T2,T11,T12
Active->SetupStart	1268	Covered	T2,T6,T7
AddrAckHold->AcquireByte	1366	Covered	T5,T21,T8
AddrAckHold->AcquireStart	1583	Not Covered
AddrAckHold->Idle	1581	Not Covered
AddrAckHold->StretchAddr	1362	Not Covered
AddrAckHold->TransmitWait	1364	Covered	T3,T4,T5
AddrAckPulse->AcquireStart	1583	Not Covered
AddrAckPulse->AddrAckHold	1348	Covered	T3,T4,T5
AddrAckPulse->Idle	1581	Not Covered
AddrAckSetup->AcquireStart	1583	Not Covered
AddrAckSetup->AddrAckPulse	1343	Covered	T3,T4,T5
AddrAckSetup->Idle	1581	Not Covered
AddrAckWait->AcquireStart	1583	Not Covered
AddrAckWait->AddrAckSetup	1338	Covered	T3,T4,T5
AddrAckWait->Idle	1581	Not Covered
AddrRead->AcquireStart	1583	Covered	T46,T47,T48
AddrRead->AddrAckWait	1321	Covered	T3,T4,T5
AddrRead->Idle	1331	Covered	T21,T22,T26
AddrRead->NackWait	1319	Not Covered
ClockLow->AcquireStart	1583	Not Covered
ClockLow->ClockPulse	1076	Covered	T2,T6,T7
ClockLow->Idle	1581	Covered	T6,T18,T49
ClockLow->SetupStart	1073	Covered	T2,T16,T17
ClockLowAck->AcquireStart	1583	Not Covered
ClockLowAck->ClockPulseAck	1114	Covered	T2,T6,T7
ClockLowAck->Idle	1581	Not Covered
ClockPulse->AcquireStart	1583	Not Covered
ClockPulse->HoldBit	1089	Covered	T2,T6,T7
ClockPulse->Idle	1581	Covered	T18,T27,T50
ClockPulseAck->AcquireStart	1583	Not Covered
ClockPulseAck->HoldDevAck	1126	Covered	T2,T7,T11
ClockPulseAck->Idle	1581	Covered	T6,T18,T27
ClockStart->AcquireStart	1583	Not Covered
ClockStart->ClockLow	1062	Covered	T2,T6,T7
ClockStart->Idle	1581	Not Covered
ClockStop->AcquireStart	1583	Not Covered
ClockStop->Idle	1581	Not Covered
ClockStop->SetupStop	1230	Covered	T2,T7,T11
HoldBit->AcquireStart	1583	Not Covered
HoldBit->ClockLow	1105	Covered	T2,T6,T7
HoldBit->ClockLowAck	1102	Covered	T2,T6,T7
HoldBit->Idle	1581	Covered	T6,T18,T50
HoldDevAck->AcquireStart	1583	Not Covered
HoldDevAck->ClockStop	1135	Covered	T7,T11,T12
HoldDevAck->Idle	1581	Not Covered
HoldDevAck->PopFmtFifo	1139	Covered	T2,T7,T11
HoldStart->AcquireStart	1583	Not Covered
HoldStart->ClockStart	1054	Covered	T2,T6,T7
HoldStart->Idle	1581	Not Covered
HoldStop->AcquireStart	1583	Not Covered
HoldStop->Idle	1250	Not Covered
HoldStop->PopFmtFifo	1254	Covered	T2,T7,T11
HostClockLowAck->AcquireStart	1583	Not Covered
HostClockLowAck->HostClockPulseAck	1186	Covered	T2,T11,T12
HostClockLowAck->Idle	1581	Not Covered
HostClockPulseAck->AcquireStart	1583	Not Covered
HostClockPulseAck->HostHoldBitAck	1199	Covered	T2,T11,T12
HostClockPulseAck->Idle	1581	Not Covered
HostHoldBitAck->AcquireStart	1583	Not Covered
HostHoldBitAck->ClockStop	1211	Covered	T2,T11,T12
HostHoldBitAck->Idle	1581	Not Covered
HostHoldBitAck->PopFmtFifo	1215	Covered	T2,T33,T16
HostHoldBitAck->ReadClockLow	1220	Covered	T2,T11,T12
Idle->AcquireStart	1583	Covered	T3,T4,T5
Idle->Active	1033	Covered	T2,T6,T7
NackHold->AcquireStart	1583	Not Covered
NackHold->Idle	1497	Not Covered
NackPulse->AcquireStart	1583	Not Covered
NackPulse->Idle	1581	Not Covered
NackPulse->NackHold	1488	Not Covered
NackSetup->AcquireStart	1583	Not Covered
NackSetup->Idle	1581	Not Covered
NackSetup->NackPulse	1482	Not Covered
NackWait->AcquireStart	1583	Not Covered
NackWait->Idle	1581	Not Covered
NackWait->NackSetup	1476	Not Covered
PopFmtFifo->AcquireStart	1583	Not Covered
PopFmtFifo->Active	1289	Covered	T2,T7,T11
PopFmtFifo->ClockStop	1281	Not Covered
PopFmtFifo->Idle	1285	Covered	T2,T7,T11
ReadClockLow->AcquireStart	1583	Not Covered
ReadClockLow->Idle	1581	Not Covered
ReadClockLow->ReadClockPulse	1148	Covered	T2,T11,T12
ReadClockPulse->AcquireStart	1583	Not Covered
ReadClockPulse->Idle	1581	Not Covered
ReadClockPulse->ReadHoldBit	1160	Covered	T2,T11,T12
ReadHoldBit->AcquireStart	1583	Not Covered
ReadHoldBit->HostClockLowAck	1172	Covered	T2,T11,T12
ReadHoldBit->Idle	1581	Not Covered
ReadHoldBit->ReadClockLow	1176	Covered	T2,T11,T12
SetupStart->AcquireStart	1583	Not Covered
SetupStart->HoldStart	1045	Covered	T2,T6,T7
SetupStart->Idle	1581	Not Covered
SetupStop->AcquireStart	1583	Not Covered
SetupStop->HoldStop	1238	Covered	T2,T7,T11
SetupStop->Idle	1581	Not Covered
StretchAcqFull->AcquireByte	1548	Not Covered
StretchAcqFull->AcquireStart	1583	Not Covered
StretchAcqFull->Idle	1581	Not Covered
StretchAddr->AcquireByte	1513	Not Covered
StretchAddr->AcquireStart	1583	Not Covered
StretchAddr->Idle	1581	Not Covered
StretchAddr->StretchTx	1513	Not Covered
StretchTx->AcquireStart	1583	Not Covered
StretchTx->Idle	1581	Not Covered
StretchTx->StretchTxSetup	1527	Covered	T3,T4,T5
StretchTxSetup->AcquireStart	1583	Not Covered
StretchTxSetup->Idle	1581	Not Covered
StretchTxSetup->TransmitSetup	1538	Covered	T3,T4,T5
TransmitAck->AcquireStart	1583	Not Covered
TransmitAck->Idle	1581	Not Covered
TransmitAck->TransmitAckPulse	1407	Covered	T3,T4,T5
TransmitAckPulse->AcquireStart	1583	Not Covered
TransmitAckPulse->Idle	1581	Not Covered
TransmitAckPulse->TransmitWait	1416	Covered	T3,T4,T5
TransmitAckPulse->WaitForStop	1419	Covered	T3,T4,T5
TransmitHold->AcquireStart	1583	Not Covered
TransmitHold->Idle	1581	Not Covered
TransmitHold->TransmitAck	1396	Covered	T3,T4,T5
TransmitHold->TransmitSetup	1400	Covered	T3,T4,T5
TransmitPulse->AcquireStart	1583	Covered	T24,T25,T51
TransmitPulse->Idle	1581	Covered	T24,T25,T51
TransmitPulse->TransmitHold	1387	Covered	T3,T4,T5
TransmitSetup->AcquireStart	1583	Not Covered
TransmitSetup->Idle	1581	Not Covered
TransmitSetup->TransmitPulse	1382	Covered	T3,T4,T5
TransmitWait->AcquireStart	1583	Not Covered
TransmitWait->Idle	1581	Not Covered
TransmitWait->StretchTx	1373	Covered	T3,T4,T5
TransmitWait->TransmitSetup	1375	Covered	T3,T4,T5
WaitForStop->AcquireStart	1583	Covered	T3,T4,T5
WaitForStop->Idle	1581	Covered	T3,T4,T5

---

Branch Coverage for Module : i2c_fsm

	Line No.	Total	Covered	Percent
Branches		303	254	83.83
IF	176	15	14	93.33
IF	198	2	2	100.00
IF	211	5	5	100.00
IF	229	3	2	66.67
IF	255	4	4	100.00
IF	270	4	3	75.00
IF	281	4	4	100.00
IF	294	4	4	100.00
IF	305	3	3	100.00
IF	312	4	4	100.00
IF	325	2	2	100.00
IF	339	5	4	80.00
IF	351	5	4	80.00
IF	375	4	4	100.00
IF	385	4	4	100.00
IF	395	4	4	100.00
IF	417	5	5	100.00
IF	438	5	5	100.00
IF	449	4	4	100.00
IF	535	4	4	100.00
IF	558	3	3	100.00
CASE	602	79	63	79.75
IF	978	3	3	100.00
CASE	1028	120	93	77.50
IF	1572	4	3	75.00
IF	1596	2	2	100.00
IF	1605	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	176	if (load_tcount)
-2-:	177	case (tcount_sel)
-3-:	192	if ((host_enable_i || target_enable_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	tSetupStart	-	Covered	T2,T6,T7
1	tHoldStart	-	Covered	T2,T6,T7
1	tSetupData	-	Covered	T3,T4,T5
1	tClockStart	-	Covered	T2,T3,T6
1	tClockLow	-	Covered	T2,T6,T7
1	tClockPulse	-	Covered	T2,T6,T7
1	tClockHigh	-	Covered	T2,T6,T7
1	tHoldBit	-	Covered	T2,T6,T7
1	tClockStop	-	Covered	T2,T7,T11
1	tSetupStop	-	Covered	T2,T7,T11
1	tHoldStop	-	Covered	T2,T7,T11
1	tNoDelay	-	Covered	T2,T7,T11
1	default	-	Not Covered
0	-	1	Covered	T2,T3,T6
0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	198	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	211	if ((!rst_ni))
-2-:	213	if (stretch_en)
-3-:	216	if (((!target_idle_o) && event_host_timeout_o))
-4-:	219	if (((!target_idle_o) && scl_i))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T2,T6,T7
0	0	1	-	Covered	T8,T9,T10
0	0	0	1	Covered	T3,T4,T5
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	229	if ((!rst_ni))
-2-:	231	if (actively_stretching)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	255	if ((!rst_ni))
-2-:	258	if ((stretch_idle_cnt == stretch_cnt_threshold))
-3-:	260	if ((!stretch_en))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T6
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T2,T6,T7

	LineNo.	Expression
-1-:	270	if ((!rst_ni))
-2-:	272	if (set_nack_next_byte)
-3-:	274	if (clear_nack_next_byte)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	281	if ((!rst_ni))
-2-:	283	if (bit_clr)
-3-:	285	if (bit_decr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	294	if ((!rst_ni))
-2-:	296	if (read_byte_clr)
-3-:	298	if (shift_data_en)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T11,T12
0	0	1	Covered	T2,T11,T12
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!fmt_flag_read_bytes_i))
-2-:	306	if ((fmt_byte_i == '0))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
0	0	Covered	T2,T11,T12

	LineNo.	Expression
-1-:	312	if ((!rst_ni))
-2-:	314	if (byte_clr)
-3-:	316	if (byte_decr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T11,T12
0	0	1	Covered	T2,T11,T12
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	325	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	339	if ((!rst_ni))
-2-:	341	if ((trans_started && (!host_enable_i)))
-3-:	343	if (log_start)
-4-:	345	if (log_stop)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	-	Covered	T2,T6,T7
0	0	0	1	Covered	T2,T7,T11
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	351	if ((!rst_ni))
-2-:	353	if ((pend_restart && (!host_enable_i)))
-3-:	355	if (req_restart)
-4-:	357	if (log_start)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	-	Covered	T2,T16,T17
0	0	0	1	Covered	T2,T6,T7
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	375	if ((!rst_ni))
-2-:	377	if ((start_det_trigger || stop_det_trigger))
-3-:	379	if ((start_det_pending || stop_det_pending))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T5
0	0	1	Covered	T3,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	385	if ((!rst_ni))
-2-:	387	if (start_det_trigger)
-3-:	389	if (((((!target_enable_i) || (!scl_i)) || start_det) || stop_det_trigger))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T5
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	395	if ((!rst_ni))
-2-:	397	if (stop_det_trigger)
-3-:	399	if (((((!target_enable_i) || (!scl_i)) || stop_det) || start_det_trigger))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T5
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	417	if ((!rst_ni))
-2-:	419	if (start_det)
-3-:	421	if ((scl_i_q && (!scl_i)))
-4-:	424	if ((input_byte_clr || bit_ack))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T3,T4,T5
0	0	1	1	Covered	T2,T3,T6
0	0	1	0	Covered	T2,T3,T6
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	438	if ((!rst_ni))
-2-:	440	if (input_byte_clr)
-3-:	442	if (((!scl_i_q) && scl_i))
-4-:	443	if ((!bit_ack))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T3,T4,T5
0	0	1	1	Covered	T2,T3,T6
0	0	1	0	Covered	T2,T3,T6
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	449	if ((!rst_ni))
-2-:	451	if (((!scl_i_q) && scl_i))
-3-:	452	if (bit_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	1	Covered	T2,T3,T6
0	1	0	Covered	T2,T3,T6
0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	535	if ((!rst_ni))
-2-:	537	if (((!en_sda_interf_det) && (|sda_rise_cnt)))
-3-:	542	if ((en_sda_interf_det && (sda_rise_cnt < sda_rise_latency)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	558	if ((!rst_ni))
-2-:	560	if ((bit_ack && address_match))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	602	case (state_q)
-2-:	608	if ((host_enable_i && trans_started))
-3-:	626	if (log_start)
-4-:	642	if (pend_restart)
-5-:	655	if ((scl_i_q && (!scl_i)))
-6-:	656	if ((sda_i_q != sda_i))
-7-:	675	if (((((!scl_i_q) && scl_i) && sda_i) && (!fmt_flag_nak_ok_i)))
-8-:	677	if ((scl_i_q && (!scl_i)))
-9-:	678	if ((sda_i_q != sda_i))
-10-:	697	if ((scl_i_q && (!scl_i)))
-11-:	698	if ((sda_i_q != sda_i))
-12-:	704	if (((bit_index == '0) && (tcount_q == 20'b1)))
-13-:	716	if (fmt_flag_read_continue_i)
-14-:	717	if ((byte_index == 9'b1))
-15-:	723	if (fmt_flag_read_continue_i)
-16-:	724	if ((byte_index == 9'b1))
-17-:	728	if ((scl_i_q && (!scl_i)))
-18-:	729	if ((sda_i_q != sda_i))
-19-:	734	if (fmt_flag_read_continue_i)
-20-:	735	if ((byte_index == 9'b1))
-21-:	771	if (fmt_flag_stop_after_i)
-22-:	809	if ((tcount_q == 20'b1))
-23-:	810	if (nack_next_byte_q)
-24-:	852	if ((!scl_i))
-25-:	886	if ((tcount_q == 20'b1))
-26-:	910	if ((tcount_q == 20'b1))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
Idle	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
SetupStart	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T7
SetupStart	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T7
HoldStart	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T7
ClockStart	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T7
ClockLow	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T16,T17
ClockLow	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T7
ClockPulse	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ClockPulse	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T7
ClockPulse	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T18,T27
ClockPulse	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T7
HoldBit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T7
ClockLowAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T7
ClockPulseAck	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T28,T29
ClockPulseAck	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T7
ClockPulseAck	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ClockPulseAck	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T7
ClockPulseAck	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T7
ClockPulseAck	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T7
HoldDevAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T7,T11
ReadClockLow	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T11,T12
ReadClockPulse	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ReadClockPulse	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T11,T12
ReadClockPulse	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T33
ReadClockPulse	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T11,T12
ReadHoldBit	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T11,T12
ReadHoldBit	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T11,T12
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T33,T16
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T11,T12
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T11,T12
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T33,T16
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T11,T12
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	Covered	T2,T11,T12
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Not Covered
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T2,T11,T12
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T34,T35,T36
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T2,T11,T12
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T2,T33,T16
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	Covered	T2,T11,T12
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	Covered	T2,T11,T12
ClockStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T7,T11
SetupStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T7,T11
HoldStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T7,T11
Active	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T7
PopFmtFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T2,T7,T11
PopFmtFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T7,T11
AcquireStart	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
AddrRead	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
AddrAckWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
AddrAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
AddrAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
AddrAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	Not Covered
AddrAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	Covered	T3,T4,T5
AddrAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Not Covered
TransmitWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
TransmitSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
TransmitPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
TransmitHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
TransmitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
TransmitAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T3,T4,T5
TransmitAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T3,T4,T5
WaitForStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
AcquireByte	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T21,T8
AcquireAckWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T21,T8
AcquireAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T21,T8
AcquireAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T21,T8
AcquireAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T5,T21,T8
AcquireAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Not Covered
NackWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
NackSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
NackPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
NackHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Not Covered
NackHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Not Covered
StretchAddr	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StretchTx	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
StretchTxSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
StretchAcqFull	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	978	if ((start_det || stop_det))
-2-:	981	(start_det) ? 

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1028	case (state_q)
-2-:	1031	if (((!host_enable_i) && (!target_enable_i)))
-3-:	1032	if (host_enable_i)
-4-:	1033	if (fmt_fifo_rvalid_i)
-5-:	1044	if ((tcount_q == 20'b1))
-6-:	1053	if ((tcount_q == 20'b1))
-7-:	1061	if ((tcount_q == 20'b1))
-8-:	1070	if ((tcount_q == 20'b1))
-9-:	1072	if (pend_restart)
-10-:	1084	if (((!scl_i) && stretch_predict_cnt_expired))
-11-:	1088	if ((tcount_q == 20'b1))
-12-:	1097	if ((tcount_q == 20'b1))
-13-:	1101	if ((bit_index == '0))
-14-:	1113	if ((tcount_q == 20'b1))
-15-:	1121	if (((!scl_i) && stretch_predict_cnt_expired))
-16-:	1125	if ((tcount_q == 20'b1))
-17-:	1133	if ((tcount_q == 20'b1))
-18-:	1134	if (fmt_flag_stop_after_i)
-19-:	1147	if ((tcount_q == 20'b1))
-20-:	1155	if (((!scl_i) && stretch_predict_cnt_expired))
-21-:	1159	if ((tcount_q == 20'b1))
-22-:	1168	if ((tcount_q == 20'b1))
-23-:	1171	if ((bit_index == '0))
-24-:	1185	if ((tcount_q == 20'b1))
-25-:	1194	if (((!scl_i) && stretch_predict_cnt_expired))
-26-:	1198	if ((tcount_q == 20'b1))
-27-:	1207	if ((tcount_q == 20'b1))
-28-:	1209	if ((byte_index == 9'b1))
-29-:	1210	if (fmt_flag_stop_after_i)
-30-:	1229	if ((tcount_q == 20'b1))
-31-:	1237	if ((tcount_q == 20'b1))
-32-:	1247	if ((tcount_q == 20'b1))
-33-:	1249	if ((!host_enable_i))
-34-:	1262	if (fmt_flag_read_bytes_i)
-35-:	1267	if ((fmt_flag_start_before_i && (!trans_started)))
-36-:	1280	if ((!host_enable_i))
-37-:	1284	if ((fmt_fifo_depth_i == 7'b1))
-38-:	1302	if ((scl_i_q && (!scl_i)))
-39-:	1311	if (bit_ack)
-40-:	1312	if (address_match)
-41-:	1313	if (acq_fifo_full_or_last_space)
-42-:	1318	if (rw_bit_q)
-43-:	1337	if (((tcount_q == 20'b1) && (!scl_i)))
-44-:	1343	if (scl_i)
-45-:	1347	if ((!scl_i))
-46-:	1355	if ((tcount_q == 20'b1))
-47-:	1361	if ((stretch_addr && (!nack_next_byte_q)))
-48-:	1363	if (rw_bit_q)
-49-:	1365	if ((!rw_bit_q))
-50-:	1372	if (stretch_tx)
-51-:	1382	if (scl_i)
-52-:	1386	if ((!scl_i))
-53-:	1394	if ((tcount_q == 20'b1))
-54-:	1395	if (bit_ack)
-55-:	1406	if (scl_i)
-56-:	1413	if ((!scl_i))
-57-:	1415	if (host_ack)
-58-:	1431	if (bit_ack)
-59-:	1438	if ((acq_fifo_full_or_last_space || nack_next_byte_q))
-60-:	1449	if (((tcount_q == 20'b1) && (!scl_i)))
-61-:	1455	if (scl_i)
-62-:	1459	if ((!scl_i))
-63-:	1467	if ((tcount_q == 20'b1))
-64-:	1470	(stretch_rx) ? 
-65-:	1475	if (((tcount_q == 20'b1) && (!scl_i)))
-66-:	1481	if (scl_i)
-67-:	1487	if ((!scl_i))
-68-:	1495	if ((tcount_q == 20'b1))
-69-:	1507	if (((!stretch_addr) || nack_timeout))
-70-:	1513	(rw_bit_q) ? 
-71-:	1520	if ((!stretch_tx))
-72-:	1537	if ((tcount_q == 20'b1))
-73-:	1547	if (((~stretch_rx) || nack_timeout))

Branches:

Branch	Status	Tests
(1.Idle )->(2)	Covered	T1,T2,T3
(1.Idle )->(!2)->(3)->(4)	Covered	T2,T6,T7
(1.Idle )->(!2)->(3)->(!4)	Covered	T2,T6,T7
(1.Idle )->(!2)->(!3)	Covered	T3,T4,T5
(1.SetupStart )->(5)	Covered	T2,T6,T7
(1.SetupStart )->(!5)	Covered	T2,T6,T7
(1.HoldStart )->(6)	Covered	T2,T6,T7
(1.HoldStart )->(!6)	Covered	T2,T6,T7
(1.ClockStart )->(7)	Covered	T2,T6,T7
(1.ClockStart )->(!7)	Covered	T15,T40,T41
(1.ClockLow )->(8)->(9)	Covered	T2,T16,T17
(1.ClockLow )->(8)->(!9)	Covered	T2,T6,T7
(1.ClockLow )->(!8)	Covered	T2,T6,T7
(1.ClockPulse )->(10)	Covered	T42,T43,T44
(1.ClockPulse )->(!10)->(11)	Covered	T2,T6,T7
(1.ClockPulse )->(!10)->(!11)	Covered	T2,T6,T7
(1.HoldBit )->(12)->(13)	Covered	T2,T6,T7
(1.HoldBit )->(12)->(!13)	Covered	T2,T6,T7
(1.HoldBit )->(!12)	Covered	T2,T6,T7
(1.ClockLowAck )->(14)	Covered	T2,T6,T7
(1.ClockLowAck )->(!14)	Covered	T2,T6,T7
(1.ClockPulseAck )->(15)	Covered	T2,T6,T7
(1.ClockPulseAck )->(!15)->(16)	Covered	T2,T7,T11
(1.ClockPulseAck )->(!15)->(!16)	Covered	T2,T6,T7
(1.HoldDevAck )->(17)->(18)	Covered	T7,T11,T12
(1.HoldDevAck )->(17)->(!18)	Covered	T2,T7,T11
(1.HoldDevAck )->(!17)	Covered	T2,T7,T11
(1.ReadClockLow )->(19)	Covered	T2,T11,T12
(1.ReadClockLow )->(!19)	Covered	T2,T11,T12
(1.ReadClockPulse )->(20)	Covered	T43,T44,T45
(1.ReadClockPulse )->(!20)->(21)	Covered	T2,T11,T12
(1.ReadClockPulse )->(!20)->(!21)	Covered	T2,T11,T12
(1.ReadHoldBit )->(22)->(23)	Covered	T2,T11,T12
(1.ReadHoldBit )->(22)->(!23)	Covered	T2,T11,T12
(1.ReadHoldBit )->(!22)	Covered	T2,T11,T12
(1.HostClockLowAck )->(24)	Covered	T2,T11,T12
(1.HostClockLowAck )->(!24)	Covered	T2,T11,T12
(1.HostClockPulseAck )->(25)	Covered	T43,T44,T45
(1.HostClockPulseAck )->(!25)->(26)	Covered	T2,T11,T12
(1.HostClockPulseAck )->(!25)->(!26)	Covered	T2,T11,T12
(1.HostHoldBitAck )->(27)->(28)->(29)	Covered	T2,T11,T12
(1.HostHoldBitAck )->(27)->(28)->(!29)	Covered	T2,T33,T16
(1.HostHoldBitAck )->(27)->(!28)	Covered	T2,T11,T12
(1.HostHoldBitAck )->(!27)	Covered	T2,T11,T12
(1.ClockStop )->(30)	Covered	T2,T7,T11
(1.ClockStop )->(!30)	Covered	T2,T7,T11
(1.SetupStop )->(31)	Covered	T2,T7,T11
(1.SetupStop )->(!31)	Covered	T2,T7,T11
(1.HoldStop )->(32)->(33)	Not Covered
(1.HoldStop )->(32)->(!33)	Covered	T2,T7,T11
(1.HoldStop )->(!32)	Covered	T7,T11,T12
(1.Active )->(34)	Covered	T2,T11,T12
(1.Active )->(!34)->(35)	Covered	T2,T6,T7
(1.Active )->(!34)->(!35)	Covered	T2,T7,T11
(1.PopFmtFifo )->(36)	Not Covered
(1.PopFmtFifo )->(!36)->(37)	Covered	T2,T7,T11
(1.PopFmtFifo )->(!36)->(!37)	Covered	T2,T7,T11
(1.AcquireStart )->(38)	Covered	T3,T4,T5
(1.AcquireStart )->(!38)	Covered	T3,T4,T5
(1.AddrRead )->(39)->(40)->(41)->(42)	Not Covered
(1.AddrRead )->(39)->(40)->(41)->(!42)	Not Covered
(1.AddrRead )->(39)->(40)->(!41)	Covered	T3,T4,T5
(1.AddrRead )->(39)->(!40)	Covered	T21,T22,T23
(1.AddrRead )->(!39)	Covered	T3,T4,T5
(1.AddrAckWait )->(43)	Covered	T3,T4,T5
(1.AddrAckWait )->(!43)	Not Covered
(1.AddrAckSetup )->(44)	Covered	T3,T4,T5
(1.AddrAckSetup )->(!44)	Covered	T3,T4,T5
(1.AddrAckPulse )->(45)	Covered	T3,T4,T5
(1.AddrAckPulse )->(!45)	Covered	T3,T4,T5
(1.AddrAckHold )->(46)->(47)	Not Covered
(1.AddrAckHold )->(46)->(!47)->(48)	Covered	T3,T4,T5
(1.AddrAckHold )->(46)->(!47)->(!48)->(49)	Covered	T5,T21,T8
(1.AddrAckHold )->(46)->(!47)->(!48)->(!49)	Not Covered
(1.AddrAckHold )->(!46)	Not Covered
(1.TransmitWait )->(50)	Covered	T3,T4,T5
(1.TransmitWait )->(!50)	Covered	T3,T4,T5
(1.TransmitSetup )->(51)	Covered	T3,T4,T5
(1.TransmitSetup )->(!51)	Covered	T3,T4,T5
(1.TransmitPulse )->(52)	Covered	T3,T4,T5
(1.TransmitPulse )->(!52)	Covered	T3,T4,T5
(1.TransmitHold )->(53)->(54)	Covered	T3,T4,T5
(1.TransmitHold )->(53)->(!54)	Covered	T3,T4,T5
(1.TransmitHold )->(!53)	Not Covered
(1.TransmitAck )->(55)	Covered	T3,T4,T5
(1.TransmitAck )->(!55)	Covered	T3,T4,T5
(1.TransmitAckPulse )->(56)->(57)	Covered	T3,T4,T5
(1.TransmitAckPulse )->(56)->(!57)	Covered	T3,T4,T5
(1.TransmitAckPulse )->(!56)	Covered	T3,T4,T5
(1.WaitForStop )	Covered	T3,T4,T5
(1.AcquireByte )->(58)->(59)	Not Covered
(1.AcquireByte )->(58)->(!59)	Covered	T5,T21,T8
(1.AcquireByte )->(!58)	Covered	T5,T21,T8
(1.AcquireAckWait )->(60)	Covered	T5,T21,T8
(1.AcquireAckWait )->(!60)	Not Covered
(1.AcquireAckSetup )->(61)	Covered	T5,T21,T8
(1.AcquireAckSetup )->(!61)	Covered	T5,T21,T8
(1.AcquireAckPulse )->(62)	Covered	T5,T21,T8
(1.AcquireAckPulse )->(!62)	Covered	T5,T21,T8
(1.AcquireAckHold )->(63)->(64)	Not Covered
(1.AcquireAckHold )->(63)->(!64)	Covered	T5,T21,T8
(1.AcquireAckHold )->(!63)	Not Covered
(1.NackWait )->(65)	Not Covered
(1.NackWait )->(!65)	Not Covered
(1.NackSetup )->(66)	Not Covered
(1.NackSetup )->(!66)	Not Covered
(1.NackPulse )->(67)	Not Covered
(1.NackPulse )->(!67)	Not Covered
(1.NackHold )->(68)	Not Covered
(1.NackHold )->(!68)	Not Covered
(1.StretchAddr )->(69)->(70)	Not Covered
(1.StretchAddr )->(69)->(!70)	Not Covered
(1.StretchAddr )->(!69)	Not Covered
(1.StretchTx )->(71)	Covered	T3,T4,T5
(1.StretchTx )->(!71)	Covered	T3,T4,T5
(1.StretchTxSetup )->(72)	Covered	T3,T4,T5
(1.StretchTxSetup )->(!72)	Covered	T3,T4,T5
(1.StretchAcqFull )->(73)	Not Covered
(1.StretchAcqFull )->(!73)	Not Covered
(1.default)	Not Covered

	LineNo.	Expression
-1-:	1572	if (((!target_idle) && (!target_enable_i)))
-2-:	1582	if (start_det)
-3-:	1584	if (stop_det)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T3,T4,T5
0	0	1	Covered	T3,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1596	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1605	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : i2c_fsm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AcqDepthRdCheck_A	215034851	2161537	0	0
AcqFifoDeepEnough_A	215034851	214913500	0	0
SclInputGlitch_A	210480085	6388581	0	0
SclOutputGlitch_A	215034851	3088703	0	0
SclSdaChangeNotSimultaneous_A	215034851	214913500	0	0

AcqDepthRdCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215034851	2161537	0	0
T3	116169	689	0	0
T4	26433	199	0	0
T5	92969	1338	0	0
T6	3071	0	0	0
T7	12887	0	0	0
T8	0	1911	0	0
T9	0	1990	0	0
T10	0	1304	0	0
T11	220660	0	0	0
T12	396593	0	0	0
T18	4795	0	0	0
T19	1249	0	0	0
T21	0	181	0	0
T37	8296	0	0	0
T52	0	982	0	0
T53	0	1158	0	0
T54	0	352	0	0

AcqFifoDeepEnough_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215034851	214913500	0	0
T1	1531	1438	0	0
T2	38154	38099	0	0
T3	116169	116093	0	0
T4	26433	26369	0	0
T6	3071	2593	0	0
T7	12887	12833	0	0
T11	220660	220599	0	0
T12	396593	396498	0	0
T18	4795	4085	0	0
T19	1249	1167	0	0

SclInputGlitch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210480085	6388581	0	0
T2	38154	606	0	0
T3	116169	5903	0	0
T4	26433	1459	0	0
T5	92969	5035	0	0
T6	76	0	0	0
T7	12887	784	0	0
T11	220660	11720	0	0
T12	396593	19924	0	0
T18	75	0	0	0
T19	1249	2	0	0
T52	0	5565	0	0
T55	0	586	0	0

SclOutputGlitch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215034851	3088703	0	0
T2	38154	606	0	0
T3	116169	269	0	0
T4	26433	58	0	0
T5	92969	42	0	0
T6	3071	20	0	0
T7	12887	784	0	0
T11	220660	11720	0	0
T12	396593	19924	0	0
T18	4795	46	0	0
T19	1249	0	0	0
T52	0	243	0	0

SclSdaChangeNotSimultaneous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215034851	214913500	0	0
T1	1531	1438	0	0
T2	38154	38099	0	0
T3	116169	116093	0	0
T4	26433	26369	0	0
T6	3071	2593	0	0
T7	12887	12833	0	0
T11	220660	220599	0	0
T12	396593	396498	0	0
T18	4795	4085	0	0
T19	1249	1167	0	0