Unified Coverage Report :: Module :: i2c_core

Module : i2c_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.36	96.81	69.74			90.91	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core	89.36	96.81	69.74			90.91	100.00

---

Module Instance : tb.dut.i2c_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.36	96.81	69.74			90.91	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.91	95.92	85.46		42.58	91.74	93.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.72	100.00	100.00	94.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
intr_hw_acq_overflow	94.44	100.00	77.78			100.00	100.00
intr_hw_acq_threshold	100.00	100.00	100.00			100.00	100.00
intr_hw_cmd_complete	100.00	100.00	100.00			100.00	100.00
intr_hw_fmt_threshold	100.00	100.00	100.00			100.00	100.00
intr_hw_host_timeout	100.00	100.00	100.00			100.00	100.00
intr_hw_nak	100.00	100.00	100.00			100.00	100.00
intr_hw_rx_overflow	100.00	100.00	100.00			100.00	100.00
intr_hw_rx_threshold	100.00	100.00	100.00			100.00	100.00
intr_hw_scl_interference	97.92	100.00	91.67			100.00	100.00
intr_hw_sda_interference	100.00	100.00	100.00			100.00	100.00
intr_hw_sda_unstable	100.00	100.00	100.00			100.00	100.00
intr_hw_stretch_timeout	100.00	100.00	100.00			100.00	100.00
intr_hw_tx_stretch	100.00	100.00	100.00			100.00	100.00
intr_hw_tx_threshold	100.00	100.00	100.00			100.00	100.00
intr_hw_unexp_stop	100.00	100.00	100.00			100.00	100.00
u_fifos	94.06	99.86	85.66			98.32	92.39
u_i2c_fsm	79.82	90.57	82.12		42.58	83.83	100.00
u_i2c_sync_scl	100.00	100.00				100.00
u_i2c_sync_sda	100.00	100.00				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c_core

	Line No.	Total	Covered	Percent
TOTAL		94	91	96.81
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	179	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	181	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00
CONT_ASSIGN	190	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	204	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	210	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
ALWAYS	217	5	5	100.00
CONT_ASSIGN	226	1	1	100.00
CONT_ASSIGN	227	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	230	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	232	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	256	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	262	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	275	1	1	100.00
CONT_ASSIGN	276	1	1	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	292	1	0	0.00
CONT_ASSIGN	293	1	0	0.00
CONT_ASSIGN	294	1	0	0.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	296	1	1	100.00
CONT_ASSIGN	297	1	1	100.00
CONT_ASSIGN	341	1	1	100.00
CONT_ASSIGN	346	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	351	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	357	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
183	1	1
184	1	1
185	1	1
186	1	1
187	1	1
188	1	1
189	1	1
190	1	1
194	1	1
195	1	1
197	1	1
199	1	1
200	1	1
202	1	1
203	1	1
204	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
217	1	1
218	1	1
219	1	1
221	1	1
222	1	1
226	1	1
227	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
240	1	1
242	1	1
243	1	1
244	1	1
245	1	1
247	1	1
249	1	1
250	1	1
251	1	1
254	1	1
256	1	1
258	1	1
260	1	1
262	1	1
267	1	1
273	1	1
274	1	1
275	1	1
276	1	1
277	1	1
278	1	1
280	1	1
281	1	1
282	1	1
283	1	1
284	1	1
285	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	0	1
293	0	1
294	0	1
295	1	1
296	1	1
297	1	1
341	1	1
346	1	1
348	1	1
351	1	1
352	1	1
357	1	1

---

Cond Coverage for Module : i2c_core

	Total	Covered	Percent
Conditions	76	53	69.74
Logical	76	53	69.74
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (event_target_nack && (reg2hw.target_nack_count.q < 8'hff))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       199
 EXPRESSION (override ? reg2hw.ovrd.sclval : scl_out_fsm)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T19,T20,T56

 LINE       200
 EXPRESSION (override ? reg2hw.ovrd.sdaval : sda_out_fsm)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T19,T20,T56

 LINE       208
 EXPRESSION (target_enable & line_loopback)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T5
1	1	Not Covered

 LINE       242
 EXPRESSION (reg2hw.fifo_ctrl.rxrst.q & reg2hw.fifo_ctrl.rxrst.qe)
             ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T37,T55,T38
1	0	Covered	T2,T3,T6
1	1	Covered	T2,T3,T6

 LINE       243
 EXPRESSION (reg2hw.fifo_ctrl.fmtrst.q & reg2hw.fifo_ctrl.fmtrst.qe)
             ------------1------------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T37,T55,T38
1	0	Covered	T2,T3,T6
1	1	Covered	T2,T3,T6

 LINE       247
 EXPRESSION ((reg2hw.fifo_ctrl.txrst.q & reg2hw.fifo_ctrl.txrst.qe) || (reg2hw.target_fifo_config.txrst_on_cond.q & target_sr_p_cond))
             ---------------------------1--------------------------    -------------------------------2------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T3,T6

 LINE       247
 SUB-EXPRESSION (reg2hw.fifo_ctrl.txrst.q & reg2hw.fifo_ctrl.txrst.qe)
                 ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T37,T55,T38
1	0	Covered	T2,T3,T6
1	1	Covered	T2,T3,T6

 LINE       247
 SUB-EXPRESSION (reg2hw.target_fifo_config.txrst_on_cond.q & target_sr_p_cond)
                 --------------------1--------------------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Not Covered
1	1	Not Covered

 LINE       249
 EXPRESSION (reg2hw.fifo_ctrl.acqrst.q & reg2hw.fifo_ctrl.acqrst.qe)
             ------------1------------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T37,T55,T38
1	0	Covered	T2,T3,T6
1	1	Covered	T2,T3,T6

 LINE       262
 EXPRESSION (rx_fifo_wvalid & ((~rx_fifo_wready)))
             -------1------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T11,T12
1	1	Covered	T57,T58,T15

 LINE       267
 EXPRESSION (reg2hw.fdata.fbyte.qe & reg2hw.fdata.start.qe & reg2hw.fdata.stop.qe & reg2hw.fdata.readb.qe & reg2hw.fdata.rcont.qe & reg2hw.fdata.nakok.qe)
             ----------1----------   ----------2----------   ----------3---------   ----------4----------   ----------5----------   ----------6----------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	1	1	1	1	1	Not Covered
1	0	1	1	1	1	Not Covered
1	1	0	1	1	1	Not Covered
1	1	1	0	1	1	Not Covered
1	1	1	1	0	1	Not Covered
1	1	1	1	1	0	Not Covered
1	1	1	1	1	1	Covered	T2,T6,T7

 LINE       280
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[7:0] : '0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T7

 LINE       281
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[8] : '0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T7

 LINE       282
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[9] : '0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T7

 LINE       283
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[10] : '0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T7

 LINE       284
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[11] : '0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T7

 LINE       285
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[12] : '0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T7

 LINE       348
 EXPRESSION (target_enable & (acq_type == AcqData))
             ------1------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       348
 SUB-EXPRESSION (acq_type == AcqData)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       351
 EXPRESSION (target_loopback ? (acq_fifo_rvalid & valid_target_lb_wr) : reg2hw.txdata.qe)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       351
 SUB-EXPRESSION (acq_fifo_rvalid & valid_target_lb_wr)
                 -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       352
 EXPRESSION (target_loopback ? acq_fifo_rdata[7:0] : reg2hw.txdata.q)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       357
 EXPRESSION ((reg2hw.acqdata.abyte.re & reg2hw.acqdata.signal.re) | (target_loopback & (tx_fifo_wready | (acq_type != AcqData))))
             --------------------------1-------------------------   ------------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T3,T4,T5

 LINE       357
 SUB-EXPRESSION (reg2hw.acqdata.abyte.re & reg2hw.acqdata.signal.re)
                 -----------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T3,T4,T5

 LINE       357
 SUB-EXPRESSION (target_loopback & (tx_fifo_wready | (acq_type != AcqData)))
                 -------1-------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       357
 SUB-EXPRESSION (tx_fifo_wready | (acq_type != AcqData))
                 -------1------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T59,T60,T61
1	0	Covered	T1,T2,T3

 LINE       357
 SUB-EXPRESSION (acq_type != AcqData)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

---

Branch Coverage for Module : i2c_core

	Line No.	Total	Covered	Percent
Branches		22	20	90.91
TERNARY	199	2	2	100.00
TERNARY	200	2	2	100.00
TERNARY	280	2	2	100.00
TERNARY	281	2	2	100.00
TERNARY	282	2	2	100.00
TERNARY	283	2	2	100.00
TERNARY	284	2	2	100.00
TERNARY	285	2	2	100.00
TERNARY	351	2	1	50.00
TERNARY	352	2	1	50.00
IF	217	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	199	(override) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T20,T56
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	200	(override) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T20,T56
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	280	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	281	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	282	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	283	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	284	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	285	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	351	(target_loopback) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	352	(target_loopback) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	217	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : i2c_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AcqFifoDepthValid_A	1041	1041	0	0
FifoDepthValid_A	1041	1041	0	0

AcqFifoDepthValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1041	1041	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

FifoDepthValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1041	1041	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0