Unified Coverage Report :: Module :: i2c_fifo_sync_sram_adapter

Module : i2c_fifo_sync_sram_adapter

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.57	100.00	86.27			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter	90.55	100.00	76.47			100.00	85.71
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter	94.12	100.00	76.47			100.00	100.00
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter	95.59	100.00	82.35			100.00	100.00
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter	96.57	100.00	86.27			100.00	100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.55	100.00	76.47			100.00	85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.70	100.00	83.65			97.01	94.12

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	100.00				100.00	40.00	u_fifos

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_inp_buf	94.32	100.00	81.82			95.45	100.00
u_oup_buf	97.73	100.00	90.91			100.00	100.00
u_sram_ptrs	94.10	100.00	90.00			92.31

---

Module Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.12	100.00	76.47			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.70	100.00	84.28			98.51	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	100.00				100.00	40.00	u_fifos

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_inp_buf	94.32	100.00	81.82			95.45	100.00
u_oup_buf	97.16	100.00	88.64			100.00	100.00
u_sram_ptrs	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.59	100.00	82.35			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	86.79			98.51	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	100.00				100.00	40.00	u_fifos

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_inp_buf	94.32	100.00	81.82			95.45	100.00
u_oup_buf	97.73	100.00	90.91			100.00	100.00
u_sram_ptrs	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.57	100.00	86.27			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.48	100.00	87.42			98.51	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	100.00				100.00	40.00	u_fifos

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_inp_buf	94.32	100.00	81.82			95.45	100.00
u_oup_buf	97.16	100.00	88.64			100.00	100.00
u_sram_ptrs	100.00	100.00	100.00			100.00

Line Coverage for Module : i2c_fifo_sync_sram_adapter ( parameter Width=13,Depth=64,SramAw=9,SramBaseAddr,DepthW=7,OupBufDepth=2,InpBufDepthW=2,OupBufDepthW=2,SramPtrW=6,SramDepthW=6,SramAddrLeadingZeros=3 )
Line Coverage for Module self-instances :

SCORE	LINE
95.59	100.00

tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

SCORE	LINE
96.57	100.00

tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

SCORE	LINE
94.12	100.00

tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
121	1	1
125	1	1
150	1	1
151	1	1
153	1	1
154	1	1
162	1	1
164	1	1
165	1	1
167	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
183	1	1
184	1	1
185	1	1
187	1	1
			MISSING_ELSE
191	1	1
196	1	1
198	1	1
199	1	1
200	1	1
204	1	1
205	1	1
206	1	1
207	1	1
212	1	1
213	1	1
214	1	1
215	1	1
220	1	1
221	1	1
222	1	1
223	1	1
228	1	1
236	1	1
240	1	1
244	1	1
249	1	1

---

Line Coverage for Module : i2c_fifo_sync_sram_adapter ( parameter Width=13,Depth=268,SramAw=9,SramBaseAddr=192,DepthW=9,OupBufDepth=2,InpBufDepthW=2,OupBufDepthW=2,SramPtrW=9,SramDepthW=9,SramAddrLeadingZeros=0 )
Line Coverage for Module self-instances :

SCORE	LINE
90.55	100.00

tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
121	1	1
125	1	1
150	1	1
151	1	1
156	1	1
157	1	1
162	1	1
164	1	1
165	1	1
167	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
183	1	1
184	1	1
185	1	1
187	1	1
			MISSING_ELSE
191	1	1
196	1	1
198	1	1
199	1	1
200	1	1
204	1	1
205	1	1
206	1	1
207	1	1
212	1	1
213	1	1
214	1	1
215	1	1
220	1	1
221	1	1
222	1	1
223	1	1
228	1	1
236	1	1
240	1	1
244	1	1
249	1	1

---

Cond Coverage for Module : i2c_fifo_sync_sram_adapter

	Total	Covered	Percent
Conditions	51	44	86.27
Logical	51	44	86.27
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T14,T15
1	1	Covered	T2,T3,T4

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T28,T60
1	1	Covered	T2,T3,T4

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T3,T4

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T5,T6

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T5,T6
1	0	Covered	T28,T60,T66

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T28,T60,T66
1	Covered	T2,T3,T4

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T28,T60,T66
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T5,T6

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T5,T6

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T5,T6

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T57
1	1	Covered	T2,T4,T5

---

Branch Coverage for Module : i2c_fifo_sync_sram_adapter

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	162	2	2	100.00
IF	164	2	2	100.00
IF	183	2	2	100.00
IF	191	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	162	(clr_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	183	if (sram_read_in_prev_cyc_q)

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!sram_empty))
-2-:	196	if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-:	212	if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T2,T5,T6
1	0	-	Covered	T2,T3,T4
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : i2c_fifo_sync_sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MinimalSramAw_A	4576	4576	0	0
MinimalSramFifoDepth_A	4576	4576	0	0
NoErr_A	967254596	966711332	0	0
NoSramReadWhenEmpty_A	967254596	752039918	0	0
NoSramWriteWhenFull_A	967254596	19925762	0	0
OupBufWreadyAfterSramRead_A	967254596	616063	0	0
SramRvalidAfterRead_A	967254596	616063	0	0

MinimalSramAw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4576	4576	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T8	4	4	0	0
T9	4	4	0	0
T10	4	4	0	0

MinimalSramFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4576	4576	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T8	4	4	0	0
T9	4	4	0	0
T10	4	4	0	0

NoErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	967254596	966711332	0	0
T1	346404	346124	0	0
T2	947804	947412	0	0
T3	49488	49168	0	0
T4	46012	45728	0	0
T5	324448	324176	0	0
T6	3296284	3290696	0	0
T7	6396	6024	0	0
T8	392792	392400	0	0
T9	42528	42312	0	0
T10	909248	908864	0	0

NoSramReadWhenEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	967254596	752039918	0	0
T1	346404	263926	0	0
T2	947804	723956	0	0
T3	49488	43732	0	0
T4	46012	36391	0	0
T5	324448	249762	0	0
T6	3296284	2627609	0	0
T7	6396	6024	0	0
T8	392792	316735	0	0
T9	42528	34074	0	0
T10	909248	697663	0	0

NoSramWriteWhenFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	967254596	19925762	0	0
T2	236951	113	0	0
T3	12372	0	0	0
T4	11503	4	0	0
T5	162224	43291	0	0
T6	2472213	192514	0	0
T7	4797	0	0	0
T8	294594	0	0	0
T9	31896	3	0	0
T10	681936	3721	0	0
T11	1620	0	0	0
T14	0	3427	0	0
T15	0	20490	0	0
T16	1451139	107075	0	0
T17	0	9688	0	0
T28	0	186283	0	0
T29	0	20025	0	0
T32	154864	0	0	0
T38	14474	0	0	0
T43	0	248408	0	0
T44	0	56139	0	0
T55	2472	0	0	0
T56	0	26354	0	0
T73	0	100	0	0
T80	0	549	0	0
T81	0	2107	0	0
T82	0	66338	0	0
T83	0	2974	0	0
T84	0	43567	0	0

OupBufWreadyAfterSramRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	967254596	616063	0	0
T1	86601	194	0	0
T2	710853	1375	0	0
T3	37116	0	0	0
T4	34509	0	0	0
T5	324448	0	0	0
T6	3296284	3697	0	0
T7	6396	0	0	0
T8	392792	270	0	0
T9	42528	0	0	0
T10	909248	1178	0	0
T15	0	43	0	0
T16	1451139	1087	0	0
T17	0	411	0	0
T23	0	85	0	0
T24	0	20	0	0
T28	0	2614	0	0
T32	77432	225	0	0
T33	0	177	0	0
T38	7237	0	0	0
T47	0	118	0	0
T50	0	92	0	0
T51	0	31	0	0
T53	0	376	0	0
T54	0	288	0	0
T55	1236	0	0	0
T72	0	84	0	0
T73	0	1250	0	0
T85	0	79	0	0

SramRvalidAfterRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	967254596	616063	0	0
T1	86601	194	0	0
T2	710853	1375	0	0
T3	37116	0	0	0
T4	34509	0	0	0
T5	324448	0	0	0
T6	3296284	3697	0	0
T7	6396	0	0	0
T8	392792	270	0	0
T9	42528	0	0	0
T10	909248	1178	0	0
T15	0	43	0	0
T16	1451139	1087	0	0
T17	0	411	0	0
T23	0	85	0	0
T24	0	20	0	0
T28	0	2614	0	0
T32	77432	225	0	0
T33	0	177	0	0
T38	7237	0	0	0
T47	0	118	0	0
T50	0	92	0	0
T51	0	31	0	0
T53	0	376	0	0
T54	0	288	0	0
T55	1236	0	0	0
T72	0	84	0	0
T73	0	1250	0	0
T85	0	79	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
121	1	1
125	1	1
150	1	1
151	1	1
156	1	1
157	1	1
162	1	1
164	1	1
165	1	1
167	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
183	1	1
184	1	1
185	1	1
187	1	1
			MISSING_ELSE
191	1	1
196	1	1
198	1	1
199	1	1
200	1	1
204	1	1
205	1	1
206	1	1
207	1	1
212	1	1
213	1	1
214	1	1
215	1	1
220	1	1
221	1	1
222	1	1
223	1	1
228	1	1
236	1	1
240	1	1
244	1	1
249	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

	Total	Covered	Percent
Conditions	51	39	76.47
Logical	51	39	76.47
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T5,T8

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T63,T64,T65
1	1	Covered	T1,T8,T16

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T16
1	1	Covered	T1,T8,T16

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T16
1	1	Covered	T1,T8,T16

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T16
0	1	Covered	T1,T8,T16
1	0	Covered	T60,T66,T86

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T60,T66,T86
1	Covered	T1,T8,T16

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T60,T66,T86
0	1	Covered	T1,T8,T16
1	0	Covered	T1,T8,T16

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T8,T16
1	1	Covered	T1,T8,T16

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T8,T16
1	1	Covered	T1,T8,T16

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T8,T16
1	1	Covered	T1,T8,T16

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T8,T16
1	1	Covered	T1,T8,T16

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T16
1	1	Covered	T1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T8,T16

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T8,T16

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T8
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	162	2	2	100.00
IF	164	2	2	100.00
IF	183	2	2	100.00
IF	191	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	162	(clr_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	183	if (sram_read_in_prev_cyc_q)

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!sram_empty))
-2-:	196	if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-:	212	if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T8,T16
1	0	-	Covered	T1,T8,T16
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MinimalSramAw_A	1144	1144	0	0
MinimalSramFifoDepth_A	1144	1144	0	0
NoErr_A	241813649	241677833	0	0
NoSramReadWhenEmpty_A	241813649	169989131	0	0
NoSramWriteWhenFull_A	241813649	0	0	0
OupBufWreadyAfterSramRead_A	241813649	165705	0	0
SramRvalidAfterRead_A	241813649	165705	0	0

MinimalSramAw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144	1144	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

MinimalSramFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144	1144	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

NoErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241813649	241677833	0	0
T1	86601	86531	0	0
T2	236951	236853	0	0
T3	12372	12292	0	0
T4	11503	11432	0	0
T5	81112	81044	0	0
T6	824071	822674	0	0
T7	1599	1506	0	0
T8	98198	98100	0	0
T9	10632	10578	0	0
T10	227312	227216	0	0

NoSramReadWhenEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241813649	169989131	0	0
T1	86601	4333	0	0
T2	236951	236853	0	0
T3	12372	12292	0	0
T4	11503	11432	0	0
T5	81112	81044	0	0
T6	824071	822674	0	0
T7	1599	1506	0	0
T8	98198	58393	0	0
T9	10632	10578	0	0
T10	227312	227216	0	0

NoSramWriteWhenFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241813649	0	0	0

OupBufWreadyAfterSramRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241813649	165705	0	0
T1	86601	194	0	0
T2	236951	0	0	0
T3	12372	0	0	0
T4	11503	0	0	0
T5	81112	0	0	0
T6	824071	0	0	0
T7	1599	0	0	0
T8	98198	270	0	0
T9	10632	0	0	0
T10	227312	0	0	0
T16	0	1087	0	0
T17	0	411	0	0
T32	0	225	0	0
T33	0	177	0	0
T47	0	118	0	0
T50	0	92	0	0
T53	0	376	0	0
T54	0	288	0	0

SramRvalidAfterRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241813649	165705	0	0
T1	86601	194	0	0
T2	236951	0	0	0
T3	12372	0	0	0
T4	11503	0	0	0
T5	81112	0	0	0
T6	824071	0	0	0
T7	1599	0	0	0
T8	98198	270	0	0
T9	10632	0	0	0
T10	227312	0	0	0
T16	0	1087	0	0
T17	0	411	0	0
T32	0	225	0	0
T33	0	177	0	0
T47	0	118	0	0
T50	0	92	0	0
T53	0	376	0	0
T54	0	288	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
121	1	1
125	1	1
150	1	1
151	1	1
153	1	1
154	1	1
162	1	1
164	1	1
165	1	1
167	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
183	1	1
184	1	1
185	1	1
187	1	1
			MISSING_ELSE
191	1	1
196	1	1
198	1	1
199	1	1
200	1	1
204	1	1
205	1	1
206	1	1
207	1	1
212	1	1
213	1	1
214	1	1
215	1	1
220	1	1
221	1	1
222	1	1
223	1	1
228	1	1
236	1	1
240	1	1
244	1	1
249	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

	Total	Covered	Percent
Conditions	51	39	76.47
Logical	51	39	76.47
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T5,T8,T16

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T60,T61,T62
1	1	Covered	T5,T8,T16

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T16
1	1	Covered	T5,T8,T16

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T16
1	1	Covered	T5,T8,T16

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T16
0	1	Covered	T5,T8,T16
1	0	Not Covered

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T5,T8,T16

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T5,T8,T16
1	0	Covered	T5,T8,T16

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T8,T16
1	1	Covered	T5,T8,T16

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T8,T16
1	1	Covered	T5,T8,T16

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T8,T16
1	1	Covered	T5,T8,T16

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T8,T16
1	1	Covered	T5,T8,T16

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T16
1	1	Covered	T1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T8,T16

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T8,T16

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T16,T17
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T16,T17

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T16
1	0	Not Covered
1	1	Covered	T5,T16,T17

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	162	2	2	100.00
IF	164	2	2	100.00
IF	183	2	2	100.00
IF	191	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	162	(clr_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	183	if (sram_read_in_prev_cyc_q)

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!sram_empty))
-2-:	196	if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-:	212	if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T5,T8,T16
1	0	-	Covered	T5,T8,T16
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MinimalSramAw_A	1144	1144	0	0
MinimalSramFifoDepth_A	1144	1144	0	0
NoErr_A	241813649	241677833	0	0
NoSramReadWhenEmpty_A	241813649	157743565	0	0
NoSramWriteWhenFull_A	241813649	11140088	0	0
OupBufWreadyAfterSramRead_A	241813649	218808	0	0
SramRvalidAfterRead_A	241813649	218808	0	0

MinimalSramAw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144	1144	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

MinimalSramFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144	1144	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

NoErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241813649	241677833	0	0
T1	86601	86531	0	0
T2	236951	236853	0	0
T3	12372	12292	0	0
T4	11503	11432	0	0
T5	81112	81044	0	0
T6	824071	822674	0	0
T7	1599	1506	0	0
T8	98198	98100	0	0
T9	10632	10578	0	0
T10	227312	227216	0	0

NoSramReadWhenEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241813649	157743565	0	0
T1	86601	86531	0	0
T2	236951	236853	0	0
T3	12372	12292	0	0
T4	11503	11432	0	0
T5	81112	6630	0	0
T6	824071	822674	0	0
T7	1599	1506	0	0
T8	98198	62142	0	0
T9	10632	10578	0	0
T10	227312	227216	0	0

NoSramWriteWhenFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241813649	11140088	0	0
T5	81112	43291	0	0
T6	824071	0	0	0
T7	1599	0	0	0
T8	98198	0	0	0
T9	10632	0	0	0
T10	227312	0	0	0
T16	483713	107075	0	0
T17	0	9688	0	0
T32	77432	0	0	0
T38	7237	0	0	0
T55	1236	0	0	0
T60	0	41973	0	0
T61	0	134736	0	0
T66	0	114694	0	0
T77	0	32815	0	0
T86	0	88166	0	0
T87	0	63755	0	0
T88	0	96648	0	0

OupBufWreadyAfterSramRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241813649	218808	0	0
T5	81112	162	0	0
T6	824071	0	0	0
T7	1599	0	0	0
T8	98198	221	0	0
T9	10632	0	0	0
T10	227312	0	0	0
T16	483713	1043	0	0
T17	0	507	0	0
T32	77432	162	0	0
T33	0	66	0	0
T38	7237	0	0	0
T47	0	86	0	0
T50	0	97	0	0
T53	0	99	0	0
T54	0	79	0	0
T55	1236	0	0	0

SramRvalidAfterRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241813649	218808	0	0
T5	81112	162	0	0
T6	824071	0	0	0
T7	1599	0	0	0
T8	98198	221	0	0
T9	10632	0	0	0
T10	227312	0	0	0
T16	483713	1043	0	0
T17	0	507	0	0
T32	77432	162	0	0
T33	0	66	0	0
T38	7237	0	0	0
T47	0	86	0	0
T50	0	97	0	0
T53	0	99	0	0
T54	0	79	0	0
T55	1236	0	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
121	1	1
125	1	1
150	1	1
151	1	1
153	1	1
154	1	1
162	1	1
164	1	1
165	1	1
167	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
183	1	1
184	1	1
185	1	1
187	1	1
			MISSING_ELSE
191	1	1
196	1	1
198	1	1
199	1	1
200	1	1
204	1	1
205	1	1
206	1	1
207	1	1
212	1	1
213	1	1
214	1	1
215	1	1
220	1	1
221	1	1
222	1	1
223	1	1
228	1	1
236	1	1
240	1	1
244	1	1
249	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

	Total	Covered	Percent
Conditions	51	42	82.35
Logical	51	42	82.35
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T28,T56
1	1	Covered	T2,T3,T6

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T23
1	1	Covered	T2,T3,T6

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T2,T6,T23

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T2,T6,T23
1	0	Covered	T28,T89,T90

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T28,T89,T90
1	Covered	T2,T3,T6

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T28,T89,T90
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T6,T23

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T6
1	1	Covered	T2,T6,T23

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T6
1	1	Covered	T2,T6,T23

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T6
1	1	Covered	T2,T3,T6

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T6
1	1	Covered	T2,T3,T6

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T23
1	1	Covered	T1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T28,T29
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T28,T29

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T6,T28,T29

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	162	2	2	100.00
IF	164	2	2	100.00
IF	183	2	2	100.00
IF	191	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	162	(clr_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	183	if (sram_read_in_prev_cyc_q)

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T23
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!sram_empty))
-2-:	196	if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-:	212	if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T2,T6,T23
1	0	-	Covered	T2,T3,T6
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MinimalSramAw_A	1144	1144	0	0
MinimalSramFifoDepth_A	1144	1144	0	0
NoErr_A	241813649	241677833	0	0
NoSramReadWhenEmpty_A	241813649	203291428	0	0
NoSramWriteWhenFull_A	241813649	8244137	0	0
OupBufWreadyAfterSramRead_A	241813649	112329	0	0
SramRvalidAfterRead_A	241813649	112329	0	0

MinimalSramAw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144	1144	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

MinimalSramFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144	1144	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

NoErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241813649	241677833	0	0
T1	86601	86531	0	0
T2	236951	236853	0	0
T3	12372	12292	0	0
T4	11503	11432	0	0
T5	81112	81044	0	0
T6	824071	822674	0	0
T7	1599	1506	0	0
T8	98198	98100	0	0
T9	10632	10578	0	0
T10	227312	227216	0	0

NoSramReadWhenEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241813649	203291428	0	0
T1	86601	86531	0	0
T2	236951	118173	0	0
T3	12372	6856	0	0
T4	11503	11432	0	0
T5	81112	81044	0	0
T6	824071	334914	0	0
T7	1599	1506	0	0
T8	98198	98100	0	0
T9	10632	10578	0	0
T10	227312	227216	0	0

NoSramWriteWhenFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241813649	8244137	0	0
T6	824071	192329	0	0
T7	1599	0	0	0
T8	98198	0	0	0
T9	10632	0	0	0
T10	227312	0	0	0
T11	1620	0	0	0
T16	483713	0	0	0
T28	0	182190	0	0
T29	0	20025	0	0
T32	77432	0	0	0
T38	7237	0	0	0
T43	0	248408	0	0
T44	0	56139	0	0
T55	1236	0	0	0
T56	0	26354	0	0
T81	0	2107	0	0
T82	0	66338	0	0
T83	0	2974	0	0
T84	0	43567	0	0

OupBufWreadyAfterSramRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241813649	112329	0	0
T2	236951	693	0	0
T3	12372	0	0	0
T4	11503	0	0	0
T5	81112	0	0	0
T6	824071	2575	0	0
T7	1599	0	0	0
T8	98198	0	0	0
T9	10632	0	0	0
T10	227312	0	0	0
T15	0	43	0	0
T16	483713	0	0	0
T23	0	85	0	0
T24	0	20	0	0
T28	0	1002	0	0
T51	0	31	0	0
T72	0	84	0	0
T73	0	630	0	0
T85	0	79	0	0

SramRvalidAfterRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241813649	112329	0	0
T2	236951	693	0	0
T3	12372	0	0	0
T4	11503	0	0	0
T5	81112	0	0	0
T6	824071	2575	0	0
T7	1599	0	0	0
T8	98198	0	0	0
T9	10632	0	0	0
T10	227312	0	0	0
T15	0	43	0	0
T16	483713	0	0	0
T23	0	85	0	0
T24	0	20	0	0
T28	0	1002	0	0
T51	0	31	0	0
T72	0	84	0	0
T73	0	630	0	0
T85	0	79	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
121	1	1
125	1	1
150	1	1
151	1	1
153	1	1
154	1	1
162	1	1
164	1	1
165	1	1
167	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
183	1	1
184	1	1
185	1	1
187	1	1
			MISSING_ELSE
191	1	1
196	1	1
198	1	1
199	1	1
200	1	1
204	1	1
205	1	1
206	1	1
207	1	1
212	1	1
213	1	1
214	1	1
215	1	1
220	1	1
221	1	1
222	1	1
223	1	1
228	1	1
236	1	1
240	1	1
244	1	1
249	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

	Total	Covered	Percent
Conditions	51	44	86.27
Logical	51	44	86.27
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T14,T15
1	1	Covered	T2,T4,T6

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T57,T58,T59
1	1	Covered	T2,T4,T6

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T10
1	1	Covered	T2,T4,T6

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6
1	1	Covered	T2,T6,T10

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T6
0	1	Covered	T2,T6,T10
1	0	Covered	T57,T58,T59

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T57,T58,T59
1	Covered	T2,T4,T6

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T57,T58,T59
0	1	Covered	T2,T4,T6
1	0	Covered	T2,T6,T10

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T6
1	1	Covered	T2,T6,T10

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T6
1	1	Covered	T2,T6,T10

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T6
1	1	Covered	T2,T4,T6

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T6
1	1	Covered	T2,T4,T6

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T10
1	1	Covered	T1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T6

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T6

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T6

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T6
1	0	Covered	T57
1	1	Covered	T2,T4,T6

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	162	2	2	100.00
IF	164	2	2	100.00
IF	183	2	2	100.00
IF	191	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	162	(clr_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	183	if (sram_read_in_prev_cyc_q)

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!sram_empty))
-2-:	196	if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-:	212	if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T2,T6,T10
1	0	-	Covered	T2,T4,T6
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MinimalSramAw_A	1144	1144	0	0
MinimalSramFifoDepth_A	1144	1144	0	0
NoErr_A	241813649	241677833	0	0
NoSramReadWhenEmpty_A	241813649	221015794	0	0
NoSramWriteWhenFull_A	241813649	541537	0	0
OupBufWreadyAfterSramRead_A	241813649	119221	0	0
SramRvalidAfterRead_A	241813649	119221	0	0

MinimalSramAw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144	1144	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

MinimalSramFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144	1144	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

NoErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241813649	241677833	0	0
T1	86601	86531	0	0
T2	236951	236853	0	0
T3	12372	12292	0	0
T4	11503	11432	0	0
T5	81112	81044	0	0
T6	824071	822674	0	0
T7	1599	1506	0	0
T8	98198	98100	0	0
T9	10632	10578	0	0
T10	227312	227216	0	0

NoSramReadWhenEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241813649	221015794	0	0
T1	86601	86531	0	0
T2	236951	132077	0	0
T3	12372	12292	0	0
T4	11503	2095	0	0
T5	81112	81044	0	0
T6	824071	647347	0	0
T7	1599	1506	0	0
T8	98198	98100	0	0
T9	10632	2340	0	0
T10	227312	16015	0	0

NoSramWriteWhenFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241813649	541537	0	0
T2	236951	113	0	0
T3	12372	0	0	0
T4	11503	4	0	0
T5	81112	0	0	0
T6	824071	185	0	0
T7	1599	0	0	0
T8	98198	0	0	0
T9	10632	3	0	0
T10	227312	3721	0	0
T14	0	3427	0	0
T15	0	20490	0	0
T16	483713	0	0	0
T28	0	4093	0	0
T73	0	100	0	0
T80	0	549	0	0

OupBufWreadyAfterSramRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241813649	119221	0	0
T2	236951	682	0	0
T3	12372	0	0	0
T4	11503	0	0	0
T5	81112	0	0	0
T6	824071	1122	0	0
T7	1599	0	0	0
T8	98198	0	0	0
T9	10632	0	0	0
T10	227312	1178	0	0
T14	0	1116	0	0
T16	483713	0	0	0
T28	0	1612	0	0
T29	0	2065	0	0
T73	0	620	0	0
T80	0	992	0	0
T91	0	620	0	0
T92	0	930	0	0

SramRvalidAfterRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241813649	119221	0	0
T2	236951	682	0	0
T3	12372	0	0	0
T4	11503	0	0	0
T5	81112	0	0	0
T6	824071	1122	0	0
T7	1599	0	0	0
T8	98198	0	0	0
T9	10632	0	0	0
T10	227312	1178	0	0
T14	0	1116	0	0
T16	483713	0	0	0
T28	0	1612	0	0
T29	0	2065	0	0
T73	0	620	0	0
T80	0	992	0	0
T91	0	620	0	0
T92	0	930	0	0