Module Definition
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Module Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.32 100.00 81.82 95.45 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.59 100.00 82.35 100.00 100.00 u_fmt_fifo_sram_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 94.10 100.00 90.00 92.31



Module Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.32 100.00 81.82 95.45 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.57 100.00 86.27 100.00 100.00 u_rx_fifo_sram_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 94.10 100.00 90.00 92.31



Module Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.32 100.00 81.82 95.45 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.12 100.00 76.47 100.00 100.00 u_tx_fifo_sram_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 94.10 100.00 90.00 92.31



Module Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.32 100.00 81.82 95.45 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.55 100.00 76.47 100.00 85.71 u_acq_fifo_sram_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 94.10 100.00 90.00 92.31



Module Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.79 100.00 79.17 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.16 100.00 88.64 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.57 100.00 86.27 100.00 100.00 u_rx_fifo_sram_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00



Module Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.79 100.00 79.17 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.16 100.00 88.64 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.12 100.00 76.47 100.00 100.00 u_tx_fifo_sram_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00



Module Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.83 100.00 83.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.59 100.00 82.35 100.00 100.00 u_fmt_fifo_sram_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00



Module Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.83 100.00 83.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.55 100.00 76.47 100.00 85.71 u_acq_fifo_sram_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_fifo_sync
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Cond Coverage for Module : prim_fifo_sync
TotalCoveredPercent
Conditions242083.33
Logical242083.33
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT2,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T3,T4
110Not Covered
111CoveredT2,T3,T4

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT1,T2,T3
11CoveredT2,T3,T4

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT2,T3,T4
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

Branch Coverage for Module : prim_fifo_sync
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T4


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3


Assert Coverage for Module : prim_fifo_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 1934509192 331620749 0 0
DepthKnown_A 1934509192 1933422664 0 0
RvalidKnown_A 1934509192 1933422664 0 0
WreadyKnown_A 1934509192 1933422664 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 1934509192 331620749 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1934509192 331620749 0 0
T1 173202 83560 0 0
T2 1421706 231803 0 0
T3 74232 10353 0 0
T4 69018 10047 0 0
T5 648896 5156 0 0
T6 6592568 801132 0 0
T7 12792 0 0 0
T8 785584 49100 0 0
T9 85056 8885 0 0
T10 1818496 208780 0 0
T14 0 178942 0 0
T16 2902278 313437 0 0
T17 0 132265 0 0
T23 0 32651 0 0
T32 154864 37492 0 0
T33 0 39914 0 0
T38 14474 966 0 0
T47 0 23464 0 0
T50 0 21002 0 0
T51 0 557 0 0
T53 0 792521 0 0
T55 2472 0 0 0
T72 0 20614 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1934509192 1933422664 0 0
T1 692808 692248 0 0
T2 1895608 1894824 0 0
T3 98976 98336 0 0
T4 92024 91456 0 0
T5 648896 648352 0 0
T6 6592568 6581392 0 0
T7 12792 12048 0 0
T8 785584 784800 0 0
T9 85056 84624 0 0
T10 1818496 1817728 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1934509192 1933422664 0 0
T1 692808 692248 0 0
T2 1895608 1894824 0 0
T3 98976 98336 0 0
T4 92024 91456 0 0
T5 648896 648352 0 0
T6 6592568 6581392 0 0
T7 12792 12048 0 0
T8 785584 784800 0 0
T9 85056 84624 0 0
T10 1818496 1817728 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1934509192 1933422664 0 0
T1 692808 692248 0 0
T2 1895608 1894824 0 0
T3 98976 98336 0 0
T4 92024 91456 0 0
T5 648896 648352 0 0
T6 6592568 6581392 0 0
T7 12792 12048 0 0
T8 785584 784800 0 0
T9 85056 84624 0 0
T10 1818496 1817728 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 1934509192 331620749 0 0
T1 173202 83560 0 0
T2 1421706 231803 0 0
T3 74232 10353 0 0
T4 69018 10047 0 0
T5 648896 5156 0 0
T6 6592568 801132 0 0
T7 12792 0 0 0
T8 785584 49100 0 0
T9 85056 8885 0 0
T10 1818496 208780 0 0
T14 0 178942 0 0
T16 2902278 313437 0 0
T17 0 132265 0 0
T23 0 32651 0 0
T32 154864 37492 0 0
T33 0 39914 0 0
T38 14474 966 0 0
T47 0 23464 0 0
T50 0 21002 0 0
T51 0 557 0 0
T53 0 792521 0 0
T55 2472 0 0 0
T72 0 20614 0 0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf
TotalCoveredPercent
Conditions241875.00
Logical241875.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT2,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T6,T73
110Not Covered
111CoveredT2,T3,T4

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T3,T4

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT2,T6,T73
10CoveredT2,T3,T4
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T4


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 241813649 136843 0 0
DepthKnown_A 241813649 241677833 0 0
RvalidKnown_A 241813649 241677833 0 0
WreadyKnown_A 241813649 241677833 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 241813649 136843 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 136843 0 0
T2 236951 746 0 0
T3 12372 61 0 0
T4 11503 2 0 0
T5 81112 0 0 0
T6 824071 2723 0 0
T7 1599 0 0 0
T8 98198 0 0 0
T9 10632 2 0 0
T10 227312 38 0 0
T14 0 36 0 0
T16 483713 0 0 0
T23 0 101 0 0
T38 0 22 0 0
T72 0 110 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 241677833 0 0
T1 86601 86531 0 0
T2 236951 236853 0 0
T3 12372 12292 0 0
T4 11503 11432 0 0
T5 81112 81044 0 0
T6 824071 822674 0 0
T7 1599 1506 0 0
T8 98198 98100 0 0
T9 10632 10578 0 0
T10 227312 227216 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 241677833 0 0
T1 86601 86531 0 0
T2 236951 236853 0 0
T3 12372 12292 0 0
T4 11503 11432 0 0
T5 81112 81044 0 0
T6 824071 822674 0 0
T7 1599 1506 0 0
T8 98198 98100 0 0
T9 10632 10578 0 0
T10 227312 227216 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 241677833 0 0
T1 86601 86531 0 0
T2 236951 236853 0 0
T3 12372 12292 0 0
T4 11503 11432 0 0
T5 81112 81044 0 0
T6 824071 822674 0 0
T7 1599 1506 0 0
T8 98198 98100 0 0
T9 10632 10578 0 0
T10 227312 227216 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 136843 0 0
T2 236951 746 0 0
T3 12372 61 0 0
T4 11503 2 0 0
T5 81112 0 0 0
T6 824071 2723 0 0
T7 1599 0 0 0
T8 98198 0 0 0
T9 10632 2 0 0
T10 227312 38 0 0
T14 0 36 0 0
T16 483713 0 0 0
T23 0 101 0 0
T38 0 22 0 0
T72 0 110 0 0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf
TotalCoveredPercent
Conditions241875.00
Logical241875.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T4,T6

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT2,T4,T6

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT74,T75,T76
110Not Covered
111CoveredT2,T4,T6

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T6

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T4,T6

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT74,T75,T76
10CoveredT2,T4,T6
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT2,T4,T6
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T2,T4,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T4,T6


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T2,T4,T6
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 241813649 275405 0 0
DepthKnown_A 241813649 241677833 0 0
RvalidKnown_A 241813649 241677833 0 0
WreadyKnown_A 241813649 241677833 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 241813649 275405 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 275405 0 0
T2 236951 704 0 0
T3 12372 0 0 0
T4 11503 64 0 0
T5 81112 0 0 0
T6 824071 2140 0 0
T7 1599 0 0 0
T8 98198 0 0 0
T9 10632 64 0 0
T10 227312 1216 0 0
T14 0 1152 0 0
T15 0 853 0 0
T16 483713 0 0 0
T23 0 11 0 0
T24 0 106 0 0
T51 0 557 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 241677833 0 0
T1 86601 86531 0 0
T2 236951 236853 0 0
T3 12372 12292 0 0
T4 11503 11432 0 0
T5 81112 81044 0 0
T6 824071 822674 0 0
T7 1599 1506 0 0
T8 98198 98100 0 0
T9 10632 10578 0 0
T10 227312 227216 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 241677833 0 0
T1 86601 86531 0 0
T2 236951 236853 0 0
T3 12372 12292 0 0
T4 11503 11432 0 0
T5 81112 81044 0 0
T6 824071 822674 0 0
T7 1599 1506 0 0
T8 98198 98100 0 0
T9 10632 10578 0 0
T10 227312 227216 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 241677833 0 0
T1 86601 86531 0 0
T2 236951 236853 0 0
T3 12372 12292 0 0
T4 11503 11432 0 0
T5 81112 81044 0 0
T6 824071 822674 0 0
T7 1599 1506 0 0
T8 98198 98100 0 0
T9 10632 10578 0 0
T10 227312 227216 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 275405 0 0
T2 236951 704 0 0
T3 12372 0 0 0
T4 11503 64 0 0
T5 81112 0 0 0
T6 824071 2140 0 0
T7 1599 0 0 0
T8 98198 0 0 0
T9 10632 64 0 0
T10 227312 1216 0 0
T14 0 1152 0 0
T15 0 853 0 0
T16 483713 0 0 0
T23 0 11 0 0
T24 0 106 0 0
T51 0 557 0 0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf
TotalCoveredPercent
Conditions241875.00
Logical241875.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT5,T8,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT5,T8,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT8,T16,T77
110Not Covered
111CoveredT5,T8,T16

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T8,T16

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT5,T8,T16

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT8,T16,T77
10CoveredT5,T8,T16
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT5,T8,T16
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T5,T8,T16
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T8,T16


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T5,T8,T16
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 241813649 267867 0 0
DepthKnown_A 241813649 241677833 0 0
RvalidKnown_A 241813649 241677833 0 0
WreadyKnown_A 241813649 241677833 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 241813649 267867 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 267867 0 0
T5 81112 164 0 0
T6 824071 0 0 0
T7 1599 0 0 0
T8 98198 292 0 0
T9 10632 0 0 0
T10 227312 0 0 0
T16 483713 1096 0 0
T17 0 547 0 0
T32 77432 204 0 0
T33 0 93 0 0
T38 7237 0 0 0
T47 0 103 0 0
T50 0 119 0 0
T53 0 413 0 0
T54 0 254 0 0
T55 1236 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 241677833 0 0
T1 86601 86531 0 0
T2 236951 236853 0 0
T3 12372 12292 0 0
T4 11503 11432 0 0
T5 81112 81044 0 0
T6 824071 822674 0 0
T7 1599 1506 0 0
T8 98198 98100 0 0
T9 10632 10578 0 0
T10 227312 227216 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 241677833 0 0
T1 86601 86531 0 0
T2 236951 236853 0 0
T3 12372 12292 0 0
T4 11503 11432 0 0
T5 81112 81044 0 0
T6 824071 822674 0 0
T7 1599 1506 0 0
T8 98198 98100 0 0
T9 10632 10578 0 0
T10 227312 227216 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 241677833 0 0
T1 86601 86531 0 0
T2 236951 236853 0 0
T3 12372 12292 0 0
T4 11503 11432 0 0
T5 81112 81044 0 0
T6 824071 822674 0 0
T7 1599 1506 0 0
T8 98198 98100 0 0
T9 10632 10578 0 0
T10 227312 227216 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 267867 0 0
T5 81112 164 0 0
T6 824071 0 0 0
T7 1599 0 0 0
T8 98198 292 0 0
T9 10632 0 0 0
T10 227312 0 0 0
T16 483713 1096 0 0
T17 0 547 0 0
T32 77432 204 0 0
T33 0 93 0 0
T38 7237 0 0 0
T47 0 103 0 0
T50 0 119 0 0
T53 0 413 0 0
T54 0 254 0 0
T55 1236 0 0 0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf
TotalCoveredPercent
Conditions241875.00
Logical241875.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T5,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T5,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT16,T53,T54
110Not Covered
111CoveredT1,T5,T8

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T5,T8

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T5,T8

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT16,T53,T54
10CoveredT1,T5,T8
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T5,T8
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T5,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T5,T8


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T5,T8
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 241813649 279552 0 0
DepthKnown_A 241813649 241677833 0 0
RvalidKnown_A 241813649 241677833 0 0
WreadyKnown_A 241813649 241677833 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 241813649 279552 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 279552 0 0
T1 86601 196 0 0
T2 236951 0 0 0
T3 12372 0 0 0
T4 11503 0 0 0
T5 81112 271 0 0
T6 824071 0 0 0
T7 1599 0 0 0
T8 98198 358 0 0
T9 10632 0 0 0
T10 227312 0 0 0
T16 0 1734 0 0
T17 0 693 0 0
T32 0 282 0 0
T33 0 212 0 0
T47 0 142 0 0
T50 0 123 0 0
T53 0 441 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 241677833 0 0
T1 86601 86531 0 0
T2 236951 236853 0 0
T3 12372 12292 0 0
T4 11503 11432 0 0
T5 81112 81044 0 0
T6 824071 822674 0 0
T7 1599 1506 0 0
T8 98198 98100 0 0
T9 10632 10578 0 0
T10 227312 227216 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 241677833 0 0
T1 86601 86531 0 0
T2 236951 236853 0 0
T3 12372 12292 0 0
T4 11503 11432 0 0
T5 81112 81044 0 0
T6 824071 822674 0 0
T7 1599 1506 0 0
T8 98198 98100 0 0
T9 10632 10578 0 0
T10 227312 227216 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 241677833 0 0
T1 86601 86531 0 0
T2 236951 236853 0 0
T3 12372 12292 0 0
T4 11503 11432 0 0
T5 81112 81044 0 0
T6 824071 822674 0 0
T7 1599 1506 0 0
T8 98198 98100 0 0
T9 10632 10578 0 0
T10 227312 227216 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 279552 0 0
T1 86601 196 0 0
T2 236951 0 0 0
T3 12372 0 0 0
T4 11503 0 0 0
T5 81112 271 0 0
T6 824071 0 0 0
T7 1599 0 0 0
T8 98198 358 0 0
T9 10632 0 0 0
T10 227312 0 0 0
T16 0 1734 0 0
T17 0 693 0 0
T32 0 282 0 0
T33 0 212 0 0
T47 0 142 0 0
T50 0 123 0 0
T53 0 441 0 0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf
TotalCoveredPercent
Conditions241979.17
Logical241979.17
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T4,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T4,T6

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT2,T4,T6

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T4,T6
110Not Covered
111CoveredT2,T6,T10

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T6

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT2,T4,T6
10CoveredT1,T2,T3
11CoveredT2,T4,T6

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT2,T4,T6
10CoveredT2,T4,T6
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT2,T4,T6
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T2,T4,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T4,T6


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T2,T4,T6
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 241813649 24301315 0 0
DepthKnown_A 241813649 241677833 0 0
RvalidKnown_A 241813649 241677833 0 0
WreadyKnown_A 241813649 241677833 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 241813649 24301315 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 24301315 0 0
T2 236951 108213 0 0
T3 12372 0 0 0
T4 11503 9644 0 0
T5 81112 0 0 0
T6 824071 189391 0 0
T7 1599 0 0 0
T8 98198 0 0 0
T9 10632 8509 0 0
T10 227312 217997 0 0
T14 0 196336 0 0
T15 0 45154 0 0
T16 483713 0 0 0
T23 0 79 0 0
T24 0 3312 0 0
T51 0 12202 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 241677833 0 0
T1 86601 86531 0 0
T2 236951 236853 0 0
T3 12372 12292 0 0
T4 11503 11432 0 0
T5 81112 81044 0 0
T6 824071 822674 0 0
T7 1599 1506 0 0
T8 98198 98100 0 0
T9 10632 10578 0 0
T10 227312 227216 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 241677833 0 0
T1 86601 86531 0 0
T2 236951 236853 0 0
T3 12372 12292 0 0
T4 11503 11432 0 0
T5 81112 81044 0 0
T6 824071 822674 0 0
T7 1599 1506 0 0
T8 98198 98100 0 0
T9 10632 10578 0 0
T10 227312 227216 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 241677833 0 0
T1 86601 86531 0 0
T2 236951 236853 0 0
T3 12372 12292 0 0
T4 11503 11432 0 0
T5 81112 81044 0 0
T6 824071 822674 0 0
T7 1599 1506 0 0
T8 98198 98100 0 0
T9 10632 10578 0 0
T10 227312 227216 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 24301315 0 0
T2 236951 108213 0 0
T3 12372 0 0 0
T4 11503 9644 0 0
T5 81112 0 0 0
T6 824071 189391 0 0
T7 1599 0 0 0
T8 98198 0 0 0
T9 10632 8509 0 0
T10 227312 217997 0 0
T14 0 196336 0 0
T15 0 45154 0 0
T16 483713 0 0 0
T23 0 79 0 0
T24 0 3312 0 0
T51 0 12202 0 0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf
TotalCoveredPercent
Conditions241979.17
Logical241979.17
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT5,T8,T16
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT5,T8,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT5,T8,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT5,T8,T16
110Not Covered
111CoveredT5,T8,T16

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T8,T16

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT5,T8,T16
10CoveredT1,T2,T3
11CoveredT5,T8,T16

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT5,T8,T16
10CoveredT5,T8,T16
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT5,T8,T16
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T5,T8,T16
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T8,T16


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T5,T8,T16
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 241813649 114599649 0 0
DepthKnown_A 241813649 241677833 0 0
RvalidKnown_A 241813649 241677833 0 0
WreadyKnown_A 241813649 241677833 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 241813649 114599649 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 114599649 0 0
T5 81112 74857 0 0
T6 824071 0 0 0
T7 1599 0 0 0
T8 98198 48268 0 0
T9 10632 0 0 0
T10 227312 0 0 0
T16 483713 481877 0 0
T17 0 210971 0 0
T32 77432 27907 0 0
T33 0 14389 0 0
T38 7237 0 0 0
T47 0 19597 0 0
T50 0 24405 0 0
T53 0 811145 0 0
T54 0 410751 0 0
T55 1236 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 241677833 0 0
T1 86601 86531 0 0
T2 236951 236853 0 0
T3 12372 12292 0 0
T4 11503 11432 0 0
T5 81112 81044 0 0
T6 824071 822674 0 0
T7 1599 1506 0 0
T8 98198 98100 0 0
T9 10632 10578 0 0
T10 227312 227216 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 241677833 0 0
T1 86601 86531 0 0
T2 236951 236853 0 0
T3 12372 12292 0 0
T4 11503 11432 0 0
T5 81112 81044 0 0
T6 824071 822674 0 0
T7 1599 1506 0 0
T8 98198 98100 0 0
T9 10632 10578 0 0
T10 227312 227216 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 241677833 0 0
T1 86601 86531 0 0
T2 236951 236853 0 0
T3 12372 12292 0 0
T4 11503 11432 0 0
T5 81112 81044 0 0
T6 824071 822674 0 0
T7 1599 1506 0 0
T8 98198 98100 0 0
T9 10632 10578 0 0
T10 227312 227216 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 114599649 0 0
T5 81112 74857 0 0
T6 824071 0 0 0
T7 1599 0 0 0
T8 98198 48268 0 0
T9 10632 0 0 0
T10 227312 0 0 0
T16 483713 481877 0 0
T17 0 210971 0 0
T32 77432 27907 0 0
T33 0 14389 0 0
T38 7237 0 0 0
T47 0 19597 0 0
T50 0 24405 0 0
T53 0 811145 0 0
T54 0 410751 0 0
T55 1236 0 0 0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf
TotalCoveredPercent
Conditions242083.33
Logical242083.33
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT2,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT15,T18,T19
101CoveredT2,T3,T4
110Not Covered
111CoveredT2,T4,T6

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT1,T2,T3
11CoveredT2,T3,T4

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT2,T3,T4
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T4


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 241813649 94097077 0 0
DepthKnown_A 241813649 241677833 0 0
RvalidKnown_A 241813649 241677833 0 0
WreadyKnown_A 241813649 241677833 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 241813649 94097077 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 94097077 0 0
T2 236951 230353 0 0
T3 12372 10292 0 0
T4 11503 9981 0 0
T5 81112 0 0 0
T6 824071 796269 0 0
T7 1599 0 0 0
T8 98198 0 0 0
T9 10632 8819 0 0
T10 227312 207526 0 0
T14 0 177754 0 0
T16 483713 0 0 0
T23 0 32539 0 0
T38 0 944 0 0
T72 0 20504 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 241677833 0 0
T1 86601 86531 0 0
T2 236951 236853 0 0
T3 12372 12292 0 0
T4 11503 11432 0 0
T5 81112 81044 0 0
T6 824071 822674 0 0
T7 1599 1506 0 0
T8 98198 98100 0 0
T9 10632 10578 0 0
T10 227312 227216 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 241677833 0 0
T1 86601 86531 0 0
T2 236951 236853 0 0
T3 12372 12292 0 0
T4 11503 11432 0 0
T5 81112 81044 0 0
T6 824071 822674 0 0
T7 1599 1506 0 0
T8 98198 98100 0 0
T9 10632 10578 0 0
T10 227312 227216 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 241677833 0 0
T1 86601 86531 0 0
T2 236951 236853 0 0
T3 12372 12292 0 0
T4 11503 11432 0 0
T5 81112 81044 0 0
T6 824071 822674 0 0
T7 1599 1506 0 0
T8 98198 98100 0 0
T9 10632 10578 0 0
T10 227312 227216 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 94097077 0 0
T2 236951 230353 0 0
T3 12372 10292 0 0
T4 11503 9981 0 0
T5 81112 0 0 0
T6 824071 796269 0 0
T7 1599 0 0 0
T8 98198 0 0 0
T9 10632 8819 0 0
T10 227312 207526 0 0
T14 0 177754 0 0
T16 483713 0 0 0
T23 0 32539 0 0
T38 0 944 0 0
T72 0 20504 0 0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf
TotalCoveredPercent
Conditions242083.33
Logical242083.33
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T5,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T5,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T5,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT78,T79
101CoveredT1,T5,T8
110Not Covered
111CoveredT1,T5,T8

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T5,T8

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT1,T5,T8
10CoveredT1,T2,T3
11CoveredT1,T5,T8

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT1,T5,T8
10CoveredT1,T5,T8
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T5,T8
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T5,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T5,T8


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T5,T8
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 241813649 97663041 0 0
DepthKnown_A 241813649 241677833 0 0
RvalidKnown_A 241813649 241677833 0 0
WreadyKnown_A 241813649 241677833 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 241813649 97663041 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 97663041 0 0
T1 86601 83364 0 0
T2 236951 0 0 0
T3 12372 0 0 0
T4 11503 0 0 0
T5 81112 4885 0 0
T6 824071 0 0 0
T7 1599 0 0 0
T8 98198 48742 0 0
T9 10632 0 0 0
T10 227312 0 0 0
T16 0 311703 0 0
T17 0 131572 0 0
T32 0 37210 0 0
T33 0 39702 0 0
T47 0 23322 0 0
T50 0 20879 0 0
T53 0 792080 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 241677833 0 0
T1 86601 86531 0 0
T2 236951 236853 0 0
T3 12372 12292 0 0
T4 11503 11432 0 0
T5 81112 81044 0 0
T6 824071 822674 0 0
T7 1599 1506 0 0
T8 98198 98100 0 0
T9 10632 10578 0 0
T10 227312 227216 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 241677833 0 0
T1 86601 86531 0 0
T2 236951 236853 0 0
T3 12372 12292 0 0
T4 11503 11432 0 0
T5 81112 81044 0 0
T6 824071 822674 0 0
T7 1599 1506 0 0
T8 98198 98100 0 0
T9 10632 10578 0 0
T10 227312 227216 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 241677833 0 0
T1 86601 86531 0 0
T2 236951 236853 0 0
T3 12372 12292 0 0
T4 11503 11432 0 0
T5 81112 81044 0 0
T6 824071 822674 0 0
T7 1599 1506 0 0
T8 98198 98100 0 0
T9 10632 10578 0 0
T10 227312 227216 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 241813649 97663041 0 0
T1 86601 83364 0 0
T2 236951 0 0 0
T3 12372 0 0 0
T4 11503 0 0 0
T5 81112 4885 0 0
T6 824071 0 0 0
T7 1599 0 0 0
T8 98198 48742 0 0
T9 10632 0 0 0
T10 227312 0 0 0
T16 0 311703 0 0
T17 0 131572 0 0
T32 0 37210 0 0
T33 0 39702 0 0
T47 0 23322 0 0
T50 0 20879 0 0
T53 0 792080 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%