Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

117591

1

T4

142

T7

94

T8

1152

ack

9558

1

T4

17

T7

1

T8

36

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	495	1			T8	8		T23	5		T28	2
high	26208	1			T4	51		T7	16		T8	252
med	47305	1			T4	46		T7	44		T8	451
sml	52631	1			T4	60		T7	32		T8	472
all_zero	510	1			T4	2		T7	3		T8	5

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

63321

1

T4

83

T7

35

T8

588

auto[1]

63828

1

T4

76

T7

60

T8

600

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

86547

1

T4

112

T7

64

T8

826

auto[1]

40602

1

T4

47

T7

31

T8

362

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

121849

1

T4

159

T7

95

T8

1171

auto[1]

5300

1

T8

17

T9

1

T23

10

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

121032

1

T4

142

T7

94

T8

1153

auto[1]

6117

1

T4

17

T7

1

T8

35

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

121639

1

T4

142

T7

94

T8

1154

auto[1]

5510

1

T4

17

T7

1

T8

34

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

63321

1

T4

83

T7

35

T8

588

auto[1]

63828

1

T4

76

T7

60

T8

600

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

86547

1

T4

112

T7

64

T8

826

auto[1]

40602

1

T4

47

T7

31

T8

362

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

121849

1

T4

159

T7

95

T8

1171

auto[1]

5300

1

T8

17

T9

1

T23

10

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

121032

1

T4

142

T7

94

T8

1153

auto[1]

6117

1

T4

17

T7

1

T8

35

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

121639

1

T4

142

T7

94

T8

1154

auto[1]

5510

1

T4

17

T7

1

T8

34

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

2

1

T225

1

T226

1

-

-

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

1

1

T227

1

-

-

-

-

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

1

1

T228

1

-

-

-

-

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

160

1

T8

2

T23

2

T35

2

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

57

1

T23

1

T20

1

T98

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

77

1

T8

1

T23

2

T35

2

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

284

1

T8

4

T23

3

T28

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

161

1

T8

3

T20

2

T98

2

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

141

1

T23

2

T28

1

T35

1

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

291

1

T8

8

T23

2

T28

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

165

1

T8

1

T35

4

T20

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

126

1

T8

2

T23

2

T28

1

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

2

1

T25

1

T229

1

-

-

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

1

1

T230

1

-

-

-

-

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

1

1

T57

1

-

-

-

-

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	37664	1			T4	39		T7	22		T8	365
write_address_byte	6117	1			T4	17		T7	1		T8	35
read_with_ack	1857	1			T28	3		T46	16		T11	9
read_with_nack	3443	1			T8	17		T9	1		T23	10
stop_byte	5510	1			T4	17		T7	1		T8	34
write_address_byte_nak	2660	1			T8	32		T23	18		T28	5
data_byte_nack	117591	1			T4	142		T7	94		T8	1152
stop_byte_nack	3159	1			T4	17		T7	1		T8	31
nakok_byte_nack	59091	1			T4	67		T7	59		T8	580
nakok_addr_byte_nack	1329	1			T8	13		T23	10		T28	2