Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26499462	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5805825

1

T1

13

T2

131

T3

580

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	31653546	1			T1	18		T2	366		T3	970
values[0x0]	325654	1			T1	10		T2	65		T3	568
values[0x1]	326087	1			T1	8		T2	76		T3	631

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	18811791	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

13493496

1

T1

15

T2

255

T3

965

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	121320	1			T2	2		T3	12		T4	20
valid_sources[0x01]	123242	1			T3	9		T6	4		T7	8
valid_sources[0x02]	117088	1			T2	1		T3	8		T4	1
valid_sources[0x03]	111333	1			T3	6		T4	17		T7	11
valid_sources[0x04]	111605	1			T2	1		T3	9		T4	5
valid_sources[0x05]	110313	1			T1	1		T2	4		T3	12
valid_sources[0x06]	249588	1			T2	4		T3	11		T4	27
valid_sources[0x07]	117865	1			T2	4		T3	16		T4	2
valid_sources[0x08]	99990	1			T2	1		T3	16		T4	9
valid_sources[0x09]	114149	1			T3	19		T4	3		T7	15
valid_sources[0x0a]	118629	1			T2	2		T3	3		T4	4
valid_sources[0x0b]	117053	1			T2	4		T3	7		T4	3
valid_sources[0x0c]	111247	1			T2	1		T3	1		T4	20
valid_sources[0x0d]	105196	1			T2	2		T3	5		T4	15
valid_sources[0x0e]	130277	1			T2	2		T3	17		T4	2
valid_sources[0x0f]	109351	1			T2	4		T3	16		T4	17
valid_sources[0x10]	113267	1			T2	1		T3	2		T4	8
valid_sources[0x11]	144782	1			T2	3		T3	3		T4	6
valid_sources[0x12]	116453	1			T2	2		T3	8		T4	5
valid_sources[0x13]	104754	1			T2	3		T3	12		T4	16
valid_sources[0x14]	110335	1			T2	2		T3	9		T4	9
valid_sources[0x15]	115866	1			T3	8		T6	1		T7	4
valid_sources[0x16]	112419	1			T3	14		T4	11		T6	2
valid_sources[0x17]	103904	1			T3	11		T6	2		T7	9
valid_sources[0x18]	277344	1			T2	1		T3	8		T4	8
valid_sources[0x19]	109820	1			T2	2		T3	9		T4	16
valid_sources[0x1a]	110550	1			T2	1		T3	11		T4	36
valid_sources[0x1b]	138473	1			T2	1		T3	13		T4	11
valid_sources[0x1c]	130938	1			T2	2		T3	6		T4	1
valid_sources[0x1d]	120673	1			T1	1		T2	2		T3	6
valid_sources[0x1e]	122004	1			T2	1		T3	2		T4	17
valid_sources[0x1f]	108229	1			T1	1		T2	1		T3	10
valid_sources[0x20]	107595	1			T2	3		T3	4		T4	7
valid_sources[0x21]	138586	1			T2	3		T3	1		T4	7
valid_sources[0x22]	120016	1			T2	2		T3	3		T4	13
valid_sources[0x23]	106445	1			T2	2		T3	2		T4	8
valid_sources[0x24]	120068	1			T2	3		T3	14		T4	28
valid_sources[0x25]	107927	1			T2	3		T3	9		T4	28
valid_sources[0x26]	112804	1			T2	2		T3	6		T6	1
valid_sources[0x27]	116128	1			T2	3		T3	7		T4	9
valid_sources[0x28]	112008	1			T2	3		T3	7		T4	10
valid_sources[0x29]	126825	1			T2	2		T3	4		T4	14
valid_sources[0x2a]	106998	1			T2	5		T3	7		T4	20
valid_sources[0x2b]	119690	1			T2	3		T3	12		T4	10
valid_sources[0x2c]	118479	1			T2	3		T3	13		T4	9
valid_sources[0x2d]	110375	1			T2	3		T3	6		T4	12
valid_sources[0x2e]	109433	1			T3	8		T4	12		T7	18
valid_sources[0x2f]	110552	1			T1	1		T2	2		T3	12
valid_sources[0x30]	116229	1			T2	1		T3	7		T4	4
valid_sources[0x31]	109741	1			T2	1		T3	5		T4	8
valid_sources[0x32]	113924	1			T2	4		T3	13		T4	11
valid_sources[0x33]	111478	1			T2	4		T3	6		T4	4
valid_sources[0x34]	106528	1			T2	3		T3	4		T4	15
valid_sources[0x35]	115786	1			T2	2		T3	4		T4	14
valid_sources[0x36]	103813	1			T2	2		T3	9		T4	6
valid_sources[0x37]	104653	1			T1	3		T3	10		T4	14
valid_sources[0x38]	122922	1			T2	3		T3	7		T4	4
valid_sources[0x39]	106363	1			T2	1		T3	15		T4	15
valid_sources[0x3a]	113826	1			T2	3		T3	12		T4	4
valid_sources[0x3b]	138191	1			T2	2		T3	5		T4	2
valid_sources[0x3c]	111630	1			T2	2		T3	15		T4	65
valid_sources[0x3d]	118181	1			T2	1		T3	4		T4	4
valid_sources[0x3e]	110603	1			T2	4		T3	5		T4	2
valid_sources[0x3f]	115379	1			T2	3		T3	6		T4	19
valid_sources[0x40]	172083	1			T2	1		T3	11		T4	16
valid_sources[0x41]	219009	1			T2	4		T3	7		T4	8
valid_sources[0x42]	126624	1			T2	1		T3	12		T4	5
valid_sources[0x43]	115345	1			T3	3		T4	17		T7	3
valid_sources[0x44]	115728	1			T1	2		T3	9		T4	28
valid_sources[0x45]	112746	1			T2	3		T3	18		T4	13
valid_sources[0x46]	104030	1			T2	1		T3	13		T4	3
valid_sources[0x47]	265371	1			T2	1		T3	25		T4	1
valid_sources[0x48]	119484	1			T2	1		T3	2		T4	23
valid_sources[0x49]	103039	1			T3	4		T4	7		T7	17
valid_sources[0x4a]	108351	1			T3	7		T4	7		T7	11
valid_sources[0x4b]	120715	1			T2	4		T3	8		T4	5
valid_sources[0x4c]	106946	1			T2	1		T3	7		T4	7
valid_sources[0x4d]	109257	1			T2	5		T4	9		T7	4
valid_sources[0x4e]	109853	1			T2	2		T3	8		T4	6
valid_sources[0x4f]	114701	1			T2	1		T3	10		T6	1
valid_sources[0x50]	113132	1			T2	4		T3	11		T4	6
valid_sources[0x51]	118608	1			T2	5		T3	11		T4	11
valid_sources[0x52]	122513	1			T2	3		T3	6		T4	1
valid_sources[0x53]	125666	1			T2	2		T3	7		T4	11
valid_sources[0x54]	128469	1			T1	1		T2	1		T3	12
valid_sources[0x55]	162512	1			T3	3		T4	18		T6	1
valid_sources[0x56]	107697	1			T2	3		T3	16		T4	1
valid_sources[0x57]	108330	1			T3	20		T4	2		T6	1
valid_sources[0x58]	190124	1			T3	7		T4	26		T6	1
valid_sources[0x59]	114247	1			T2	2		T3	16		T4	27
valid_sources[0x5a]	122419	1			T2	3		T3	13		T4	12
valid_sources[0x5b]	115913	1			T2	4		T3	3		T4	6
valid_sources[0x5c]	187015	1			T2	2		T3	2		T4	6
valid_sources[0x5d]	116311	1			T2	2		T3	11		T4	16
valid_sources[0x5e]	113104	1			T2	1		T3	5		T4	7
valid_sources[0x5f]	117584	1			T2	3		T3	9		T4	8
valid_sources[0x60]	112266	1			T2	1		T3	13		T6	1
valid_sources[0x61]	117645	1			T2	1		T3	7		T4	2
valid_sources[0x62]	113196	1			T1	1		T2	2		T3	6
valid_sources[0x63]	109680	1			T3	13		T4	21		T6	1
valid_sources[0x64]	114292	1			T2	3		T3	9		T4	3
valid_sources[0x65]	107149	1			T2	1		T3	6		T4	4
valid_sources[0x66]	104908	1			T1	1		T2	2		T3	6
valid_sources[0x67]	110654	1			T2	4		T3	27		T4	35
valid_sources[0x68]	112426	1			T2	3		T3	4		T4	7
valid_sources[0x69]	121048	1			T2	3		T3	4		T4	22
valid_sources[0x6a]	106378	1			T2	3		T3	8		T7	10
valid_sources[0x6b]	112935	1			T2	2		T3	5		T4	4
valid_sources[0x6c]	113851	1			T2	2		T3	3		T4	13
valid_sources[0x6d]	125879	1			T2	5		T3	16		T4	11
valid_sources[0x6e]	110819	1			T2	1		T3	6		T4	2
valid_sources[0x6f]	251328	1			T2	4		T3	23		T4	1
valid_sources[0x70]	115779	1			T1	4		T2	3		T3	2
valid_sources[0x71]	108620	1			T2	1		T3	5		T6	2
valid_sources[0x72]	112763	1			T3	4		T4	34		T6	1
valid_sources[0x73]	127294	1			T3	6		T4	1		T6	1
valid_sources[0x74]	108717	1			T2	6		T3	11		T4	7
valid_sources[0x75]	126412	1			T2	2		T3	4		T4	15
valid_sources[0x76]	112153	1			T2	5		T3	6		T4	3
valid_sources[0x77]	112431	1			T2	3		T3	4		T4	10
valid_sources[0x78]	110328	1			T2	1		T3	10		T4	14
valid_sources[0x79]	110368	1			T2	5		T3	10		T4	19
valid_sources[0x7a]	102302	1			T3	9		T4	7		T7	12
valid_sources[0x7b]	123831	1			T2	5		T3	8		T4	16
valid_sources[0x7c]	119825	1			T2	3		T3	12		T4	11
valid_sources[0x7d]	110771	1			T3	2		T4	11		T7	8
valid_sources[0x7e]	114553	1			T2	2		T3	12		T4	15
valid_sources[0x7f]	106051	1			T2	2		T3	5		T4	29
valid_sources[0x80]	118511	1			T2	2		T3	7		T4	18

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5523788

1

T1

9

T2

68

T3

248

values[0x0]

all_enables

biggest_size

166965

1

T1

3

T2

35

T3

228

values[0x1]

all_enables

biggest_size

115072

1

T1

1

T2

28

T3

104