Unified Coverage Report :: Module :: i2c_reg_top

Module : i2c_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.75	100.00	99.01			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	99.75	100.00	99.01			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.75	100.00	99.01			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.90	98.67	98.17	100.00		97.66	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.72	100.00	100.00	94.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_acqdata_abyte	100.00	100.00
u_acqdata_signal	100.00	100.00
u_alert_test	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_ctrl0_qe	100.00	100.00				100.00
u_ctrl_enablehost	96.30	100.00	88.89			100.00
u_ctrl_enabletarget	96.30	100.00	88.89			100.00
u_ctrl_llpbk	96.30	100.00	88.89			100.00
u_fdata0_qe	100.00	100.00				100.00
u_fdata_fbyte	100.00	100.00	100.00			100.00
u_fdata_nakok	100.00	100.00	100.00			100.00
u_fdata_rcont	100.00	100.00	100.00			100.00
u_fdata_readb	100.00	100.00	100.00			100.00
u_fdata_start	100.00	100.00	100.00			100.00
u_fdata_stop	100.00	100.00	100.00			100.00
u_fifo_ctrl0_qe	100.00	100.00				100.00
u_fifo_ctrl_acqrst	100.00	100.00	100.00			100.00
u_fifo_ctrl_fmtrst	100.00	100.00	100.00			100.00
u_fifo_ctrl_rxrst	100.00	100.00	100.00			100.00
u_fifo_ctrl_txrst	100.00	100.00	100.00			100.00
u_host_fifo_config0_qe	100.00	100.00				100.00
u_host_fifo_config_fmt_thresh	100.00	100.00	100.00			100.00
u_host_fifo_config_rx_thresh	100.00	100.00	100.00			100.00
u_host_fifo_status_fmtlvl	100.00	100.00
u_host_fifo_status_rxlvl	100.00	100.00
u_host_nack_handler_timeout_en	100.00	100.00	100.00			100.00
u_host_nack_handler_timeout_val	100.00	100.00	100.00			100.00
u_host_timeout_ctrl	100.00	100.00	100.00			100.00
u_intr_enable_acq_full	100.00	100.00	100.00			100.00
u_intr_enable_acq_threshold	100.00	100.00	100.00			100.00
u_intr_enable_cmd_complete	100.00	100.00	100.00			100.00
u_intr_enable_fmt_threshold	100.00	100.00	100.00			100.00
u_intr_enable_host_timeout	100.00	100.00	100.00			100.00
u_intr_enable_nak	100.00	100.00	100.00			100.00
u_intr_enable_rx_overflow	100.00	100.00	100.00			100.00
u_intr_enable_rx_threshold	100.00	100.00	100.00			100.00
u_intr_enable_scl_interference	100.00	100.00	100.00			100.00
u_intr_enable_sda_interference	100.00	100.00	100.00			100.00
u_intr_enable_sda_unstable	100.00	100.00	100.00			100.00
u_intr_enable_stretch_timeout	100.00	100.00	100.00			100.00
u_intr_enable_tx_stretch	100.00	100.00	100.00			100.00
u_intr_enable_tx_threshold	100.00	100.00	100.00			100.00
u_intr_enable_unexp_stop	100.00	100.00	100.00			100.00
u_intr_state_acq_full	62.59	77.78	50.00			60.00
u_intr_state_acq_threshold	62.59	77.78	50.00			60.00
u_intr_state_cmd_complete	100.00	100.00	100.00			100.00
u_intr_state_fmt_threshold	62.59	77.78	50.00			60.00
u_intr_state_host_timeout	100.00	100.00	100.00			100.00
u_intr_state_nak	100.00	100.00	100.00			100.00
u_intr_state_rx_overflow	100.00	100.00	100.00			100.00
u_intr_state_rx_threshold	62.59	77.78	50.00			60.00
u_intr_state_scl_interference	100.00	100.00	100.00			100.00
u_intr_state_sda_interference	100.00	100.00	100.00			100.00
u_intr_state_sda_unstable	100.00	100.00	100.00			100.00
u_intr_state_stretch_timeout	100.00	100.00	100.00			100.00
u_intr_state_tx_stretch	62.59	77.78	50.00			60.00
u_intr_state_tx_threshold	62.59	77.78	50.00			60.00
u_intr_state_unexp_stop	100.00	100.00	100.00			100.00
u_intr_test_acq_full	100.00	100.00
u_intr_test_acq_threshold	100.00	100.00
u_intr_test_cmd_complete	100.00	100.00
u_intr_test_fmt_threshold	100.00	100.00
u_intr_test_host_timeout	100.00	100.00
u_intr_test_nak	100.00	100.00
u_intr_test_rx_overflow	100.00	100.00
u_intr_test_rx_threshold	100.00	100.00
u_intr_test_scl_interference	100.00	100.00
u_intr_test_sda_interference	100.00	100.00
u_intr_test_sda_unstable	100.00	100.00
u_intr_test_stretch_timeout	100.00	100.00
u_intr_test_tx_stretch	100.00	100.00
u_intr_test_tx_threshold	100.00	100.00
u_intr_test_unexp_stop	100.00	100.00
u_ovrd_sclval	100.00	100.00	100.00			100.00
u_ovrd_sdaval	100.00	100.00	100.00			100.00
u_ovrd_txovrden	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_rdata	100.00	100.00
u_reg_if	98.67	97.14	97.53			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_status_acqempty	100.00	100.00
u_status_acqfull	100.00	100.00
u_status_fmtempty	100.00	100.00
u_status_fmtfull	100.00	100.00
u_status_host_disabled_nack_timeout	100.00	100.00
u_status_hostidle	100.00	100.00
u_status_rxempty	100.00	100.00
u_status_rxfull	100.00	100.00
u_status_targetidle	100.00	100.00
u_status_txempty	100.00	100.00
u_status_txfull	100.00	100.00
u_target_fifo_config0_qe	100.00	100.00				100.00
u_target_fifo_config_acq_thresh	100.00	100.00	100.00			100.00
u_target_fifo_config_tx_thresh	100.00	100.00	100.00			100.00
u_target_fifo_config_txrst_on_cond	100.00	100.00	100.00			100.00
u_target_fifo_status_acqlvl	100.00	100.00
u_target_fifo_status_txlvl	100.00	100.00
u_target_id_address0	100.00	100.00	100.00			100.00
u_target_id_address1	100.00	100.00	100.00			100.00
u_target_id_mask0	100.00	100.00	100.00			100.00
u_target_id_mask1	100.00	100.00	100.00			100.00
u_target_nack_count	81.90	100.00	60.00			85.71
u_target_timeout_ctrl_en	100.00	100.00	100.00			100.00
u_target_timeout_ctrl_val	100.00	100.00	100.00			100.00
u_timeout_ctrl_en	100.00	100.00	100.00			100.00
u_timeout_ctrl_val	100.00	100.00	100.00			100.00
u_timing0_thigh	100.00	100.00	100.00			100.00
u_timing0_tlow	100.00	100.00	100.00			100.00
u_timing1_t_f	100.00	100.00	100.00			100.00
u_timing1_t_r	100.00	100.00	100.00			100.00
u_timing2_thd_sta	100.00	100.00	100.00			100.00
u_timing2_tsu_sta	100.00	100.00	100.00			100.00
u_timing3_thd_dat	100.00	100.00	100.00			100.00
u_timing3_tsu_dat	100.00	100.00	100.00			100.00
u_timing4_t_buf	100.00	100.00	100.00			100.00
u_timing4_tsu_sto	100.00	100.00	100.00			100.00
u_txdata	100.00	100.00	100.00			100.00
u_txdata0_qe	100.00	100.00				100.00
u_val_scl_rx	66.67	66.67
u_val_sda_rx	66.67	66.67

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c_reg_top

	Line No.	Total	Covered	Percent
TOTAL		331	331	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	1138	1	1	100.00
CONT_ASSIGN	1153	1	1	100.00
CONT_ASSIGN	1169	1	1	100.00
CONT_ASSIGN	1185	1	1	100.00
CONT_ASSIGN	1201	1	1	100.00
CONT_ASSIGN	1217	1	1	100.00
CONT_ASSIGN	1233	1	1	100.00
CONT_ASSIGN	1249	1	1	100.00
CONT_ASSIGN	1265	1	1	100.00
CONT_ASSIGN	1281	1	1	100.00
CONT_ASSIGN	1297	1	1	100.00
CONT_ASSIGN	1313	1	1	100.00
CONT_ASSIGN	1329	1	1	100.00
CONT_ASSIGN	1345	1	1	100.00
CONT_ASSIGN	1361	1	1	100.00
CONT_ASSIGN	1377	1	1	100.00
CONT_ASSIGN	1383	1	1	100.00
CONT_ASSIGN	1397	1	1	100.00
CONT_ASSIGN	1438	1	1	100.00
CONT_ASSIGN	1466	1	1	100.00
CONT_ASSIGN	1494	1	1	100.00
CONT_ASSIGN	1718	1	1	100.00
CONT_ASSIGN	1746	1	1	100.00
CONT_ASSIGN	1774	1	1	100.00
CONT_ASSIGN	1802	1	1	100.00
CONT_ASSIGN	1830	1	1	100.00
CONT_ASSIGN	1858	1	1	100.00
CONT_ASSIGN	1899	1	1	100.00
CONT_ASSIGN	1927	1	1	100.00
CONT_ASSIGN	1955	1	1	100.00
CONT_ASSIGN	1983	1	1	100.00
CONT_ASSIGN	2024	1	1	100.00
CONT_ASSIGN	2052	1	1	100.00
CONT_ASSIGN	2093	1	1	100.00
CONT_ASSIGN	2121	1	1	100.00
CONT_ASSIGN	2149	1	1	100.00
CONT_ASSIGN	2846	1	1	100.00
ALWAYS	3020	29	29	100.00
CONT_ASSIGN	3051	1	1	100.00
ALWAYS	3055	1	1	100.00
CONT_ASSIGN	3087	1	1	100.00
CONT_ASSIGN	3089	1	1	100.00
CONT_ASSIGN	3091	1	1	100.00
CONT_ASSIGN	3093	1	1	100.00
CONT_ASSIGN	3095	1	1	100.00
CONT_ASSIGN	3097	1	1	100.00
CONT_ASSIGN	3099	1	1	100.00
CONT_ASSIGN	3101	1	1	100.00
CONT_ASSIGN	3103	1	1	100.00
CONT_ASSIGN	3105	1	1	100.00
CONT_ASSIGN	3106	1	1	100.00
CONT_ASSIGN	3108	1	1	100.00
CONT_ASSIGN	3110	1	1	100.00
CONT_ASSIGN	3112	1	1	100.00
CONT_ASSIGN	3114	1	1	100.00
CONT_ASSIGN	3116	1	1	100.00
CONT_ASSIGN	3118	1	1	100.00
CONT_ASSIGN	3120	1	1	100.00
CONT_ASSIGN	3122	1	1	100.00
CONT_ASSIGN	3124	1	1	100.00
CONT_ASSIGN	3126	1	1	100.00
CONT_ASSIGN	3128	1	1	100.00
CONT_ASSIGN	3130	1	1	100.00
CONT_ASSIGN	3132	1	1	100.00
CONT_ASSIGN	3134	1	1	100.00
CONT_ASSIGN	3136	1	1	100.00
CONT_ASSIGN	3137	1	1	100.00
CONT_ASSIGN	3139	1	1	100.00
CONT_ASSIGN	3141	1	1	100.00
CONT_ASSIGN	3143	1	1	100.00
CONT_ASSIGN	3145	1	1	100.00
CONT_ASSIGN	3147	1	1	100.00
CONT_ASSIGN	3149	1	1	100.00
CONT_ASSIGN	3151	1	1	100.00
CONT_ASSIGN	3153	1	1	100.00
CONT_ASSIGN	3155	1	1	100.00
CONT_ASSIGN	3157	1	1	100.00
CONT_ASSIGN	3159	1	1	100.00
CONT_ASSIGN	3161	1	1	100.00
CONT_ASSIGN	3163	1	1	100.00
CONT_ASSIGN	3165	1	1	100.00
CONT_ASSIGN	3167	1	1	100.00
CONT_ASSIGN	3168	1	1	100.00
CONT_ASSIGN	3170	1	1	100.00
CONT_ASSIGN	3171	1	1	100.00
CONT_ASSIGN	3173	1	1	100.00
CONT_ASSIGN	3175	1	1	100.00
CONT_ASSIGN	3177	1	1	100.00
CONT_ASSIGN	3178	1	1	100.00
CONT_ASSIGN	3179	1	1	100.00
CONT_ASSIGN	3180	1	1	100.00
CONT_ASSIGN	3182	1	1	100.00
CONT_ASSIGN	3184	1	1	100.00
CONT_ASSIGN	3186	1	1	100.00
CONT_ASSIGN	3188	1	1	100.00
CONT_ASSIGN	3190	1	1	100.00
CONT_ASSIGN	3192	1	1	100.00
CONT_ASSIGN	3193	1	1	100.00
CONT_ASSIGN	3195	1	1	100.00
CONT_ASSIGN	3197	1	1	100.00
CONT_ASSIGN	3199	1	1	100.00
CONT_ASSIGN	3201	1	1	100.00
CONT_ASSIGN	3202	1	1	100.00
CONT_ASSIGN	3204	1	1	100.00
CONT_ASSIGN	3206	1	1	100.00
CONT_ASSIGN	3207	1	1	100.00
CONT_ASSIGN	3209	1	1	100.00
CONT_ASSIGN	3211	1	1	100.00
CONT_ASSIGN	3213	1	1	100.00
CONT_ASSIGN	3214	1	1	100.00
CONT_ASSIGN	3215	1	1	100.00
CONT_ASSIGN	3216	1	1	100.00
CONT_ASSIGN	3218	1	1	100.00
CONT_ASSIGN	3220	1	1	100.00
CONT_ASSIGN	3222	1	1	100.00
CONT_ASSIGN	3223	1	1	100.00
CONT_ASSIGN	3224	1	1	100.00
CONT_ASSIGN	3226	1	1	100.00
CONT_ASSIGN	3228	1	1	100.00
CONT_ASSIGN	3229	1	1	100.00
CONT_ASSIGN	3231	1	1	100.00
CONT_ASSIGN	3233	1	1	100.00
CONT_ASSIGN	3234	1	1	100.00
CONT_ASSIGN	3236	1	1	100.00
CONT_ASSIGN	3238	1	1	100.00
CONT_ASSIGN	3239	1	1	100.00
CONT_ASSIGN	3241	1	1	100.00
CONT_ASSIGN	3243	1	1	100.00
CONT_ASSIGN	3244	1	1	100.00
CONT_ASSIGN	3246	1	1	100.00
CONT_ASSIGN	3248	1	1	100.00
CONT_ASSIGN	3249	1	1	100.00
CONT_ASSIGN	3251	1	1	100.00
CONT_ASSIGN	3253	1	1	100.00
CONT_ASSIGN	3254	1	1	100.00
CONT_ASSIGN	3256	1	1	100.00
CONT_ASSIGN	3258	1	1	100.00
CONT_ASSIGN	3260	1	1	100.00
CONT_ASSIGN	3262	1	1	100.00
CONT_ASSIGN	3263	1	1	100.00
CONT_ASSIGN	3264	1	1	100.00
CONT_ASSIGN	3266	1	1	100.00
CONT_ASSIGN	3267	1	1	100.00
CONT_ASSIGN	3269	1	1	100.00
CONT_ASSIGN	3270	1	1	100.00
CONT_ASSIGN	3272	1	1	100.00
CONT_ASSIGN	3274	1	1	100.00
CONT_ASSIGN	3275	1	1	100.00
CONT_ASSIGN	3278	1	1	100.00
CONT_ASSIGN	3280	1	1	100.00
CONT_ASSIGN	3282	1	1	100.00
ALWAYS	3286	29	29	100.00
ALWAYS	3319	112	112	100.00
CONT_ASSIGN	3526	0	0
CONT_ASSIGN	3534	1	1	100.00
CONT_ASSIGN	3535	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
77	1	1
89	1	1
90	1	1
118	1	1
119	1	1
1138	1	1
1153	1	1
1169	1	1
1185	1	1
1201	1	1
1217	1	1
1233	1	1
1249	1	1
1265	1	1
1281	1	1
1297	1	1
1313	1	1
1329	1	1
1345	1	1
1361	1	1
1377	1	1
1383	1	1
1397	1	1
1438	1	1
1466	1	1
1494	1	1
1718	1	1
1746	1	1
1774	1	1
1802	1	1
1830	1	1
1858	1	1
1899	1	1
1927	1	1
1955	1	1
1983	1	1
2024	1	1
2052	1	1
2093	1	1
2121	1	1
2149	1	1
2846	1	1
3020	1	1
3021	1	1
3022	1	1
3023	1	1
3024	1	1
3025	1	1
3026	1	1
3027	1	1
3028	1	1
3029	1	1
3030	1	1
3031	1	1
3032	1	1
3033	1	1
3034	1	1
3035	1	1
3036	1	1
3037	1	1
3038	1	1
3039	1	1
3040	1	1
3041	1	1
3042	1	1
3043	1	1
3044	1	1
3045	1	1
3046	1	1
3047	1	1
3048	1	1
3051	1	1
3055	1	1
3087	1	1
3089	1	1
3091	1	1
3093	1	1
3095	1	1
3097	1	1
3099	1	1
3101	1	1
3103	1	1
3105	1	1
3106	1	1
3108	1	1
3110	1	1
3112	1	1
3114	1	1
3116	1	1
3118	1	1
3120	1	1
3122	1	1
3124	1	1
3126	1	1
3128	1	1
3130	1	1
3132	1	1
3134	1	1
3136	1	1
3137	1	1
3139	1	1
3141	1	1
3143	1	1
3145	1	1
3147	1	1
3149	1	1
3151	1	1
3153	1	1
3155	1	1
3157	1	1
3159	1	1
3161	1	1
3163	1	1
3165	1	1
3167	1	1
3168	1	1
3170	1	1
3171	1	1
3173	1	1
3175	1	1
3177	1	1
3178	1	1
3179	1	1
3180	1	1
3182	1	1
3184	1	1
3186	1	1
3188	1	1
3190	1	1
3192	1	1
3193	1	1
3195	1	1
3197	1	1
3199	1	1
3201	1	1
3202	1	1
3204	1	1
3206	1	1
3207	1	1
3209	1	1
3211	1	1
3213	1	1
3214	1	1
3215	1	1
3216	1	1
3218	1	1
3220	1	1
3222	1	1
3223	1	1
3224	1	1
3226	1	1
3228	1	1
3229	1	1
3231	1	1
3233	1	1
3234	1	1
3236	1	1
3238	1	1
3239	1	1
3241	1	1
3243	1	1
3244	1	1
3246	1	1
3248	1	1
3249	1	1
3251	1	1
3253	1	1
3254	1	1
3256	1	1
3258	1	1
3260	1	1
3262	1	1
3263	1	1
3264	1	1
3266	1	1
3267	1	1
3269	1	1
3270	1	1
3272	1	1
3274	1	1
3275	1	1
3278	1	1
3280	1	1
3282	1	1
3286	1	1
3287	1	1
3288	1	1
3289	1	1
3290	1	1
3291	1	1
3292	1	1
3293	1	1
3294	1	1
3295	1	1
3296	1	1
3297	1	1
3298	1	1
3299	1	1
3300	1	1
3301	1	1
3302	1	1
3303	1	1
3304	1	1
3305	1	1
3306	1	1
3307	1	1
3308	1	1
3309	1	1
3310	1	1
3311	1	1
3312	1	1
3313	1	1
3314	1	1
3319	1	1
3320	1	1
3322	1	1
3323	1	1
3324	1	1
3325	1	1
3326	1	1
3327	1	1
3328	1	1
3329	1	1
3330	1	1
3331	1	1
3332	1	1
3333	1	1
3334	1	1
3335	1	1
3336	1	1
3340	1	1
3341	1	1
3342	1	1
3343	1	1
3344	1	1
3345	1	1
3346	1	1
3347	1	1
3348	1	1
3349	1	1
3350	1	1
3351	1	1
3352	1	1
3353	1	1
3354	1	1
3358	1	1
3359	1	1
3360	1	1
3361	1	1
3362	1	1
3363	1	1
3364	1	1
3365	1	1
3366	1	1
3367	1	1
3368	1	1
3369	1	1
3370	1	1
3371	1	1
3372	1	1
3376	1	1
3380	1	1
3381	1	1
3382	1	1
3386	1	1
3387	1	1
3388	1	1
3389	1	1
3390	1	1
3391	1	1
3392	1	1
3393	1	1
3394	1	1
3395	1	1
3396	1	1
3400	1	1
3404	1	1
3405	1	1
3406	1	1
3407	1	1
3408	1	1
3409	1	1
3413	1	1
3414	1	1
3415	1	1
3416	1	1
3420	1	1
3421	1	1
3425	1	1
3426	1	1
3427	1	1
3431	1	1
3432	1	1
3436	1	1
3437	1	1
3441	1	1
3442	1	1
3443	1	1
3447	1	1
3448	1	1
3452	1	1
3453	1	1
3457	1	1
3458	1	1
3462	1	1
3463	1	1
3467	1	1
3468	1	1
3472	1	1
3473	1	1
3477	1	1
3478	1	1
3482	1	1
3483	1	1
3484	1	1
3485	1	1
3489	1	1
3490	1	1
3494	1	1
3498	1	1
3502	1	1
3503	1	1
3507	1	1
3511	1	1
3512	1	1
3526		unreachable
3534	1	1
3535	1	1

---

Cond Coverage for Module : i2c_reg_top

	Total	Covered	Percent
Conditions	303	300	99.01
Logical	303	300	99.01
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T78,T105,T120
1	1	Covered	T1,T2,T3

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T106,T107,T108
1	0	Covered	T120,T121,T122

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T106,T107,T108
0	1	0	Covered	T120,T121,T122
1	0	0	Covered	T106,T107,T108

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T120,T121,T122
0	1	0	Covered	T104,T78,T105
1	0	0	Covered	T104,T78,T105

 LINE       3021
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_INTR_STATE_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3022
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_INTR_ENABLE_OFFSET)
            ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3023
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_INTR_TEST_OFFSET)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       3024
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_ALERT_TEST_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3025
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_CTRL_OFFSET)
            ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3026
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_STATUS_OFFSET)
            ----------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       3027
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_RDATA_OFFSET)
            ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       3028
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_FDATA_OFFSET)
            ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3029
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_FIFO_CTRL_OFFSET)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3030
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_HOST_FIFO_CONFIG_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3031
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_FIFO_CONFIG_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3032
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_HOST_FIFO_STATUS_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3033
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_FIFO_STATUS_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3034
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_OVRD_OFFSET)
            ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3035
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_VAL_OFFSET)
            --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3036
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING0_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3037
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING1_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       3038
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING2_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3039
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING3_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3040
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING4_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3041
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMEOUT_CTRL_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3042
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_ID_OFFSET)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3043
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_ACQDATA_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       3044
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TXDATA_OFFSET)
            ----------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3045
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_HOST_TIMEOUT_CTRL_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       3046
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_TIMEOUT_CTRL_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3047
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_NACK_COUNT_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3048
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_HOST_NACK_HANDLER_TIMEOUT_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3051
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3051
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       3055
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[2] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[8] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T104,T78,T105

 LINE       3055
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b0011 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b0011 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b0011 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b0011 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1111 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T1,T2,T3
28 (addr_hit[27] & ((|(4'...	Covered	T1,T2,T3
27 (addr_hit[26] & ((|(4'...	Covered	T2,T3,T5
26 (addr_hit[25] & ((|(4'...	Covered	T1,T2,T3
25 (addr_hit[24] & ((|(4'...	Covered	T2,T3,T5
24 (addr_hit[23] & ((|(4'...	Covered	T2,T3,T5
23 (addr_hit[22] & ((|(4'...	Covered	T2,T3,T5
22 (addr_hit[21] & ((|(4'...	Covered	T1,T2,T3
21 (addr_hit[20] & ((|(4'...	Covered	T2,T3,T5
20 (addr_hit[19] & ((|(4'...	Covered	T1,T2,T3
19 (addr_hit[18] & ((|(4'...	Covered	T1,T2,T3
18 (addr_hit[17] & ((|(4'...	Covered	T1,T2,T3
17 (addr_hit[16] & ((|(4'...	Covered	T2,T3,T5
16 (addr_hit[15] & ((|(4'...	Covered	T1,T2,T3
15 (addr_hit[14] & ((|(4'...	Covered	T1,T2,T3
14 (addr_hit[13] & ((|(4'...	Covered	T1,T2,T3
13 (addr_hit[12] & ((|(4'...	Covered	T1,T2,T3
12 (addr_hit[11] & ((|(4'...	Covered	T1,T2,T3
11 (addr_hit[10] & ((|(4'...	Covered	T1,T2,T3
10 (addr_hit[9] & ((|(4'b...	Covered	T1,T2,T3
9 (addr_hit[8] & ((|(4'b...	Covered	T1,T2,T3
8 (addr_hit[7] & ((|(4'b...	Covered	T1,T2,T3
7 (addr_hit[6] & ((|(4'b...	Covered	T2,T3,T5
6 (addr_hit[5] & ((|(4'b...	Covered	T2,T3,T4
5 (addr_hit[4] & ((|(4'b...	Covered	T1,T2,T3
4 (addr_hit[3] & ((|(4'b...	Covered	T1,T2,T3
3 (addr_hit[2] & ((|(4'b...	Covered	T2,T3,T5
2 (addr_hit[1] & ((|(4'b...	Covered	T2,T3,T5
1 (addr_hit[0] & ((|(4'b...	Covered	T1,T2,T3

 LINE       3055
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       3055
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       3055
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T5

 LINE       3055
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       3055
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       3055
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       3055
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T5

 LINE       3055
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       3055
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       3055
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       3055
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       3055
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T2,T3

 LINE       3055
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T14
1	1	Covered	T1,T2,T3

 LINE       3055
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       3055
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T14
1	1	Covered	T1,T2,T3

 LINE       3055
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       3055
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T5

 LINE       3055
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       3055
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       3055
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       3055
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       3055
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       3055
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T5

 LINE       3055
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       3055
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T5

 LINE       3055
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       3055
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       3055
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       3087
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T123,T124,T125
1	1	1	Covered	T1,T2,T3

 LINE       3106
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T126,T124,T125
1	1	1	Covered	T1,T2,T3

 LINE       3137
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T5
1	1	0	Covered	T104,T123,T124
1	1	1	Covered	T20,T99,T100

 LINE       3168
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T124,T127,T128
1	1	1	Covered	T101,T102,T103

 LINE       3171
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T125,T127,T128
1	1	1	Covered	T1,T2,T3

 LINE       3178
 EXPRESSION (addr_hit[5] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T122,T129,T130
1	1	1	Covered	T2,T3,T4

 LINE       3179
 EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T5
1	1	0	Covered	T129,T131,T132
1	1	1	Covered	T8,T9,T23

 LINE       3180
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T104,T122,T124
1	1	1	Covered	T4,T6,T7

 LINE       3193
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T104,T122,T124
1	1	1	Covered	T1,T2,T3

 LINE       3202
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T126,T124,T127
1	1	1	Covered	T2,T3,T4

 LINE       3207
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T120,T124,T127
1	1	1	Covered	T2,T3,T4

 LINE       3214
 EXPRESSION (addr_hit[11] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T126,T133
1	1	1	Covered	T6,T8,T23

 LINE       3215
 EXPRESSION (addr_hit[12] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T120,T134,T135
1	1	1	Covered	T2,T3,T5

 LINE       3216
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T104,T105,T124
1	1	1	Covered	T1,T29,T51

 LINE       3223
 EXPRESSION (addr_hit[14] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       3224
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T120,T122,T127
1	1	1	Covered	T2,T3,T4

 LINE       3229
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T104,T124,T125
1	1	1	Covered	T2,T3,T4

 LINE       3234
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T104,T78,T124
1	1	1	Covered	T2,T3,T4

 LINE       3239
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T124,T125,T127
1	1	1	Covered	T2,T3,T4

 LINE       3244
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T104,T124,T125
1	1	1	Covered	T2,T3,T4

 LINE       3249
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T120,T122,T124
1	1	1	Covered	T2,T3,T4

 LINE       3254
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T104,T105,T124
1	1	1	Covered	T2,T3,T5

 LINE       3263
 EXPRESSION (addr_hit[22] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T5
1	1	0	Covered	T121,T123,T130
1	1	1	Covered	T2,T3,T5

 LINE       3264
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T104,T78,T124
1	1	1	Covered	T2,T3,T5

 LINE       3267
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T5
1	1	0	Covered	T104,T105,T124
1	1	1	Covered	T2,T3,T5

 LINE       3270
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T104,T124,T127
1	1	1	Covered	T76,T77,T78

 LINE       3275
 EXPRESSION (addr_hit[26] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T76,T77,T78

 LINE       3278
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T104,T105,T124
1	1	1	Covered	T17,T18,T19

---

Branch Coverage for Module : i2c_reg_top

	Line No.	Total	Covered	Percent
Branches		34	34	100.00
TERNARY	3051	2	2	100.00
IF	68	3	3	100.00
CASE	3320	29	29	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	3051	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	68	if ((!rst_ni))
-2-:	70	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T106,T107,T108
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	3320	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T2,T3,T4
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T2,T3,T4
addr_hit[6]	Covered	T2,T3,T4
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T2,T3,T4
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T2,T3,T4
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T2,T3,T4
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : i2c_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	231960925	32297732	0	0
reAfterRv	231960925	32297606	0	0
rePulse	231960925	31651700	0	0
wePulse	231960925	645906	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	231960925	32297732	0	0
T1	1562	36	0	0
T2	52688	507	0	0
T3	249952	2169	0	0
T4	31033	2741	0	0
T5	52787	695	0	0
T6	6987	179	0	0
T7	19236	2393	0	0
T8	381085	189145	0	0
T9	17600	1495	0	0
T10	135697	16611	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	231960925	32297606	0	0
T1	1562	36	0	0
T2	52688	507	0	0
T3	249952	2169	0	0
T4	31033	2741	0	0
T5	52787	695	0	0
T6	6987	179	0	0
T7	19236	2393	0	0
T8	381085	189145	0	0
T9	17600	1495	0	0
T10	135697	16611	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	231960925	31651700	0	0
T1	1562	18	0	0
T2	52688	366	0	0
T3	249952	970	0	0
T4	31033	2472	0	0
T5	52787	528	0	0
T6	6987	91	0	0
T7	19236	2285	0	0
T8	381085	187719	0	0
T9	17600	1447	0	0
T10	135697	16225	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	231960925	645906	0	0
T1	1562	18	0	0
T2	52688	141	0	0
T3	249952	1199	0	0
T4	31033	269	0	0
T5	52787	167	0	0
T6	6987	88	0	0
T7	19236	108	0	0
T8	381085	1426	0	0
T9	17600	48	0	0
T10	135697	386	0	0