Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.72	100.00	100.00	94.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	231960925	8932	0	0
host_fifo_config_rd_A	231960925	6490	0	0
host_nack_handler_timeout_rd_A	231960925	1787	0	0
host_timeout_ctrl_rd_A	231960925	1394	0	0
intr_enable_rd_A	231960925	5969	0	0
ovrd_rd_A	231960925	2656	0	0
target_fifo_config_rd_A	231960925	2259	0	0
target_id_rd_A	231960925	2270	0	0
target_timeout_ctrl_rd_A	231960925	1722	0	0
timeout_ctrl_rd_A	231960925	1701	0	0
timing0_rd_A	231960925	1792	0	0
timing1_rd_A	231960925	1884	0	0
timing2_rd_A	231960925	1599	0	0
timing3_rd_A	231960925	1721	0	0
timing4_rd_A	231960925	1880	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231960925	8932	0	0
T78	1899	32	0	0
T104	7445	226	0	0
T105	6404	499	0	0
T120	12166	6	0	0
T121	6562	2	0	0
T122	13611	1	0	0
T123	7433	1	0	0
T124	11482	625	0	0
T125	4016	225	0	0
T136	1913	3	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231960925	6490	0	0
T14	105188	0	0	0
T23	251611	139	0	0
T28	178277	0	0	0
T32	61327	0	0	0
T35	0	253	0	0
T36	10549	0	0	0
T48	77061	0	0	0
T49	35903	0	0	0
T52	219547	0	0	0
T55	0	620	0	0
T79	360360	0	0	0
T100	0	328	0	0
T101	1699	0	0	0
T160	0	354	0	0
T161	0	115	0	0
T162	0	203	0	0
T163	0	186	0	0
T164	0	130	0	0
T165	0	127	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231960925	1787	0	0
T121	6562	27	0	0
T122	13611	130	0	0
T123	7433	42	0	0
T138	2238	6	0	0
T153	5870	19	0	0
T158	3066	26	0	0
T166	54033	423	0	0
T167	11610	18	0	0
T168	1756	25	0	0
T169	3160	16	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231960925	1394	0	0
T121	6562	21	0	0
T122	13611	80	0	0
T123	7433	30	0	0
T153	5870	24	0	0
T158	3066	5	0	0
T166	54033	454	0	0
T167	11610	4	0	0
T168	1756	8	0	0
T169	3160	15	0	0
T170	1958	10	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231960925	5969	0	0
T88	246296	0	0	0
T100	719897	35	0	0
T121	0	197	0	0
T122	0	756	0	0
T123	0	391	0	0
T153	0	65	0	0
T160	0	11	0	0
T165	0	14	0	0
T166	0	449	0	0
T171	0	4	0	0
T172	0	8	0	0
T173	26446	0	0	0
T174	25353	0	0	0
T175	496545	0	0	0
T176	101273	0	0	0
T177	79580	0	0	0
T178	1089	0	0	0
T179	35448	0	0	0
T180	203452	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231960925	2656	0	0
T1	1562	46	0	0
T2	52688	0	0	0
T3	249952	0	0	0
T4	31033	0	0	0
T5	52787	0	0	0
T6	6987	0	0	0
T7	19236	0	0	0
T8	381085	0	0	0
T9	17600	0	0	0
T10	135697	0	0	0
T29	0	31	0	0
T181	0	68	0	0
T182	0	81	0	0
T183	0	14	0	0
T184	0	39	0	0
T185	0	30	0	0
T186	0	30	0	0
T187	0	22	0	0
T188	0	72	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231960925	2259	0	0
T121	6562	41	0	0
T122	13611	173	0	0
T123	7433	74	0	0
T138	2238	6	0	0
T153	5870	23	0	0
T158	3066	54	0	0
T166	54033	460	0	0
T167	11610	7	0	0
T168	1756	9	0	0
T169	3160	43	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231960925	2270	0	0
T121	6562	68	0	0
T122	13611	246	0	0
T123	7433	104	0	0
T138	2238	7	0	0
T153	5870	11	0	0
T158	3066	19	0	0
T166	54033	438	0	0
T167	11610	7	0	0
T168	1756	6	0	0
T169	3160	16	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231960925	1722	0	0
T121	6562	24	0	0
T122	13611	117	0	0
T123	7433	82	0	0
T138	2238	9	0	0
T153	5870	25	0	0
T158	3066	17	0	0
T166	54033	462	0	0
T168	1756	11	0	0
T169	3160	16	0	0
T170	1958	7	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231960925	1701	0	0
T121	6562	21	0	0
T122	13611	90	0	0
T123	7433	64	0	0
T153	5870	18	0	0
T158	3066	22	0	0
T166	54033	443	0	0
T167	11610	10	0	0
T168	1756	4	0	0
T169	3160	29	0	0
T170	1958	7	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231960925	1792	0	0
T121	6562	23	0	0
T122	13611	116	0	0
T123	7433	36	0	0
T138	2238	9	0	0
T153	5870	54	0	0
T158	3066	10	0	0
T166	54033	433	0	0
T167	11610	3	0	0
T168	1756	4	0	0
T169	3160	24	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231960925	1884	0	0
T121	6562	39	0	0
T122	13611	148	0	0
T123	7433	52	0	0
T138	2238	8	0	0
T153	5870	40	0	0
T166	54033	467	0	0
T167	11610	12	0	0
T168	1756	8	0	0
T169	3160	14	0	0
T170	1958	9	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231960925	1599	0	0
T121	6562	40	0	0
T122	13611	91	0	0
T123	7433	48	0	0
T153	5870	19	0	0
T158	3066	29	0	0
T166	54033	432	0	0
T167	11610	1	0	0
T168	1756	2	0	0
T169	3160	9	0	0
T170	1958	10	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231960925	1721	0	0
T121	6562	21	0	0
T122	13611	128	0	0
T123	7433	42	0	0
T138	2238	1	0	0
T153	5870	38	0	0
T158	3066	6	0	0
T166	54033	448	0	0
T167	11610	18	0	0
T168	1756	2	0	0
T169	3160	22	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231960925	1880	0	0
T121	6562	30	0	0
T122	13611	132	0	0
T123	7433	34	0	0
T138	2238	14	0	0
T153	5870	35	0	0
T158	3066	27	0	0
T166	54033	455	0	0
T167	11610	6	0	0
T168	1756	5	0	0
T169	3160	16	0	0