| T1066 |
/workspace/coverage/default/45.i2c_host_fifo_reset_fmt.243505814 |
|
|
Mar 31 03:47:45 PM PDT 24 |
Mar 31 03:47:46 PM PDT 24 |
332363278 ps |
| T1067 |
/workspace/coverage/default/11.i2c_host_fifo_fmt_empty.1002213852 |
|
|
Mar 31 03:44:45 PM PDT 24 |
Mar 31 03:44:51 PM PDT 24 |
1495447509 ps |
| T1068 |
/workspace/coverage/default/37.i2c_target_stress_rd.283362719 |
|
|
Mar 31 03:47:03 PM PDT 24 |
Mar 31 03:47:16 PM PDT 24 |
16351014161 ps |
| T1069 |
/workspace/coverage/default/40.i2c_target_bad_addr.309985134 |
|
|
Mar 31 03:47:20 PM PDT 24 |
Mar 31 03:47:24 PM PDT 24 |
871429345 ps |
| T1070 |
/workspace/coverage/default/19.i2c_host_fifo_reset_fmt.1984288631 |
|
|
Mar 31 03:45:23 PM PDT 24 |
Mar 31 03:45:24 PM PDT 24 |
119126451 ps |
| T1071 |
/workspace/coverage/default/13.i2c_host_perf.2342904026 |
|
|
Mar 31 03:44:48 PM PDT 24 |
Mar 31 03:44:52 PM PDT 24 |
201325233 ps |
| T1072 |
/workspace/coverage/default/18.i2c_host_mode_toggle.2355874095 |
|
|
Mar 31 03:45:19 PM PDT 24 |
Mar 31 03:45:52 PM PDT 24 |
3173444269 ps |
| T1073 |
/workspace/coverage/default/23.i2c_host_fifo_overflow.1034067044 |
|
|
Mar 31 03:45:57 PM PDT 24 |
Mar 31 03:48:39 PM PDT 24 |
26641898587 ps |
| T1074 |
/workspace/coverage/default/12.i2c_host_fifo_reset_rx.1279656837 |
|
|
Mar 31 03:44:47 PM PDT 24 |
Mar 31 03:44:52 PM PDT 24 |
634380984 ps |
| T1075 |
/workspace/coverage/default/49.i2c_host_fifo_overflow.2519367500 |
|
|
Mar 31 03:48:07 PM PDT 24 |
Mar 31 03:49:50 PM PDT 24 |
1407696192 ps |
| T1076 |
/workspace/coverage/default/8.i2c_host_override.4045177980 |
|
|
Mar 31 03:44:30 PM PDT 24 |
Mar 31 03:44:31 PM PDT 24 |
47508337 ps |
| T1077 |
/workspace/coverage/default/22.i2c_target_fifo_reset_tx.1549568205 |
|
|
Mar 31 03:45:45 PM PDT 24 |
Mar 31 03:45:53 PM PDT 24 |
10963895862 ps |
| T1078 |
/workspace/coverage/default/4.i2c_host_fifo_reset_rx.2514498786 |
|
|
Mar 31 03:44:06 PM PDT 24 |
Mar 31 03:44:10 PM PDT 24 |
137327909 ps |
| T1079 |
/workspace/coverage/default/7.i2c_target_stress_rd.2108763867 |
|
|
Mar 31 03:44:19 PM PDT 24 |
Mar 31 03:44:33 PM PDT 24 |
1469952248 ps |
| T1080 |
/workspace/coverage/default/8.i2c_host_fifo_reset_rx.2128355632 |
|
|
Mar 31 03:44:39 PM PDT 24 |
Mar 31 03:44:46 PM PDT 24 |
239482958 ps |
| T1081 |
/workspace/coverage/default/2.i2c_target_smoke.3052373335 |
|
|
Mar 31 03:43:51 PM PDT 24 |
Mar 31 03:43:58 PM PDT 24 |
4736125755 ps |
| T1082 |
/workspace/coverage/default/17.i2c_host_override.3427573132 |
|
|
Mar 31 03:45:18 PM PDT 24 |
Mar 31 03:45:19 PM PDT 24 |
25769977 ps |
| T1083 |
/workspace/coverage/default/30.i2c_host_fifo_watermark.2970281658 |
|
|
Mar 31 03:46:26 PM PDT 24 |
Mar 31 03:47:43 PM PDT 24 |
7626346168 ps |
| T1084 |
/workspace/coverage/default/15.i2c_alert_test.3654982121 |
|
|
Mar 31 03:45:12 PM PDT 24 |
Mar 31 03:45:13 PM PDT 24 |
27882359 ps |
| T1085 |
/workspace/coverage/default/25.i2c_host_fifo_overflow.2815983225 |
|
|
Mar 31 03:46:10 PM PDT 24 |
Mar 31 03:47:18 PM PDT 24 |
1929972577 ps |
| T1086 |
/workspace/coverage/default/11.i2c_target_fifo_reset_acq.3859786837 |
|
|
Mar 31 03:44:38 PM PDT 24 |
Mar 31 03:45:15 PM PDT 24 |
10305830437 ps |
| T1087 |
/workspace/coverage/default/3.i2c_target_fifo_reset_tx.508047145 |
|
|
Mar 31 03:43:59 PM PDT 24 |
Mar 31 03:44:14 PM PDT 24 |
10421102545 ps |
| T1088 |
/workspace/coverage/default/44.i2c_host_fifo_full.3561731192 |
|
|
Mar 31 03:47:36 PM PDT 24 |
Mar 31 03:48:53 PM PDT 24 |
2204107170 ps |
| T1089 |
/workspace/coverage/default/46.i2c_host_error_intr.161852237 |
|
|
Mar 31 03:47:55 PM PDT 24 |
Mar 31 03:47:57 PM PDT 24 |
107853079 ps |
| T1090 |
/workspace/coverage/default/15.i2c_host_mode_toggle.1918065235 |
|
|
Mar 31 03:45:13 PM PDT 24 |
Mar 31 03:46:31 PM PDT 24 |
1498053414 ps |
| T1091 |
/workspace/coverage/default/29.i2c_target_smoke.2327504207 |
|
|
Mar 31 03:46:23 PM PDT 24 |
Mar 31 03:46:33 PM PDT 24 |
1069283596 ps |
| T1092 |
/workspace/coverage/default/47.i2c_host_mode_toggle.157821141 |
|
|
Mar 31 03:47:56 PM PDT 24 |
Mar 31 03:48:23 PM PDT 24 |
11722602529 ps |
| T1093 |
/workspace/coverage/default/3.i2c_host_fifo_overflow.1034739782 |
|
|
Mar 31 03:44:02 PM PDT 24 |
Mar 31 03:44:42 PM PDT 24 |
1331929849 ps |
| T1094 |
/workspace/coverage/default/3.i2c_host_fifo_reset_fmt.3964421452 |
|
|
Mar 31 03:43:58 PM PDT 24 |
Mar 31 03:43:59 PM PDT 24 |
93352654 ps |
| T1095 |
/workspace/coverage/default/43.i2c_host_fifo_full.2724495721 |
|
|
Mar 31 03:47:31 PM PDT 24 |
Mar 31 03:48:05 PM PDT 24 |
1384123217 ps |
| T1096 |
/workspace/coverage/default/0.i2c_target_intr_stress_wr.1725113766 |
|
|
Mar 31 03:43:46 PM PDT 24 |
Mar 31 03:43:54 PM PDT 24 |
3274531791 ps |
| T1097 |
/workspace/coverage/default/42.i2c_target_bad_addr.26711590 |
|
|
Mar 31 03:47:45 PM PDT 24 |
Mar 31 03:47:49 PM PDT 24 |
668738513 ps |
| T1098 |
/workspace/coverage/default/49.i2c_target_bad_addr.1838436419 |
|
|
Mar 31 03:48:02 PM PDT 24 |
Mar 31 03:48:06 PM PDT 24 |
3622631255 ps |
| T1099 |
/workspace/coverage/default/3.i2c_target_intr_smoke.4196947096 |
|
|
Mar 31 03:43:59 PM PDT 24 |
Mar 31 03:44:06 PM PDT 24 |
1332127143 ps |
| T1100 |
/workspace/coverage/default/2.i2c_host_fifo_fmt_empty.1747416547 |
|
|
Mar 31 03:43:51 PM PDT 24 |
Mar 31 03:43:58 PM PDT 24 |
832831119 ps |
| T1101 |
/workspace/coverage/default/47.i2c_host_stress_all.3452450778 |
|
|
Mar 31 03:48:07 PM PDT 24 |
Mar 31 04:12:32 PM PDT 24 |
15407031921 ps |
| T1102 |
/workspace/coverage/default/43.i2c_alert_test.2246965667 |
|
|
Mar 31 03:47:40 PM PDT 24 |
Mar 31 03:47:41 PM PDT 24 |
43966822 ps |
| T1103 |
/workspace/coverage/default/17.i2c_host_may_nack.1372021288 |
|
|
Mar 31 03:45:21 PM PDT 24 |
Mar 31 03:45:25 PM PDT 24 |
471519337 ps |
| T1104 |
/workspace/coverage/default/30.i2c_host_error_intr.3224649520 |
|
|
Mar 31 03:46:29 PM PDT 24 |
Mar 31 03:46:31 PM PDT 24 |
347084037 ps |
| T1105 |
/workspace/coverage/default/18.i2c_target_timeout.3094115175 |
|
|
Mar 31 03:45:22 PM PDT 24 |
Mar 31 03:45:29 PM PDT 24 |
1455602238 ps |
| T1106 |
/workspace/coverage/default/3.i2c_alert_test.3417311420 |
|
|
Mar 31 03:43:57 PM PDT 24 |
Mar 31 03:43:58 PM PDT 24 |
23264061 ps |
| T1107 |
/workspace/coverage/default/3.i2c_host_smoke.2397323051 |
|
|
Mar 31 03:44:02 PM PDT 24 |
Mar 31 03:45:25 PM PDT 24 |
1739492090 ps |
| T1108 |
/workspace/coverage/default/17.i2c_host_smoke.3719904244 |
|
|
Mar 31 03:45:22 PM PDT 24 |
Mar 31 03:45:51 PM PDT 24 |
11537710939 ps |
| T1109 |
/workspace/coverage/default/48.i2c_target_bad_addr.1709302799 |
|
|
Mar 31 03:48:10 PM PDT 24 |
Mar 31 03:48:13 PM PDT 24 |
484713756 ps |
| T1110 |
/workspace/coverage/default/1.i2c_target_stress_rd.3624392041 |
|
|
Mar 31 03:43:48 PM PDT 24 |
Mar 31 03:44:38 PM PDT 24 |
4853157938 ps |
| T1111 |
/workspace/coverage/default/20.i2c_target_bad_addr.2071635008 |
|
|
Mar 31 03:45:32 PM PDT 24 |
Mar 31 03:45:36 PM PDT 24 |
3320438414 ps |
| T1112 |
/workspace/coverage/default/15.i2c_target_stretch.2507685111 |
|
|
Mar 31 03:45:08 PM PDT 24 |
Mar 31 03:57:25 PM PDT 24 |
20143894050 ps |
| T1113 |
/workspace/coverage/default/0.i2c_host_override.3437177425 |
|
|
Mar 31 03:43:43 PM PDT 24 |
Mar 31 03:43:44 PM PDT 24 |
83565335 ps |
| T1114 |
/workspace/coverage/default/9.i2c_host_smoke.3889096773 |
|
|
Mar 31 03:44:40 PM PDT 24 |
Mar 31 03:45:19 PM PDT 24 |
4358299044 ps |
| T1115 |
/workspace/coverage/default/21.i2c_target_intr_smoke.2826710033 |
|
|
Mar 31 03:45:37 PM PDT 24 |
Mar 31 03:45:45 PM PDT 24 |
2811523714 ps |
| T1116 |
/workspace/coverage/default/48.i2c_host_fifo_fmt_empty.2773112399 |
|
|
Mar 31 03:47:59 PM PDT 24 |
Mar 31 03:48:03 PM PDT 24 |
442456765 ps |
| T1117 |
/workspace/coverage/default/43.i2c_target_fifo_reset_acq.4116811836 |
|
|
Mar 31 03:47:32 PM PDT 24 |
Mar 31 03:48:25 PM PDT 24 |
10093263843 ps |
| T1118 |
/workspace/coverage/default/16.i2c_target_fifo_reset_tx.441120239 |
|
|
Mar 31 03:45:16 PM PDT 24 |
Mar 31 03:45:55 PM PDT 24 |
10090480365 ps |
| T1119 |
/workspace/coverage/default/24.i2c_host_fifo_fmt_empty.542676734 |
|
|
Mar 31 03:45:58 PM PDT 24 |
Mar 31 03:46:03 PM PDT 24 |
774125114 ps |
| T1120 |
/workspace/coverage/default/2.i2c_target_fifo_reset_acq.1584269547 |
|
|
Mar 31 03:43:56 PM PDT 24 |
Mar 31 03:45:19 PM PDT 24 |
10048741242 ps |
| T1121 |
/workspace/coverage/default/37.i2c_target_intr_smoke.2977504184 |
|
|
Mar 31 03:47:09 PM PDT 24 |
Mar 31 03:47:13 PM PDT 24 |
1660996310 ps |
| T1122 |
/workspace/coverage/default/44.i2c_host_mode_toggle.2592973081 |
|
|
Mar 31 03:47:45 PM PDT 24 |
Mar 31 03:49:05 PM PDT 24 |
3047644483 ps |
| T1123 |
/workspace/coverage/default/34.i2c_host_fifo_fmt_empty.2369854151 |
|
|
Mar 31 03:46:46 PM PDT 24 |
Mar 31 03:46:53 PM PDT 24 |
1067674805 ps |
| T1124 |
/workspace/coverage/default/35.i2c_host_smoke.2942976116 |
|
|
Mar 31 03:46:50 PM PDT 24 |
Mar 31 03:47:03 PM PDT 24 |
737720895 ps |
| T1125 |
/workspace/coverage/default/42.i2c_host_may_nack.208975625 |
|
|
Mar 31 03:47:37 PM PDT 24 |
Mar 31 03:47:44 PM PDT 24 |
2092459270 ps |
| T1126 |
/workspace/coverage/default/39.i2c_target_timeout.1249881210 |
|
|
Mar 31 03:47:12 PM PDT 24 |
Mar 31 03:47:20 PM PDT 24 |
1907521006 ps |
| T1127 |
/workspace/coverage/default/4.i2c_alert_test.471758867 |
|
|
Mar 31 03:44:06 PM PDT 24 |
Mar 31 03:44:07 PM PDT 24 |
17700367 ps |
| T1128 |
/workspace/coverage/default/44.i2c_host_error_intr.3164802459 |
|
|
Mar 31 03:47:35 PM PDT 24 |
Mar 31 03:47:36 PM PDT 24 |
1444249536 ps |
| T228 |
/workspace/coverage/default/7.i2c_host_fifo_watermark.3825392700 |
|
|
Mar 31 03:44:15 PM PDT 24 |
Mar 31 03:48:30 PM PDT 24 |
7409899142 ps |
| T1129 |
/workspace/coverage/default/45.i2c_target_intr_smoke.1714678764 |
|
|
Mar 31 03:47:45 PM PDT 24 |
Mar 31 03:47:54 PM PDT 24 |
6173793835 ps |
| T1130 |
/workspace/coverage/default/9.i2c_target_fifo_reset_tx.1143844812 |
|
|
Mar 31 03:44:32 PM PDT 24 |
Mar 31 03:44:50 PM PDT 24 |
10618153440 ps |
| T1131 |
/workspace/coverage/default/10.i2c_target_fifo_reset_tx.1552055729 |
|
|
Mar 31 03:44:39 PM PDT 24 |
Mar 31 03:44:54 PM PDT 24 |
10117567377 ps |
| T1132 |
/workspace/coverage/default/38.i2c_alert_test.2569495542 |
|
|
Mar 31 03:47:07 PM PDT 24 |
Mar 31 03:47:08 PM PDT 24 |
37084948 ps |
| T1133 |
/workspace/coverage/default/12.i2c_target_smoke.2805320994 |
|
|
Mar 31 03:44:44 PM PDT 24 |
Mar 31 03:44:54 PM PDT 24 |
3102547436 ps |
| T1134 |
/workspace/coverage/default/38.i2c_target_smoke.2287047978 |
|
|
Mar 31 03:47:09 PM PDT 24 |
Mar 31 03:47:24 PM PDT 24 |
735737102 ps |
| T1135 |
/workspace/coverage/default/16.i2c_target_stretch.512876987 |
|
|
Mar 31 03:45:13 PM PDT 24 |
Mar 31 03:46:42 PM PDT 24 |
6921977342 ps |
| T1136 |
/workspace/coverage/default/10.i2c_host_perf.615101722 |
|
|
Mar 31 03:44:39 PM PDT 24 |
Mar 31 03:46:43 PM PDT 24 |
12986263475 ps |
| T1137 |
/workspace/coverage/default/28.i2c_target_smoke.4163320977 |
|
|
Mar 31 03:46:15 PM PDT 24 |
Mar 31 03:46:33 PM PDT 24 |
1102555988 ps |
| T1138 |
/workspace/coverage/default/27.i2c_host_perf.2400541054 |
|
|
Mar 31 03:46:10 PM PDT 24 |
Mar 31 03:46:47 PM PDT 24 |
13545579180 ps |
| T1139 |
/workspace/coverage/default/43.i2c_host_fifo_reset_rx.470952910 |
|
|
Mar 31 03:47:47 PM PDT 24 |
Mar 31 03:47:56 PM PDT 24 |
899808206 ps |
| T1140 |
/workspace/coverage/default/14.i2c_host_override.1500738261 |
|
|
Mar 31 03:44:55 PM PDT 24 |
Mar 31 03:44:57 PM PDT 24 |
26332296 ps |
| T1141 |
/workspace/coverage/default/15.i2c_target_timeout.662199467 |
|
|
Mar 31 03:45:09 PM PDT 24 |
Mar 31 03:45:16 PM PDT 24 |
2511515594 ps |
| T1142 |
/workspace/coverage/default/17.i2c_target_stretch.1841446666 |
|
|
Mar 31 03:45:18 PM PDT 24 |
Mar 31 03:45:39 PM PDT 24 |
7578222086 ps |
| T1143 |
/workspace/coverage/default/22.i2c_host_error_intr.4188638847 |
|
|
Mar 31 03:45:47 PM PDT 24 |
Mar 31 03:45:49 PM PDT 24 |
71207585 ps |
| T1144 |
/workspace/coverage/default/1.i2c_host_fifo_overflow.3385208961 |
|
|
Mar 31 03:43:46 PM PDT 24 |
Mar 31 03:44:48 PM PDT 24 |
1876733345 ps |
| T1145 |
/workspace/coverage/default/47.i2c_host_fifo_fmt_empty.1121159834 |
|
|
Mar 31 03:47:52 PM PDT 24 |
Mar 31 03:48:05 PM PDT 24 |
274576355 ps |
| T1146 |
/workspace/coverage/default/9.i2c_target_stretch.4230661201 |
|
|
Mar 31 03:44:27 PM PDT 24 |
Mar 31 03:44:47 PM PDT 24 |
11208892807 ps |
| T1147 |
/workspace/coverage/default/8.i2c_target_hrst.2074090013 |
|
|
Mar 31 03:44:26 PM PDT 24 |
Mar 31 03:44:29 PM PDT 24 |
323930917 ps |
| T1148 |
/workspace/coverage/default/34.i2c_host_perf.3928197511 |
|
|
Mar 31 03:46:51 PM PDT 24 |
Mar 31 03:48:21 PM PDT 24 |
6326883159 ps |
| T1149 |
/workspace/coverage/default/39.i2c_host_smoke.2263562792 |
|
|
Mar 31 03:47:08 PM PDT 24 |
Mar 31 03:47:32 PM PDT 24 |
1945337672 ps |
| T1150 |
/workspace/coverage/default/16.i2c_host_error_intr.2766258682 |
|
|
Mar 31 03:45:11 PM PDT 24 |
Mar 31 03:45:13 PM PDT 24 |
63254995 ps |
| T110 |
/workspace/coverage/default/2.i2c_sec_cm.2054018716 |
|
|
Mar 31 03:43:57 PM PDT 24 |
Mar 31 03:43:58 PM PDT 24 |
64985733 ps |
| T1151 |
/workspace/coverage/default/48.i2c_host_error_intr.2229306957 |
|
|
Mar 31 03:48:05 PM PDT 24 |
Mar 31 03:48:07 PM PDT 24 |
1634613010 ps |
| T1152 |
/workspace/coverage/default/24.i2c_alert_test.3447422845 |
|
|
Mar 31 03:45:58 PM PDT 24 |
Mar 31 03:45:59 PM PDT 24 |
21067832 ps |
| T1153 |
/workspace/coverage/default/39.i2c_host_error_intr.3463583566 |
|
|
Mar 31 03:47:17 PM PDT 24 |
Mar 31 03:47:18 PM PDT 24 |
285562889 ps |
| T1154 |
/workspace/coverage/default/15.i2c_host_perf.3909358040 |
|
|
Mar 31 03:45:08 PM PDT 24 |
Mar 31 03:48:06 PM PDT 24 |
2570679915 ps |
| T1155 |
/workspace/coverage/default/43.i2c_target_fifo_reset_tx.1912536669 |
|
|
Mar 31 03:47:34 PM PDT 24 |
Mar 31 03:47:51 PM PDT 24 |
10126465440 ps |
| T1156 |
/workspace/coverage/default/23.i2c_host_may_nack.320150776 |
|
|
Mar 31 03:45:51 PM PDT 24 |
Mar 31 03:45:57 PM PDT 24 |
358664650 ps |
| T1157 |
/workspace/coverage/default/42.i2c_target_stretch.309131644 |
|
|
Mar 31 03:47:24 PM PDT 24 |
Mar 31 04:04:26 PM PDT 24 |
42207811886 ps |
| T1158 |
/workspace/coverage/default/22.i2c_host_fifo_reset_rx.1824955323 |
|
|
Mar 31 03:45:44 PM PDT 24 |
Mar 31 03:45:47 PM PDT 24 |
512287017 ps |
| T1159 |
/workspace/coverage/default/40.i2c_target_stretch.3253152249 |
|
|
Mar 31 03:47:22 PM PDT 24 |
Mar 31 04:03:19 PM PDT 24 |
41230349724 ps |
| T1160 |
/workspace/coverage/default/35.i2c_target_bad_addr.2903694554 |
|
|
Mar 31 03:46:58 PM PDT 24 |
Mar 31 03:47:04 PM PDT 24 |
2041943367 ps |
| T1161 |
/workspace/coverage/default/9.i2c_host_fifo_fmt_empty.2589512381 |
|
|
Mar 31 03:44:33 PM PDT 24 |
Mar 31 03:44:51 PM PDT 24 |
1050537101 ps |
| T1162 |
/workspace/coverage/default/29.i2c_host_error_intr.3236646692 |
|
|
Mar 31 03:46:22 PM PDT 24 |
Mar 31 03:46:24 PM PDT 24 |
323471530 ps |
| T1163 |
/workspace/coverage/default/32.i2c_host_fifo_reset_fmt.10417792 |
|
|
Mar 31 03:46:33 PM PDT 24 |
Mar 31 03:46:35 PM PDT 24 |
555826007 ps |
| T1164 |
/workspace/coverage/default/8.i2c_host_fifo_reset_fmt.3155403128 |
|
|
Mar 31 03:44:31 PM PDT 24 |
Mar 31 03:44:32 PM PDT 24 |
97765855 ps |
| T1165 |
/workspace/coverage/default/13.i2c_host_fifo_watermark.850309599 |
|
|
Mar 31 03:44:49 PM PDT 24 |
Mar 31 03:45:50 PM PDT 24 |
11688507885 ps |
| T1166 |
/workspace/coverage/default/1.i2c_host_fifo_full.2596606840 |
|
|
Mar 31 03:43:47 PM PDT 24 |
Mar 31 03:45:13 PM PDT 24 |
3105013984 ps |
| T1167 |
/workspace/coverage/default/46.i2c_target_hrst.1641227356 |
|
|
Mar 31 03:47:47 PM PDT 24 |
Mar 31 03:47:49 PM PDT 24 |
1116522943 ps |
| T1168 |
/workspace/coverage/default/45.i2c_host_fifo_reset_rx.25782083 |
|
|
Mar 31 03:47:42 PM PDT 24 |
Mar 31 03:47:46 PM PDT 24 |
341868839 ps |
| T1169 |
/workspace/coverage/default/13.i2c_host_fifo_overflow.2782106271 |
|
|
Mar 31 03:44:51 PM PDT 24 |
Mar 31 03:45:57 PM PDT 24 |
11979366693 ps |
| T1170 |
/workspace/coverage/default/20.i2c_target_stress_rd.3870543903 |
|
|
Mar 31 03:45:27 PM PDT 24 |
Mar 31 03:45:48 PM PDT 24 |
13685390490 ps |
| T1171 |
/workspace/coverage/default/24.i2c_host_error_intr.2811432793 |
|
|
Mar 31 03:45:56 PM PDT 24 |
Mar 31 03:45:58 PM PDT 24 |
65714588 ps |
| T1172 |
/workspace/coverage/default/23.i2c_host_smoke.1640673576 |
|
|
Mar 31 03:45:44 PM PDT 24 |
Mar 31 03:46:08 PM PDT 24 |
5107103274 ps |
| T1173 |
/workspace/coverage/default/5.i2c_target_intr_smoke.3191366934 |
|
|
Mar 31 03:44:07 PM PDT 24 |
Mar 31 03:44:13 PM PDT 24 |
1065997204 ps |
| T1174 |
/workspace/coverage/default/38.i2c_host_perf.3347864394 |
|
|
Mar 31 03:47:08 PM PDT 24 |
Mar 31 04:04:03 PM PDT 24 |
12536946780 ps |
| T1175 |
/workspace/coverage/default/35.i2c_target_timeout.1932613093 |
|
|
Mar 31 03:47:05 PM PDT 24 |
Mar 31 03:47:13 PM PDT 24 |
1243791178 ps |
| T1176 |
/workspace/coverage/default/24.i2c_target_timeout.474713834 |
|
|
Mar 31 03:45:55 PM PDT 24 |
Mar 31 03:46:03 PM PDT 24 |
1505364458 ps |
| T1177 |
/workspace/coverage/default/33.i2c_alert_test.1654352728 |
|
|
Mar 31 03:46:42 PM PDT 24 |
Mar 31 03:46:43 PM PDT 24 |
15080630 ps |
| T1178 |
/workspace/coverage/default/30.i2c_host_mode_toggle.63366116 |
|
|
Mar 31 03:46:28 PM PDT 24 |
Mar 31 03:46:49 PM PDT 24 |
4705457607 ps |
| T1179 |
/workspace/coverage/default/39.i2c_host_may_nack.435079514 |
|
|
Mar 31 03:47:19 PM PDT 24 |
Mar 31 03:47:22 PM PDT 24 |
1563008744 ps |
| T1180 |
/workspace/coverage/default/41.i2c_target_fifo_reset_tx.2582627538 |
|
|
Mar 31 03:47:29 PM PDT 24 |
Mar 31 03:47:47 PM PDT 24 |
10390505828 ps |
| T1181 |
/workspace/coverage/default/47.i2c_target_smoke.2144386031 |
|
|
Mar 31 03:47:51 PM PDT 24 |
Mar 31 03:48:20 PM PDT 24 |
7911507485 ps |
| T1182 |
/workspace/coverage/default/5.i2c_target_stress_rd.4083289676 |
|
|
Mar 31 03:44:06 PM PDT 24 |
Mar 31 03:44:27 PM PDT 24 |
506216758 ps |
| T1183 |
/workspace/coverage/default/21.i2c_host_may_nack.2337215299 |
|
|
Mar 31 03:45:39 PM PDT 24 |
Mar 31 03:45:42 PM PDT 24 |
230552835 ps |
| T1184 |
/workspace/coverage/default/26.i2c_host_perf.1822585093 |
|
|
Mar 31 03:46:05 PM PDT 24 |
Mar 31 03:46:50 PM PDT 24 |
936437914 ps |
| T1185 |
/workspace/coverage/default/41.i2c_host_fifo_fmt_empty.2812188765 |
|
|
Mar 31 03:47:21 PM PDT 24 |
Mar 31 03:47:25 PM PDT 24 |
226001839 ps |
| T1186 |
/workspace/coverage/default/1.i2c_target_stretch.4191127934 |
|
|
Mar 31 03:43:48 PM PDT 24 |
Mar 31 04:24:53 PM PDT 24 |
29740345957 ps |
| T1187 |
/workspace/coverage/default/30.i2c_host_may_nack.2116750979 |
|
|
Mar 31 03:46:30 PM PDT 24 |
Mar 31 03:46:33 PM PDT 24 |
1219482568 ps |
| T1188 |
/workspace/coverage/default/26.i2c_target_hrst.2960933587 |
|
|
Mar 31 03:46:08 PM PDT 24 |
Mar 31 03:46:11 PM PDT 24 |
1744557992 ps |
| T1189 |
/workspace/coverage/default/37.i2c_target_fifo_reset_tx.3126999933 |
|
|
Mar 31 03:47:02 PM PDT 24 |
Mar 31 03:47:53 PM PDT 24 |
10187016860 ps |
| T1190 |
/workspace/coverage/default/11.i2c_host_fifo_reset_fmt.3834783228 |
|
|
Mar 31 03:44:42 PM PDT 24 |
Mar 31 03:44:43 PM PDT 24 |
74691802 ps |
| T1191 |
/workspace/coverage/default/2.i2c_target_hrst.3986140876 |
|
|
Mar 31 03:44:03 PM PDT 24 |
Mar 31 03:44:05 PM PDT 24 |
697067884 ps |
| T1192 |
/workspace/coverage/default/31.i2c_target_hrst.957100132 |
|
|
Mar 31 03:46:35 PM PDT 24 |
Mar 31 03:46:37 PM PDT 24 |
3484111270 ps |
| T1193 |
/workspace/coverage/default/37.i2c_host_fifo_fmt_empty.871583913 |
|
|
Mar 31 03:47:05 PM PDT 24 |
Mar 31 03:47:14 PM PDT 24 |
1640827198 ps |
| T1194 |
/workspace/coverage/default/16.i2c_target_hrst.2505515881 |
|
|
Mar 31 03:45:21 PM PDT 24 |
Mar 31 03:45:24 PM PDT 24 |
2046417158 ps |
| T1195 |
/workspace/coverage/default/9.i2c_alert_test.2420933985 |
|
|
Mar 31 03:44:38 PM PDT 24 |
Mar 31 03:44:39 PM PDT 24 |
48104378 ps |
| T1196 |
/workspace/coverage/default/15.i2c_host_fifo_overflow.418127795 |
|
|
Mar 31 03:45:02 PM PDT 24 |
Mar 31 03:47:44 PM PDT 24 |
8428090386 ps |
| T1197 |
/workspace/coverage/default/9.i2c_target_hrst.326758862 |
|
|
Mar 31 03:44:37 PM PDT 24 |
Mar 31 03:44:39 PM PDT 24 |
514339940 ps |
| T1198 |
/workspace/coverage/default/18.i2c_target_intr_smoke.2008073027 |
|
|
Mar 31 03:45:21 PM PDT 24 |
Mar 31 03:45:26 PM PDT 24 |
3035973511 ps |
| T1199 |
/workspace/coverage/default/19.i2c_host_mode_toggle.3433428108 |
|
|
Mar 31 03:45:26 PM PDT 24 |
Mar 31 03:45:55 PM PDT 24 |
6645371188 ps |
| T1200 |
/workspace/coverage/default/40.i2c_host_fifo_reset_fmt.3246661707 |
|
|
Mar 31 03:47:13 PM PDT 24 |
Mar 31 03:47:14 PM PDT 24 |
585687074 ps |
| T1201 |
/workspace/coverage/default/11.i2c_host_fifo_watermark.2883024523 |
|
|
Mar 31 03:44:42 PM PDT 24 |
Mar 31 03:45:46 PM PDT 24 |
5988927171 ps |
| T1202 |
/workspace/coverage/default/14.i2c_target_fifo_reset_acq.494690242 |
|
|
Mar 31 03:44:57 PM PDT 24 |
Mar 31 03:45:18 PM PDT 24 |
10252677455 ps |
| T1203 |
/workspace/coverage/default/6.i2c_host_mode_toggle.3735417376 |
|
|
Mar 31 03:44:20 PM PDT 24 |
Mar 31 03:45:30 PM PDT 24 |
6732371711 ps |
| T1204 |
/workspace/coverage/default/47.i2c_host_error_intr.1984193852 |
|
|
Mar 31 03:48:04 PM PDT 24 |
Mar 31 03:48:06 PM PDT 24 |
239637857 ps |
| T1205 |
/workspace/coverage/default/18.i2c_target_stress_rd.2835436926 |
|
|
Mar 31 03:45:20 PM PDT 24 |
Mar 31 03:45:54 PM PDT 24 |
7431447430 ps |
| T1206 |
/workspace/coverage/default/17.i2c_target_bad_addr.3996874404 |
|
|
Mar 31 03:45:18 PM PDT 24 |
Mar 31 03:45:22 PM PDT 24 |
1642021493 ps |
| T1207 |
/workspace/coverage/default/11.i2c_target_bad_addr.1755828255 |
|
|
Mar 31 03:44:38 PM PDT 24 |
Mar 31 03:44:42 PM PDT 24 |
431301085 ps |
| T1208 |
/workspace/coverage/default/11.i2c_host_fifo_full.1933580028 |
|
|
Mar 31 03:44:41 PM PDT 24 |
Mar 31 03:45:18 PM PDT 24 |
1286305786 ps |
| T1209 |
/workspace/coverage/default/47.i2c_host_perf.1640381706 |
|
|
Mar 31 03:47:54 PM PDT 24 |
Mar 31 03:50:41 PM PDT 24 |
3396378054 ps |
| T1210 |
/workspace/coverage/default/38.i2c_target_intr_smoke.4048006933 |
|
|
Mar 31 03:47:10 PM PDT 24 |
Mar 31 03:47:16 PM PDT 24 |
2274046014 ps |
| T1211 |
/workspace/coverage/default/32.i2c_target_bad_addr.1293989600 |
|
|
Mar 31 03:46:38 PM PDT 24 |
Mar 31 03:46:41 PM PDT 24 |
629029916 ps |
| T1212 |
/workspace/coverage/default/27.i2c_target_fifo_reset_tx.3822198247 |
|
|
Mar 31 03:46:17 PM PDT 24 |
Mar 31 03:47:52 PM PDT 24 |
10089013970 ps |
| T1213 |
/workspace/coverage/default/17.i2c_target_smoke.3273739288 |
|
|
Mar 31 03:45:17 PM PDT 24 |
Mar 31 03:45:39 PM PDT 24 |
2429782913 ps |
| T104 |
/workspace/coverage/cover_reg_top/5.i2c_tl_errors.544959829 |
|
|
Mar 31 12:27:42 PM PDT 24 |
Mar 31 12:27:44 PM PDT 24 |
76766198 ps |
| T76 |
/workspace/coverage/cover_reg_top/16.i2c_csr_rw.1316539893 |
|
|
Mar 31 12:27:13 PM PDT 24 |
Mar 31 12:27:15 PM PDT 24 |
15633129 ps |
| T233 |
/workspace/coverage/cover_reg_top/9.i2c_intr_test.1420981781 |
|
|
Mar 31 12:27:01 PM PDT 24 |
Mar 31 12:27:02 PM PDT 24 |
15604147 ps |
| T232 |
/workspace/coverage/cover_reg_top/16.i2c_intr_test.3110117685 |
|
|
Mar 31 12:27:00 PM PDT 24 |
Mar 31 12:27:01 PM PDT 24 |
71561038 ps |
| T77 |
/workspace/coverage/cover_reg_top/5.i2c_csr_rw.274388741 |
|
|
Mar 31 12:27:18 PM PDT 24 |
Mar 31 12:27:19 PM PDT 24 |
60528946 ps |
| T78 |
/workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3895713770 |
|
|
Mar 31 12:27:23 PM PDT 24 |
Mar 31 12:27:25 PM PDT 24 |
111857275 ps |
| T105 |
/workspace/coverage/cover_reg_top/13.i2c_tl_errors.4211497340 |
|
|
Mar 31 12:26:52 PM PDT 24 |
Mar 31 12:26:54 PM PDT 24 |
640635096 ps |
| T139 |
/workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1380825751 |
|
|
Mar 31 12:27:00 PM PDT 24 |
Mar 31 12:27:02 PM PDT 24 |
313633914 ps |
| T153 |
/workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.3433232870 |
|
|
Mar 31 12:27:46 PM PDT 24 |
Mar 31 12:27:48 PM PDT 24 |
150531177 ps |
| T234 |
/workspace/coverage/cover_reg_top/5.i2c_intr_test.559540014 |
|
|
Mar 31 12:27:06 PM PDT 24 |
Mar 31 12:27:06 PM PDT 24 |
80127612 ps |
| T1214 |
/workspace/coverage/cover_reg_top/17.i2c_intr_test.1134148242 |
|
|
Mar 31 12:27:20 PM PDT 24 |
Mar 31 12:27:22 PM PDT 24 |
25225566 ps |
| T120 |
/workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.3083496657 |
|
|
Mar 31 12:27:06 PM PDT 24 |
Mar 31 12:27:08 PM PDT 24 |
187201892 ps |
| T121 |
/workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.3114008458 |
|
|
Mar 31 12:27:50 PM PDT 24 |
Mar 31 12:27:52 PM PDT 24 |
273480366 ps |
| T122 |
/workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.3367993773 |
|
|
Mar 31 12:27:03 PM PDT 24 |
Mar 31 12:27:06 PM PDT 24 |
283575564 ps |
| T237 |
/workspace/coverage/cover_reg_top/43.i2c_intr_test.2963229004 |
|
|
Mar 31 12:27:19 PM PDT 24 |
Mar 31 12:27:21 PM PDT 24 |
22539782 ps |
| T126 |
/workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1937281061 |
|
|
Mar 31 12:28:01 PM PDT 24 |
Mar 31 12:28:03 PM PDT 24 |
44857479 ps |
| T238 |
/workspace/coverage/cover_reg_top/22.i2c_intr_test.4055271308 |
|
|
Mar 31 12:27:00 PM PDT 24 |
Mar 31 12:27:06 PM PDT 24 |
19245422 ps |
| T154 |
/workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3188078442 |
|
|
Mar 31 12:27:00 PM PDT 24 |
Mar 31 12:27:01 PM PDT 24 |
55063678 ps |
| T123 |
/workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.807146350 |
|
|
Mar 31 12:27:14 PM PDT 24 |
Mar 31 12:27:16 PM PDT 24 |
177058309 ps |
| T236 |
/workspace/coverage/cover_reg_top/20.i2c_intr_test.1134212396 |
|
|
Mar 31 12:27:27 PM PDT 24 |
Mar 31 12:27:28 PM PDT 24 |
16925763 ps |
| T124 |
/workspace/coverage/cover_reg_top/14.i2c_tl_errors.3301192680 |
|
|
Mar 31 12:26:53 PM PDT 24 |
Mar 31 12:26:55 PM PDT 24 |
249634583 ps |
| T125 |
/workspace/coverage/cover_reg_top/1.i2c_tl_errors.2545692944 |
|
|
Mar 31 12:27:02 PM PDT 24 |
Mar 31 12:27:03 PM PDT 24 |
83675201 ps |
| T136 |
/workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.2947988634 |
|
|
Mar 31 12:27:30 PM PDT 24 |
Mar 31 12:27:30 PM PDT 24 |
19156661 ps |
| T137 |
/workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.2996244373 |
|
|
Mar 31 12:26:51 PM PDT 24 |
Mar 31 12:26:53 PM PDT 24 |
64011409 ps |
| T138 |
/workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.3677386869 |
|
|
Mar 31 12:27:31 PM PDT 24 |
Mar 31 12:27:32 PM PDT 24 |
29081447 ps |
| T239 |
/workspace/coverage/cover_reg_top/13.i2c_intr_test.1942590070 |
|
|
Mar 31 12:27:27 PM PDT 24 |
Mar 31 12:27:28 PM PDT 24 |
45727976 ps |
| T155 |
/workspace/coverage/cover_reg_top/12.i2c_csr_rw.2616700548 |
|
|
Mar 31 12:26:53 PM PDT 24 |
Mar 31 12:26:53 PM PDT 24 |
19428986 ps |
| T166 |
/workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.118097702 |
|
|
Mar 31 12:27:21 PM PDT 24 |
Mar 31 12:27:28 PM PDT 24 |
2701761707 ps |
| T235 |
/workspace/coverage/cover_reg_top/14.i2c_intr_test.2658297222 |
|
|
Mar 31 12:27:42 PM PDT 24 |
Mar 31 12:27:43 PM PDT 24 |
17476086 ps |
| T156 |
/workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.2005855585 |
|
|
Mar 31 12:27:50 PM PDT 24 |
Mar 31 12:27:56 PM PDT 24 |
119574813 ps |
| T140 |
/workspace/coverage/cover_reg_top/18.i2c_csr_rw.3219806249 |
|
|
Mar 31 12:27:06 PM PDT 24 |
Mar 31 12:27:07 PM PDT 24 |
19516540 ps |
| T240 |
/workspace/coverage/cover_reg_top/32.i2c_intr_test.3929028961 |
|
|
Mar 31 12:27:00 PM PDT 24 |
Mar 31 12:27:00 PM PDT 24 |
229244253 ps |
| T127 |
/workspace/coverage/cover_reg_top/18.i2c_tl_errors.3234790490 |
|
|
Mar 31 12:27:06 PM PDT 24 |
Mar 31 12:27:07 PM PDT 24 |
27358845 ps |
| T157 |
/workspace/coverage/cover_reg_top/0.i2c_csr_rw.2627155782 |
|
|
Mar 31 12:27:23 PM PDT 24 |
Mar 31 12:27:24 PM PDT 24 |
23511524 ps |
| T1215 |
/workspace/coverage/cover_reg_top/29.i2c_intr_test.2815685500 |
|
|
Mar 31 12:28:26 PM PDT 24 |
Mar 31 12:28:27 PM PDT 24 |
52422806 ps |
| T1216 |
/workspace/coverage/cover_reg_top/34.i2c_intr_test.2225383048 |
|
|
Mar 31 12:26:54 PM PDT 24 |
Mar 31 12:26:55 PM PDT 24 |
58016942 ps |
| T167 |
/workspace/coverage/cover_reg_top/2.i2c_tl_errors.2940851686 |
|
|
Mar 31 12:27:51 PM PDT 24 |
Mar 31 12:27:55 PM PDT 24 |
290286552 ps |
| T168 |
/workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.792973558 |
|
|
Mar 31 12:27:06 PM PDT 24 |
Mar 31 12:27:06 PM PDT 24 |
293028580 ps |
| T158 |
/workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1365056823 |
|
|
Mar 31 12:27:02 PM PDT 24 |
Mar 31 12:27:03 PM PDT 24 |
63886358 ps |
| T1217 |
/workspace/coverage/cover_reg_top/17.i2c_tl_errors.2423941780 |
|
|
Mar 31 12:27:10 PM PDT 24 |
Mar 31 12:27:12 PM PDT 24 |
96271404 ps |
| T1218 |
/workspace/coverage/cover_reg_top/2.i2c_intr_test.3236587285 |
|
|
Mar 31 12:26:57 PM PDT 24 |
Mar 31 12:26:58 PM PDT 24 |
20335189 ps |
| T1219 |
/workspace/coverage/cover_reg_top/38.i2c_intr_test.2650187551 |
|
|
Mar 31 12:27:26 PM PDT 24 |
Mar 31 12:27:27 PM PDT 24 |
17449308 ps |
| T159 |
/workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1331942773 |
|
|
Mar 31 12:27:01 PM PDT 24 |
Mar 31 12:27:02 PM PDT 24 |
21453599 ps |
| T1220 |
/workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.3934997673 |
|
|
Mar 31 12:27:03 PM PDT 24 |
Mar 31 12:27:07 PM PDT 24 |
395636590 ps |
| T169 |
/workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.4271473641 |
|
|
Mar 31 12:26:59 PM PDT 24 |
Mar 31 12:27:00 PM PDT 24 |
137433763 ps |
| T1221 |
/workspace/coverage/cover_reg_top/21.i2c_intr_test.3741369582 |
|
|
Mar 31 12:27:38 PM PDT 24 |
Mar 31 12:27:39 PM PDT 24 |
42760184 ps |
| T1222 |
/workspace/coverage/cover_reg_top/0.i2c_intr_test.3628151850 |
|
|
Mar 31 12:27:34 PM PDT 24 |
Mar 31 12:27:34 PM PDT 24 |
43140988 ps |
| T1223 |
/workspace/coverage/cover_reg_top/44.i2c_intr_test.1195027398 |
|
|
Mar 31 12:27:51 PM PDT 24 |
Mar 31 12:27:53 PM PDT 24 |
27690723 ps |
| T1224 |
/workspace/coverage/cover_reg_top/3.i2c_intr_test.891089205 |
|
|
Mar 31 12:27:24 PM PDT 24 |
Mar 31 12:27:25 PM PDT 24 |
22017104 ps |
| T141 |
/workspace/coverage/cover_reg_top/4.i2c_csr_rw.550225940 |
|
|
Mar 31 12:26:52 PM PDT 24 |
Mar 31 12:26:53 PM PDT 24 |
47378813 ps |
| T1225 |
/workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1987206333 |
|
|
Mar 31 12:27:24 PM PDT 24 |
Mar 31 12:27:25 PM PDT 24 |
53324888 ps |
| T170 |
/workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3417492490 |
|
|
Mar 31 12:27:10 PM PDT 24 |
Mar 31 12:27:11 PM PDT 24 |
122502890 ps |
| T1226 |
/workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2437506233 |
|
|
Mar 31 12:27:26 PM PDT 24 |
Mar 31 12:27:27 PM PDT 24 |
30260612 ps |
| T1227 |
/workspace/coverage/cover_reg_top/1.i2c_intr_test.1971183655 |
|
|
Mar 31 12:26:54 PM PDT 24 |
Mar 31 12:26:55 PM PDT 24 |
50696600 ps |
| T1228 |
/workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.474116472 |
|
|
Mar 31 12:27:12 PM PDT 24 |
Mar 31 12:27:13 PM PDT 24 |
88056135 ps |
| T1229 |
/workspace/coverage/cover_reg_top/36.i2c_intr_test.2650354161 |
|
|
Mar 31 12:27:03 PM PDT 24 |
Mar 31 12:27:03 PM PDT 24 |
19616901 ps |
| T1230 |
/workspace/coverage/cover_reg_top/0.i2c_tl_errors.902698185 |
|
|
Mar 31 12:27:08 PM PDT 24 |
Mar 31 12:27:10 PM PDT 24 |
75335527 ps |
| T1231 |
/workspace/coverage/cover_reg_top/33.i2c_intr_test.2255763420 |
|
|
Mar 31 12:27:46 PM PDT 24 |
Mar 31 12:27:48 PM PDT 24 |
22311729 ps |
| T1232 |
/workspace/coverage/cover_reg_top/10.i2c_intr_test.2074095572 |
|
|
Mar 31 12:27:29 PM PDT 24 |
Mar 31 12:27:29 PM PDT 24 |
18838233 ps |
| T1233 |
/workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.902688042 |
|
|
Mar 31 12:26:52 PM PDT 24 |
Mar 31 12:26:53 PM PDT 24 |
40444281 ps |
| T1234 |
/workspace/coverage/cover_reg_top/9.i2c_csr_rw.1755587815 |
|
|
Mar 31 12:27:02 PM PDT 24 |
Mar 31 12:27:03 PM PDT 24 |
54894149 ps |
| T1235 |
/workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.1935650632 |
|
|
Mar 31 12:26:56 PM PDT 24 |
Mar 31 12:26:56 PM PDT 24 |
35693311 ps |
| T1236 |
/workspace/coverage/cover_reg_top/11.i2c_intr_test.1101585724 |
|
|
Mar 31 12:27:32 PM PDT 24 |
Mar 31 12:27:33 PM PDT 24 |
31583853 ps |
| T142 |
/workspace/coverage/cover_reg_top/6.i2c_csr_rw.3914600309 |
|
|
Mar 31 12:27:34 PM PDT 24 |
Mar 31 12:27:35 PM PDT 24 |
212000990 ps |
| T143 |
/workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1757882130 |
|
|
Mar 31 12:27:01 PM PDT 24 |
Mar 31 12:27:02 PM PDT 24 |
85097651 ps |
| T1237 |
/workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1322351947 |
|
|
Mar 31 12:27:33 PM PDT 24 |
Mar 31 12:27:33 PM PDT 24 |
191758959 ps |
| T1238 |
/workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2949078755 |
|
|
Mar 31 12:27:52 PM PDT 24 |
Mar 31 12:27:53 PM PDT 24 |
58855653 ps |
| T1239 |
/workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.4148491206 |
|
|
Mar 31 12:27:18 PM PDT 24 |
Mar 31 12:27:20 PM PDT 24 |
76329470 ps |
| T128 |
/workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2458659172 |
|
|
Mar 31 12:27:03 PM PDT 24 |
Mar 31 12:27:05 PM PDT 24 |
224934982 ps |
| T1240 |
/workspace/coverage/cover_reg_top/10.i2c_tl_errors.4104737993 |
|
|
Mar 31 12:26:53 PM PDT 24 |
Mar 31 12:26:55 PM PDT 24 |
55084653 ps |
| T1241 |
/workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.3512571307 |
|
|
Mar 31 12:27:48 PM PDT 24 |
Mar 31 12:27:49 PM PDT 24 |
168534430 ps |
| T1242 |
/workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.1985649084 |
|
|
Mar 31 12:27:27 PM PDT 24 |
Mar 31 12:27:28 PM PDT 24 |
61247879 ps |
| T1243 |
/workspace/coverage/cover_reg_top/15.i2c_tl_errors.3809442415 |
|
|
Mar 31 12:27:36 PM PDT 24 |
Mar 31 12:27:38 PM PDT 24 |
223740501 ps |
| T1244 |
/workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.4111837048 |
|
|
Mar 31 12:27:23 PM PDT 24 |
Mar 31 12:27:26 PM PDT 24 |
69883637 ps |
| T144 |
/workspace/coverage/cover_reg_top/14.i2c_csr_rw.1566201754 |
|
|
Mar 31 12:27:03 PM PDT 24 |
Mar 31 12:27:05 PM PDT 24 |
28607178 ps |
| T1245 |
/workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.3631412079 |
|
|
Mar 31 12:26:52 PM PDT 24 |
Mar 31 12:26:53 PM PDT 24 |
22768068 ps |
| T1246 |
/workspace/coverage/cover_reg_top/25.i2c_intr_test.1485955480 |
|
|
Mar 31 12:27:30 PM PDT 24 |
Mar 31 12:27:31 PM PDT 24 |
43410815 ps |
| T1247 |
/workspace/coverage/cover_reg_top/15.i2c_intr_test.386751160 |
|
|
Mar 31 12:27:02 PM PDT 24 |
Mar 31 12:27:03 PM PDT 24 |
19928307 ps |
| T223 |
/workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3902615773 |
|
|
Mar 31 12:27:24 PM PDT 24 |
Mar 31 12:27:27 PM PDT 24 |
297103699 ps |
| T1248 |
/workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.1356292698 |
|
|
Mar 31 12:26:53 PM PDT 24 |
Mar 31 12:26:54 PM PDT 24 |
39280609 ps |
| T1249 |
/workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.4142302213 |
|
|
Mar 31 12:27:03 PM PDT 24 |
Mar 31 12:27:04 PM PDT 24 |
58662962 ps |
| T134 |
/workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.3106195586 |
|
|
Mar 31 12:27:51 PM PDT 24 |
Mar 31 12:27:54 PM PDT 24 |
273732470 ps |
| T1250 |
/workspace/coverage/cover_reg_top/46.i2c_intr_test.3254491092 |
|
|
Mar 31 12:28:26 PM PDT 24 |
Mar 31 12:28:27 PM PDT 24 |
17976680 ps |
| T1251 |
/workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.993278873 |
|
|
Mar 31 12:27:01 PM PDT 24 |
Mar 31 12:27:02 PM PDT 24 |
80762871 ps |
| T1252 |
/workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3842572868 |
|
|
Mar 31 12:27:06 PM PDT 24 |
Mar 31 12:27:08 PM PDT 24 |
81650245 ps |
| T1253 |
/workspace/coverage/cover_reg_top/42.i2c_intr_test.2745622442 |
|
|
Mar 31 12:28:44 PM PDT 24 |
Mar 31 12:28:45 PM PDT 24 |
30274423 ps |
| T129 |
/workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.3467672413 |
|
|
Mar 31 12:27:08 PM PDT 24 |
Mar 31 12:27:10 PM PDT 24 |
126221502 ps |
| T149 |
/workspace/coverage/cover_reg_top/13.i2c_csr_rw.913907557 |
|
|
Mar 31 12:27:46 PM PDT 24 |
Mar 31 12:27:47 PM PDT 24 |
330484840 ps |
| T1254 |
/workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.4065733089 |
|
|
Mar 31 12:27:20 PM PDT 24 |
Mar 31 12:27:22 PM PDT 24 |
85483828 ps |
| T1255 |
/workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.2160008784 |
|
|
Mar 31 12:27:00 PM PDT 24 |
Mar 31 12:27:02 PM PDT 24 |
40349888 ps |
| T130 |
/workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.4238392190 |
|
|
Mar 31 12:27:02 PM PDT 24 |
Mar 31 12:27:04 PM PDT 24 |
437763039 ps |
| T1256 |
/workspace/coverage/cover_reg_top/19.i2c_intr_test.2140086869 |
|
|
Mar 31 12:26:58 PM PDT 24 |
Mar 31 12:26:59 PM PDT 24 |
15293368 ps |
| T145 |
/workspace/coverage/cover_reg_top/11.i2c_csr_rw.869722886 |
|
|
Mar 31 12:27:03 PM PDT 24 |
Mar 31 12:27:03 PM PDT 24 |
26223782 ps |
| T1257 |
/workspace/coverage/cover_reg_top/15.i2c_csr_rw.3327731598 |
|
|
Mar 31 12:27:19 PM PDT 24 |
Mar 31 12:27:20 PM PDT 24 |
24994978 ps |
| T1258 |
/workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3617263561 |
|
|
Mar 31 12:27:54 PM PDT 24 |
Mar 31 12:27:55 PM PDT 24 |
24880310 ps |
| T1259 |
/workspace/coverage/cover_reg_top/39.i2c_intr_test.2681098230 |
|
|
Mar 31 12:28:44 PM PDT 24 |
Mar 31 12:28:44 PM PDT 24 |
19007522 ps |
| T1260 |
/workspace/coverage/cover_reg_top/40.i2c_intr_test.3580119613 |
|
|
Mar 31 12:28:26 PM PDT 24 |
Mar 31 12:28:27 PM PDT 24 |
26569878 ps |
| T1261 |
/workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2946675155 |
|
|
Mar 31 12:27:01 PM PDT 24 |
Mar 31 12:27:02 PM PDT 24 |
20125566 ps |
| T1262 |
/workspace/coverage/cover_reg_top/31.i2c_intr_test.302300241 |
|
|
Mar 31 12:27:41 PM PDT 24 |
Mar 31 12:27:42 PM PDT 24 |
38333149 ps |
| T1263 |
/workspace/coverage/cover_reg_top/4.i2c_tl_errors.1338832677 |
|
|
Mar 31 12:27:30 PM PDT 24 |
Mar 31 12:27:32 PM PDT 24 |
49500847 ps |