Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
87.67 97.23 91.15 97.65 44.23 94.57 98.23 90.65


Total test records in report: 1313
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T1264 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1475185623 Mar 31 12:26:54 PM PDT 24 Mar 31 12:26:55 PM PDT 24 32395295 ps
T1265 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.275446298 Mar 31 12:27:04 PM PDT 24 Mar 31 12:27:05 PM PDT 24 200599044 ps
T1266 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1831643320 Mar 31 12:27:17 PM PDT 24 Mar 31 12:27:18 PM PDT 24 222566976 ps
T1267 /workspace/coverage/cover_reg_top/35.i2c_intr_test.1713965484 Mar 31 12:27:44 PM PDT 24 Mar 31 12:27:45 PM PDT 24 120488563 ps
T1268 /workspace/coverage/cover_reg_top/49.i2c_intr_test.362267015 Mar 31 12:27:03 PM PDT 24 Mar 31 12:27:04 PM PDT 24 32355577 ps
T1269 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.464097724 Mar 31 12:27:23 PM PDT 24 Mar 31 12:27:26 PM PDT 24 152854342 ps
T1270 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.2562222641 Mar 31 12:27:01 PM PDT 24 Mar 31 12:27:02 PM PDT 24 252601147 ps
T1271 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.32934596 Mar 31 12:26:52 PM PDT 24 Mar 31 12:26:53 PM PDT 24 24648648 ps
T1272 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.3028244488 Mar 31 12:26:50 PM PDT 24 Mar 31 12:26:53 PM PDT 24 331030736 ps
T1273 /workspace/coverage/cover_reg_top/47.i2c_intr_test.3913290487 Mar 31 12:28:44 PM PDT 24 Mar 31 12:28:45 PM PDT 24 16882226 ps
T1274 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.3945634655 Mar 31 12:27:12 PM PDT 24 Mar 31 12:27:14 PM PDT 24 153923540 ps
T1275 /workspace/coverage/cover_reg_top/26.i2c_intr_test.1485013824 Mar 31 12:27:00 PM PDT 24 Mar 31 12:27:01 PM PDT 24 36214794 ps
T1276 /workspace/coverage/cover_reg_top/12.i2c_intr_test.1117502500 Mar 31 12:27:02 PM PDT 24 Mar 31 12:27:02 PM PDT 24 15612801 ps
T1277 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1596237830 Mar 31 12:27:29 PM PDT 24 Mar 31 12:27:29 PM PDT 24 118113378 ps
T1278 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1231276107 Mar 31 12:27:28 PM PDT 24 Mar 31 12:27:28 PM PDT 24 59407318 ps
T1279 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.4050449812 Mar 31 12:27:35 PM PDT 24 Mar 31 12:27:36 PM PDT 24 110199745 ps
T1280 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.2371392562 Mar 31 12:27:01 PM PDT 24 Mar 31 12:27:03 PM PDT 24 141164775 ps
T135 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.572665089 Mar 31 12:27:31 PM PDT 24 Mar 31 12:27:33 PM PDT 24 243168655 ps
T146 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3536165710 Mar 31 12:27:35 PM PDT 24 Mar 31 12:27:36 PM PDT 24 38507284 ps
T1281 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.148452861 Mar 31 12:27:17 PM PDT 24 Mar 31 12:27:19 PM PDT 24 46025938 ps
T147 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.2548072637 Mar 31 12:27:28 PM PDT 24 Mar 31 12:27:29 PM PDT 24 88801720 ps
T1282 /workspace/coverage/cover_reg_top/18.i2c_intr_test.1414506169 Mar 31 12:26:54 PM PDT 24 Mar 31 12:26:55 PM PDT 24 14894928 ps
T131 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3652867443 Mar 31 12:27:31 PM PDT 24 Mar 31 12:27:33 PM PDT 24 49725797 ps
T132 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.3893964425 Mar 31 12:27:02 PM PDT 24 Mar 31 12:27:04 PM PDT 24 256752132 ps
T1283 /workspace/coverage/cover_reg_top/7.i2c_intr_test.1118019791 Mar 31 12:27:45 PM PDT 24 Mar 31 12:27:46 PM PDT 24 63099589 ps
T1284 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.1350174922 Mar 31 12:27:51 PM PDT 24 Mar 31 12:27:53 PM PDT 24 68666201 ps
T148 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.473687171 Mar 31 12:27:13 PM PDT 24 Mar 31 12:27:14 PM PDT 24 66836312 ps
T1285 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.742153322 Mar 31 12:27:23 PM PDT 24 Mar 31 12:27:24 PM PDT 24 42101191 ps
T1286 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1012459149 Mar 31 12:26:56 PM PDT 24 Mar 31 12:26:57 PM PDT 24 106392365 ps
T1287 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.937399877 Mar 31 12:26:58 PM PDT 24 Mar 31 12:26:59 PM PDT 24 67204749 ps
T1288 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.2122981255 Mar 31 12:27:09 PM PDT 24 Mar 31 12:27:12 PM PDT 24 130260860 ps
T1289 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3615684889 Mar 31 12:27:27 PM PDT 24 Mar 31 12:27:29 PM PDT 24 121095599 ps
T150 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.3505920639 Mar 31 12:26:53 PM PDT 24 Mar 31 12:26:58 PM PDT 24 495858938 ps
T1290 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.3242574379 Mar 31 12:27:46 PM PDT 24 Mar 31 12:27:48 PM PDT 24 40235310 ps
T224 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.2354602991 Mar 31 12:27:03 PM PDT 24 Mar 31 12:27:05 PM PDT 24 152613600 ps
T1291 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.1357155635 Mar 31 12:27:57 PM PDT 24 Mar 31 12:27:59 PM PDT 24 226607951 ps
T1292 /workspace/coverage/cover_reg_top/28.i2c_intr_test.2490116751 Mar 31 12:27:19 PM PDT 24 Mar 31 12:27:20 PM PDT 24 80029991 ps
T1293 /workspace/coverage/cover_reg_top/41.i2c_intr_test.3729635959 Mar 31 12:27:47 PM PDT 24 Mar 31 12:27:48 PM PDT 24 93334872 ps
T221 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2108945802 Mar 31 12:27:17 PM PDT 24 Mar 31 12:27:20 PM PDT 24 136318127 ps
T133 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.2246449128 Mar 31 12:27:02 PM PDT 24 Mar 31 12:27:03 PM PDT 24 262799848 ps
T1294 /workspace/coverage/cover_reg_top/45.i2c_intr_test.437894294 Mar 31 12:26:54 PM PDT 24 Mar 31 12:26:59 PM PDT 24 74931854 ps
T152 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.3719480339 Mar 31 12:27:08 PM PDT 24 Mar 31 12:27:09 PM PDT 24 24527101 ps
T1295 /workspace/coverage/cover_reg_top/8.i2c_intr_test.1822501182 Mar 31 12:27:25 PM PDT 24 Mar 31 12:27:26 PM PDT 24 124666943 ps
T1296 /workspace/coverage/cover_reg_top/37.i2c_intr_test.369512073 Mar 31 12:27:51 PM PDT 24 Mar 31 12:27:57 PM PDT 24 40503057 ps
T1297 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.3775387099 Mar 31 12:27:32 PM PDT 24 Mar 31 12:27:34 PM PDT 24 162341404 ps
T1298 /workspace/coverage/cover_reg_top/4.i2c_intr_test.213111704 Mar 31 12:26:53 PM PDT 24 Mar 31 12:26:54 PM PDT 24 18815543 ps
T1299 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.1909279248 Mar 31 12:27:34 PM PDT 24 Mar 31 12:27:35 PM PDT 24 183451378 ps
T1300 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2855367042 Mar 31 12:27:17 PM PDT 24 Mar 31 12:27:19 PM PDT 24 215369671 ps
T1301 /workspace/coverage/cover_reg_top/27.i2c_intr_test.3776776737 Mar 31 12:27:02 PM PDT 24 Mar 31 12:27:03 PM PDT 24 17652516 ps
T1302 /workspace/coverage/cover_reg_top/30.i2c_intr_test.1000587377 Mar 31 12:27:17 PM PDT 24 Mar 31 12:27:19 PM PDT 24 19350852 ps
T1303 /workspace/coverage/cover_reg_top/23.i2c_intr_test.3750145250 Mar 31 12:27:00 PM PDT 24 Mar 31 12:27:00 PM PDT 24 17030351 ps
T1304 /workspace/coverage/cover_reg_top/24.i2c_intr_test.498627918 Mar 31 12:27:03 PM PDT 24 Mar 31 12:27:04 PM PDT 24 17786597 ps
T1305 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.2129351320 Mar 31 12:27:36 PM PDT 24 Mar 31 12:27:37 PM PDT 24 35359282 ps
T1306 /workspace/coverage/cover_reg_top/6.i2c_intr_test.2395068516 Mar 31 12:26:59 PM PDT 24 Mar 31 12:27:00 PM PDT 24 23646964 ps
T1307 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2905399729 Mar 31 12:27:01 PM PDT 24 Mar 31 12:27:01 PM PDT 24 20757599 ps
T1308 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1645560449 Mar 31 12:26:58 PM PDT 24 Mar 31 12:26:59 PM PDT 24 61301685 ps
T1309 /workspace/coverage/cover_reg_top/48.i2c_intr_test.1434805538 Mar 31 12:28:46 PM PDT 24 Mar 31 12:28:52 PM PDT 24 16862639 ps
T222 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.318162357 Mar 31 12:27:01 PM PDT 24 Mar 31 12:27:03 PM PDT 24 146539401 ps
T1310 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.1455326155 Mar 31 12:26:53 PM PDT 24 Mar 31 12:26:56 PM PDT 24 55606883 ps
T151 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.1885782559 Mar 31 12:27:40 PM PDT 24 Mar 31 12:27:41 PM PDT 24 19796663 ps
T1311 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.980133773 Mar 31 12:26:52 PM PDT 24 Mar 31 12:26:53 PM PDT 24 26308622 ps
T1312 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.3291100932 Mar 31 12:27:22 PM PDT 24 Mar 31 12:27:25 PM PDT 24 142977188 ps
T1313 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.558666457 Mar 31 12:26:54 PM PDT 24 Mar 31 12:26:55 PM PDT 24 57043117 ps

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.4253740724
Short name T3
Test name
Test status
Simulation time 10414846417 ps
CPU time 16.61 seconds
Started Mar 31 03:48:04 PM PDT 24
Finished Mar 31 03:48:21 PM PDT 24
Peak memory 344460 kb
Host smart-960cdf6c-a227-4744-a01e-e51cc0364a8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253740724 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.4253740724
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.3921322991
Short name T28
Test name
Test status
Simulation time 7131152513 ps
CPU time 62.18 seconds
Started Mar 31 03:47:20 PM PDT 24
Finished Mar 31 03:48:23 PM PDT 24
Peak memory 618192 kb
Host smart-c610cc1b-7d60-4d1b-80ae-caa90f067a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921322991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.3921322991
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_stress_all.1321801329
Short name T20
Test name
Test status
Simulation time 15791799933 ps
CPU time 1330.86 seconds
Started Mar 31 03:44:20 PM PDT 24
Finished Mar 31 04:06:32 PM PDT 24
Peak memory 3241456 kb
Host smart-4af4c54d-a0eb-4080-81de-8bb9798b87e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321801329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stress_all.1321801329
Directory /workspace/7.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.3367993773
Short name T122
Test name
Test status
Simulation time 283575564 ps
CPU time 2 seconds
Started Mar 31 12:27:03 PM PDT 24
Finished Mar 31 12:27:06 PM PDT 24
Peak memory 203556 kb
Host smart-c176a92e-c39f-4d58-9495-9984b725a516
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367993773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.3367993773
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/33.i2c_host_override.3112072055
Short name T29
Test name
Test status
Simulation time 47985150 ps
CPU time 0.62 seconds
Started Mar 31 03:46:37 PM PDT 24
Finished Mar 31 03:46:39 PM PDT 24
Peak memory 203612 kb
Host smart-5114603e-f952-4a6a-a987-06d20e701e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112072055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.3112072055
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_target_unexp_stop.2341588955
Short name T32
Test name
Test status
Simulation time 2453131988 ps
CPU time 3.85 seconds
Started Mar 31 03:47:48 PM PDT 24
Finished Mar 31 03:47:52 PM PDT 24
Peak memory 203916 kb
Host smart-b3b785d7-3b18-478a-9ad4-7658bc127b65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341588955 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 46.i2c_target_unexp_stop.2341588955
Directory /workspace/46.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.2377737832
Short name T217
Test name
Test status
Simulation time 2033636828 ps
CPU time 8.87 seconds
Started Mar 31 03:44:56 PM PDT 24
Finished Mar 31 03:45:06 PM PDT 24
Peak memory 203852 kb
Host smart-ff437d16-f163-494f-8646-c6457f8f5bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377737832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.2377737832
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.3301192680
Short name T124
Test name
Test status
Simulation time 249634583 ps
CPU time 2.45 seconds
Started Mar 31 12:26:53 PM PDT 24
Finished Mar 31 12:26:55 PM PDT 24
Peak memory 203552 kb
Host smart-1a0385a7-6cee-4f7e-8637-6eb9316f4bd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301192680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.3301192680
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.581139415
Short name T12
Test name
Test status
Simulation time 2771725385 ps
CPU time 26.82 seconds
Started Mar 31 03:44:28 PM PDT 24
Finished Mar 31 03:44:55 PM PDT 24
Peak memory 333856 kb
Host smart-aea22dc9-8d01-4ba8-9d5b-bb34fb8fb8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581139415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.581139415
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.2062751477
Short name T106
Test name
Test status
Simulation time 43020640 ps
CPU time 0.85 seconds
Started Mar 31 03:43:59 PM PDT 24
Finished Mar 31 03:44:00 PM PDT 24
Peak memory 221300 kb
Host smart-0d4f4fbc-2f36-4dbb-b906-15abb8034536
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062751477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.2062751477
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/29.i2c_host_stress_all.3219916728
Short name T160
Test name
Test status
Simulation time 27038295185 ps
CPU time 928.55 seconds
Started Mar 31 03:46:21 PM PDT 24
Finished Mar 31 04:01:50 PM PDT 24
Peak memory 2896260 kb
Host smart-8e076905-dcb4-4d82-9f2d-1755be5c8aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219916728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.3219916728
Directory /workspace/29.i2c_host_stress_all/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.3258124279
Short name T25
Test name
Test status
Simulation time 59315946030 ps
CPU time 1164.46 seconds
Started Mar 31 03:44:37 PM PDT 24
Finished Mar 31 04:04:02 PM PDT 24
Peak memory 2265448 kb
Host smart-d794f795-0ca5-4e1c-af56-27fc19e7bd11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258124279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.3258124279
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.869722886
Short name T145
Test name
Test status
Simulation time 26223782 ps
CPU time 0.71 seconds
Started Mar 31 12:27:03 PM PDT 24
Finished Mar 31 12:27:03 PM PDT 24
Peak memory 203192 kb
Host smart-daf75c5b-bd6d-4844-b847-fad2edbec497
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869722886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.869722886
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.823874832
Short name T118
Test name
Test status
Simulation time 1995782069 ps
CPU time 4.5 seconds
Started Mar 31 03:43:44 PM PDT 24
Finished Mar 31 03:43:49 PM PDT 24
Peak memory 203808 kb
Host smart-eb5a2c35-30ee-42ae-9cc5-80772ff6e7e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823874832 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.823874832
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_host_stress_all.2330230512
Short name T230
Test name
Test status
Simulation time 15978614279 ps
CPU time 363.89 seconds
Started Mar 31 03:47:49 PM PDT 24
Finished Mar 31 03:53:53 PM PDT 24
Peak memory 1381072 kb
Host smart-e69cd5e4-d036-4c66-aef5-8ca4aef32380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330230512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stress_all.2330230512
Directory /workspace/46.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.2012268678
Short name T37
Test name
Test status
Simulation time 89803158 ps
CPU time 0.86 seconds
Started Mar 31 03:43:42 PM PDT 24
Finished Mar 31 03:43:43 PM PDT 24
Peak memory 203692 kb
Host smart-c8754aba-d90b-41e6-9645-7930b15b2666
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012268678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fm
t.2012268678
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.290544698
Short name T211
Test name
Test status
Simulation time 1495669403 ps
CPU time 2.07 seconds
Started Mar 31 03:47:08 PM PDT 24
Finished Mar 31 03:47:10 PM PDT 24
Peak memory 203808 kb
Host smart-cb932cf3-aa1f-4eff-b5e5-0ea65fb61dd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290544698 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 38.i2c_target_hrst.290544698
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.1960061703
Short name T14
Test name
Test status
Simulation time 3756742210 ps
CPU time 5.95 seconds
Started Mar 31 03:43:53 PM PDT 24
Finished Mar 31 03:43:59 PM PDT 24
Peak memory 220116 kb
Host smart-07831970-1a25-4dea-8837-3adf4f8da991
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960061703 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.1960061703
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.3899915141
Short name T62
Test name
Test status
Simulation time 10048634259 ps
CPU time 85.12 seconds
Started Mar 31 03:47:47 PM PDT 24
Finished Mar 31 03:49:12 PM PDT 24
Peak memory 572728 kb
Host smart-b9cebbd7-fd3d-41eb-bd5c-9f96b58ec208
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899915141 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.3899915141
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_alert_test.818248385
Short name T252
Test name
Test status
Simulation time 17252709 ps
CPU time 0.65 seconds
Started Mar 31 03:43:56 PM PDT 24
Finished Mar 31 03:43:57 PM PDT 24
Peak memory 203724 kb
Host smart-a1cc5234-2ba0-4ccd-87a5-2acbcfc84563
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818248385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.818248385
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_stress_all.1393800862
Short name T165
Test name
Test status
Simulation time 18724261379 ps
CPU time 1518.25 seconds
Started Mar 31 03:47:58 PM PDT 24
Finished Mar 31 04:13:17 PM PDT 24
Peak memory 3586464 kb
Host smart-dab6d27e-7e40-4cfb-a78e-e74eb65b4248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393800862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stress_all.1393800862
Directory /workspace/49.i2c_host_stress_all/latest

Test location /workspace/coverage/default/14.i2c_host_stress_all.2305706136
Short name T171
Test name
Test status
Simulation time 31250583378 ps
CPU time 231.36 seconds
Started Mar 31 03:44:55 PM PDT 24
Finished Mar 31 03:48:48 PM PDT 24
Peak memory 1064552 kb
Host smart-c60f434f-f4c0-4e56-bf1a-0702049dae4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305706136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stress_all.2305706136
Directory /workspace/14.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_host_stress_all.2078505863
Short name T57
Test name
Test status
Simulation time 35522905942 ps
CPU time 1149.36 seconds
Started Mar 31 03:43:42 PM PDT 24
Finished Mar 31 04:02:52 PM PDT 24
Peak memory 2105988 kb
Host smart-18b1497e-d62c-4ba7-b42d-39a6260fa9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078505863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stress_all.2078505863
Directory /workspace/0.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.3341509510
Short name T435
Test name
Test status
Simulation time 139750051 ps
CPU time 3.1 seconds
Started Mar 31 03:43:35 PM PDT 24
Finished Mar 31 03:43:39 PM PDT 24
Peak memory 203868 kb
Host smart-c604f573-2607-4540-948e-2e552cd02aa2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341509510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.
3341509510
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.57460916
Short name T34
Test name
Test status
Simulation time 579234568 ps
CPU time 1.81 seconds
Started Mar 31 03:44:48 PM PDT 24
Finished Mar 31 03:44:50 PM PDT 24
Peak memory 203744 kb
Host smart-7639c002-f47c-4404-9cf7-f7b63d7d8ca9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57460916 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 12.i2c_target_hrst.57460916
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_host_stress_all.2477273065
Short name T21
Test name
Test status
Simulation time 41520901998 ps
CPU time 3442.28 seconds
Started Mar 31 03:45:24 PM PDT 24
Finished Mar 31 04:42:47 PM PDT 24
Peak memory 3251692 kb
Host smart-7d22cbd6-7efa-4f19-b85b-4bed9e108537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477273065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stress_all.2477273065
Directory /workspace/18.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.572665089
Short name T135
Test name
Test status
Simulation time 243168655 ps
CPU time 2.11 seconds
Started Mar 31 12:27:31 PM PDT 24
Finished Mar 31 12:27:33 PM PDT 24
Peak memory 203544 kb
Host smart-102744e6-21e2-4db1-8cf3-e09fd66a629c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572665089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.572665089
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.940709156
Short name T244
Test name
Test status
Simulation time 10423338321 ps
CPU time 14.34 seconds
Started Mar 31 03:45:33 PM PDT 24
Finished Mar 31 03:45:48 PM PDT 24
Peak memory 283704 kb
Host smart-f5a23721-e25b-4ba6-ae25-0a65fcf32f12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940709156 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_acq.940709156
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.2627155782
Short name T157
Test name
Test status
Simulation time 23511524 ps
CPU time 0.67 seconds
Started Mar 31 12:27:23 PM PDT 24
Finished Mar 31 12:27:24 PM PDT 24
Peak memory 203324 kb
Host smart-f3296a3b-ccf4-4630-9707-7e58d1efaf33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627155782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.2627155782
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.3132288057
Short name T214
Test name
Test status
Simulation time 4096839895 ps
CPU time 23.89 seconds
Started Mar 31 03:43:49 PM PDT 24
Finished Mar 31 03:44:13 PM PDT 24
Peak memory 400780 kb
Host smart-41f2d930-2b84-4e42-a875-4d8056fa4ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132288057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.3132288057
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.2298932201
Short name T202
Test name
Test status
Simulation time 770068919 ps
CPU time 1.29 seconds
Started Mar 31 03:46:14 PM PDT 24
Finished Mar 31 03:46:16 PM PDT 24
Peak memory 203808 kb
Host smart-f36745ca-c402-47e9-b470-dab50829085d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298932201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f
mt.2298932201
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.81107142
Short name T88
Test name
Test status
Simulation time 10262510583 ps
CPU time 14.16 seconds
Started Mar 31 03:44:10 PM PDT 24
Finished Mar 31 03:44:25 PM PDT 24
Peak memory 294292 kb
Host smart-baaa4da6-181f-4b73-92a8-0725d0a6cd43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81107142 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.i2c_target_fifo_reset_acq.81107142
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.1972524223
Short name T94
Test name
Test status
Simulation time 10067839850 ps
CPU time 18.18 seconds
Started Mar 31 03:43:50 PM PDT 24
Finished Mar 31 03:44:09 PM PDT 24
Peak memory 332084 kb
Host smart-7e8e382c-6323-4500-a2ad-7bb553c82818
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972524223 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.1972524223
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.3628151850
Short name T1222
Test name
Test status
Simulation time 43140988 ps
CPU time 0.66 seconds
Started Mar 31 12:27:34 PM PDT 24
Finished Mar 31 12:27:34 PM PDT 24
Peak memory 203192 kb
Host smart-b3cbed1f-ec30-49d2-873c-9b0f074bb048
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628151850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.3628151850
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.318162357
Short name T222
Test name
Test status
Simulation time 146539401 ps
CPU time 1.38 seconds
Started Mar 31 12:27:01 PM PDT 24
Finished Mar 31 12:27:03 PM PDT 24
Peak memory 203544 kb
Host smart-a18daba4-fa2c-41c8-8d99-4991239f8d26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318162357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.318162357
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_host_perf.3148213947
Short name T194
Test name
Test status
Simulation time 888147300 ps
CPU time 2.96 seconds
Started Mar 31 03:43:39 PM PDT 24
Finished Mar 31 03:43:42 PM PDT 24
Peak memory 228288 kb
Host smart-a40a0b3a-899c-497b-b7f5-68cd68b92c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148213947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.3148213947
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.3452905472
Short name T225
Test name
Test status
Simulation time 22270378223 ps
CPU time 116.37 seconds
Started Mar 31 03:43:47 PM PDT 24
Finished Mar 31 03:45:44 PM PDT 24
Peak memory 1092356 kb
Host smart-a9de8626-5541-4fd3-aa95-0b541da23cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452905472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.3452905472
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_perf.2899759324
Short name T9
Test name
Test status
Simulation time 733394995 ps
CPU time 3.35 seconds
Started Mar 31 03:44:44 PM PDT 24
Finished Mar 31 03:44:48 PM PDT 24
Peak memory 236232 kb
Host smart-7c41de7e-9ac9-4101-97ab-6337cda7c342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899759324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.2899759324
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_perf.4085449082
Short name T191
Test name
Test status
Simulation time 7758287396 ps
CPU time 13.55 seconds
Started Mar 31 03:45:23 PM PDT 24
Finished Mar 31 03:45:37 PM PDT 24
Peak memory 220232 kb
Host smart-4321f0ed-df6c-47d5-8f31-1b59a77d9efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085449082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.4085449082
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_stress_all.3823288249
Short name T100
Test name
Test status
Simulation time 14115775698 ps
CPU time 233.41 seconds
Started Mar 31 03:45:45 PM PDT 24
Finished Mar 31 03:49:39 PM PDT 24
Peak memory 1962536 kb
Host smart-7309cdf0-3914-48c9-941b-4a77209352c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823288249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stress_all.3823288249
Directory /workspace/22.i2c_host_stress_all/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.650205458
Short name T210
Test name
Test status
Simulation time 5892962967 ps
CPU time 12.26 seconds
Started Mar 31 03:46:10 PM PDT 24
Finished Mar 31 03:46:23 PM PDT 24
Peak memory 203832 kb
Host smart-29498984-09c4-41b1-a012-c0d6dd372fa6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650205458 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.650205458
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.1755578921
Short name T227
Test name
Test status
Simulation time 7412436155 ps
CPU time 108.31 seconds
Started Mar 31 03:46:27 PM PDT 24
Finished Mar 31 03:48:16 PM PDT 24
Peak memory 1061908 kb
Host smart-68a8e0d1-fd5f-43ac-957f-3c39782e8242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755578921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.1755578921
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.3825392700
Short name T228
Test name
Test status
Simulation time 7409899142 ps
CPU time 254.44 seconds
Started Mar 31 03:44:15 PM PDT 24
Finished Mar 31 03:48:30 PM PDT 24
Peak memory 1058376 kb
Host smart-10b8678f-e8d6-4268-8b5c-770169ef89f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825392700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.3825392700
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.2545692944
Short name T125
Test name
Test status
Simulation time 83675201 ps
CPU time 1.1 seconds
Started Mar 31 12:27:02 PM PDT 24
Finished Mar 31 12:27:03 PM PDT 24
Peak memory 203540 kb
Host smart-a6328ccb-7b69-4951-89bc-ecd693e86a69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545692944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.2545692944
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.4238392190
Short name T130
Test name
Test status
Simulation time 437763039 ps
CPU time 2.05 seconds
Started Mar 31 12:27:02 PM PDT 24
Finished Mar 31 12:27:04 PM PDT 24
Peak memory 203688 kb
Host smart-b0ea9559-593e-4d66-8f22-58aaa13a75ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238392190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.4238392190
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1937281061
Short name T126
Test name
Test status
Simulation time 44857479 ps
CPU time 1.32 seconds
Started Mar 31 12:28:01 PM PDT 24
Finished Mar 31 12:28:03 PM PDT 24
Peak memory 203508 kb
Host smart-c7ae0d71-d393-46ec-a10f-bc4fbdf0d3c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937281061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.1937281061
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.3893964425
Short name T132
Test name
Test status
Simulation time 256752132 ps
CPU time 1.37 seconds
Started Mar 31 12:27:02 PM PDT 24
Finished Mar 31 12:27:04 PM PDT 24
Peak memory 203500 kb
Host smart-ee26585d-cd4e-4f86-b118-a9ae0a5cf5ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893964425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.3893964425
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1380825751
Short name T139
Test name
Test status
Simulation time 313633914 ps
CPU time 1.66 seconds
Started Mar 31 12:27:00 PM PDT 24
Finished Mar 31 12:27:02 PM PDT 24
Peak memory 203440 kb
Host smart-81a3a611-e40d-4dd7-a69d-f6543b64c5ce
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380825751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.1380825751
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.118097702
Short name T166
Test name
Test status
Simulation time 2701761707 ps
CPU time 5.5 seconds
Started Mar 31 12:27:21 PM PDT 24
Finished Mar 31 12:27:28 PM PDT 24
Peak memory 203496 kb
Host smart-d9a5c701-1b51-45a9-b734-916afd82d219
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118097702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.118097702
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1322351947
Short name T1237
Test name
Test status
Simulation time 191758959 ps
CPU time 0.64 seconds
Started Mar 31 12:27:33 PM PDT 24
Finished Mar 31 12:27:33 PM PDT 24
Peak memory 203136 kb
Host smart-6ac2d561-15e9-48a4-b6e1-b4b98855da46
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322351947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.1322351947
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.937399877
Short name T1287
Test name
Test status
Simulation time 67204749 ps
CPU time 0.7 seconds
Started Mar 31 12:26:58 PM PDT 24
Finished Mar 31 12:26:59 PM PDT 24
Peak memory 203360 kb
Host smart-6976d144-3cc7-4d8a-8185-cf11b1cc28b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937399877 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.937399877
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1012459149
Short name T1286
Test name
Test status
Simulation time 106392365 ps
CPU time 0.83 seconds
Started Mar 31 12:26:56 PM PDT 24
Finished Mar 31 12:26:57 PM PDT 24
Peak memory 203280 kb
Host smart-34ddf3a2-a36c-4c84-a1ed-544cc509ecc5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012459149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.1012459149
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.902698185
Short name T1230
Test name
Test status
Simulation time 75335527 ps
CPU time 1.57 seconds
Started Mar 31 12:27:08 PM PDT 24
Finished Mar 31 12:27:10 PM PDT 24
Peak memory 203472 kb
Host smart-b1d558fa-e1ac-4edc-b520-abc759ac5ee6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902698185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.902698185
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1987206333
Short name T1225
Test name
Test status
Simulation time 53324888 ps
CPU time 1.2 seconds
Started Mar 31 12:27:24 PM PDT 24
Finished Mar 31 12:27:25 PM PDT 24
Peak memory 203472 kb
Host smart-bdc0939a-42d3-43a9-b4a1-1d01a84cd609
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987206333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.1987206333
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.3505920639
Short name T150
Test name
Test status
Simulation time 495858938 ps
CPU time 5.44 seconds
Started Mar 31 12:26:53 PM PDT 24
Finished Mar 31 12:26:58 PM PDT 24
Peak memory 203504 kb
Host smart-95cd33c4-e7a9-4345-a332-31dc4ddc6cc6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505920639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.3505920639
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.1350174922
Short name T1284
Test name
Test status
Simulation time 68666201 ps
CPU time 0.69 seconds
Started Mar 31 12:27:51 PM PDT 24
Finished Mar 31 12:27:53 PM PDT 24
Peak memory 203096 kb
Host smart-9afde2f0-addf-4493-a62e-51a38197ea5b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350174922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.1350174922
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.4142302213
Short name T1249
Test name
Test status
Simulation time 58662962 ps
CPU time 0.88 seconds
Started Mar 31 12:27:03 PM PDT 24
Finished Mar 31 12:27:04 PM PDT 24
Peak memory 203356 kb
Host smart-7f490aac-10f2-472d-aa96-e508d15eb1f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142302213 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.4142302213
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.980133773
Short name T1311
Test name
Test status
Simulation time 26308622 ps
CPU time 0.72 seconds
Started Mar 31 12:26:52 PM PDT 24
Finished Mar 31 12:26:53 PM PDT 24
Peak memory 203208 kb
Host smart-5bde5f17-9d12-42ef-81fe-d1d799970a96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980133773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.980133773
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.1971183655
Short name T1227
Test name
Test status
Simulation time 50696600 ps
CPU time 0.65 seconds
Started Mar 31 12:26:54 PM PDT 24
Finished Mar 31 12:26:55 PM PDT 24
Peak memory 203256 kb
Host smart-f47fecc0-6470-4250-8ec3-27bf4d9b1aeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971183655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.1971183655
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1331942773
Short name T159
Test name
Test status
Simulation time 21453599 ps
CPU time 0.81 seconds
Started Mar 31 12:27:01 PM PDT 24
Finished Mar 31 12:27:02 PM PDT 24
Peak memory 203336 kb
Host smart-5e22acf2-1a9d-4363-882c-45cd5f8a3204
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331942773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou
tstanding.1331942773
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1645560449
Short name T1308
Test name
Test status
Simulation time 61301685 ps
CPU time 0.9 seconds
Started Mar 31 12:26:58 PM PDT 24
Finished Mar 31 12:26:59 PM PDT 24
Peak memory 203320 kb
Host smart-e9c780e8-595e-4166-9ca1-b10fa342cccd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645560449 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.1645560449
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.3242574379
Short name T1290
Test name
Test status
Simulation time 40235310 ps
CPU time 0.78 seconds
Started Mar 31 12:27:46 PM PDT 24
Finished Mar 31 12:27:48 PM PDT 24
Peak memory 203200 kb
Host smart-6fa2f408-ff4e-449a-949f-91fc5e2246f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242574379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.3242574379
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.2074095572
Short name T1232
Test name
Test status
Simulation time 18838233 ps
CPU time 0.64 seconds
Started Mar 31 12:27:29 PM PDT 24
Finished Mar 31 12:27:29 PM PDT 24
Peak memory 203352 kb
Host smart-520f8c9a-6b75-4d0e-a2b6-a52a4e10a874
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074095572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.2074095572
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.4104737993
Short name T1240
Test name
Test status
Simulation time 55084653 ps
CPU time 1.2 seconds
Started Mar 31 12:26:53 PM PDT 24
Finished Mar 31 12:26:55 PM PDT 24
Peak memory 203552 kb
Host smart-7b02f0f2-6cd1-432b-8b3c-ee111b5d9731
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104737993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.4104737993
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.2996244373
Short name T137
Test name
Test status
Simulation time 64011409 ps
CPU time 1.45 seconds
Started Mar 31 12:26:51 PM PDT 24
Finished Mar 31 12:26:53 PM PDT 24
Peak memory 203604 kb
Host smart-8a8ef028-94d3-444f-b607-75e7ccc90add
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996244373 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.2996244373
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.1101585724
Short name T1236
Test name
Test status
Simulation time 31583853 ps
CPU time 0.63 seconds
Started Mar 31 12:27:32 PM PDT 24
Finished Mar 31 12:27:33 PM PDT 24
Peak memory 203236 kb
Host smart-ba93edbc-6568-45b2-a052-6156a97b4d7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101585724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.1101585724
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1365056823
Short name T158
Test name
Test status
Simulation time 63886358 ps
CPU time 0.79 seconds
Started Mar 31 12:27:02 PM PDT 24
Finished Mar 31 12:27:03 PM PDT 24
Peak memory 203328 kb
Host smart-c5c5b9d7-1117-4c24-a655-33f20bb875c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365056823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.1365056823
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.1357155635
Short name T1291
Test name
Test status
Simulation time 226607951 ps
CPU time 1.25 seconds
Started Mar 31 12:27:57 PM PDT 24
Finished Mar 31 12:27:59 PM PDT 24
Peak memory 203536 kb
Host smart-64701b9a-d76a-4b0a-92a4-c95938fbecec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357155635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.1357155635
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1231276107
Short name T1278
Test name
Test status
Simulation time 59407318 ps
CPU time 0.83 seconds
Started Mar 31 12:27:28 PM PDT 24
Finished Mar 31 12:27:28 PM PDT 24
Peak memory 203372 kb
Host smart-5e2e4d40-2939-4c7c-be5a-280fb38ecaca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231276107 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.1231276107
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.2616700548
Short name T155
Test name
Test status
Simulation time 19428986 ps
CPU time 0.72 seconds
Started Mar 31 12:26:53 PM PDT 24
Finished Mar 31 12:26:53 PM PDT 24
Peak memory 203236 kb
Host smart-c353acd0-b3b6-4141-8528-90f57fcdef84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616700548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.2616700548
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.1117502500
Short name T1276
Test name
Test status
Simulation time 15612801 ps
CPU time 0.7 seconds
Started Mar 31 12:27:02 PM PDT 24
Finished Mar 31 12:27:02 PM PDT 24
Peak memory 203248 kb
Host smart-1ac0f257-f068-4985-b39a-185da302c3b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117502500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.1117502500
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.1985649084
Short name T1242
Test name
Test status
Simulation time 61247879 ps
CPU time 0.86 seconds
Started Mar 31 12:27:27 PM PDT 24
Finished Mar 31 12:27:28 PM PDT 24
Peak memory 203336 kb
Host smart-6b70e5ca-9804-4f99-8b9c-07ed48eee1c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985649084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.1985649084
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.1455326155
Short name T1310
Test name
Test status
Simulation time 55606883 ps
CPU time 2.52 seconds
Started Mar 31 12:26:53 PM PDT 24
Finished Mar 31 12:26:56 PM PDT 24
Peak memory 203568 kb
Host smart-94e92998-d5e7-491c-a178-096fb9e2ad65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455326155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.1455326155
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.807146350
Short name T123
Test name
Test status
Simulation time 177058309 ps
CPU time 1.41 seconds
Started Mar 31 12:27:14 PM PDT 24
Finished Mar 31 12:27:16 PM PDT 24
Peak memory 203548 kb
Host smart-e4ee4dc4-0dee-4226-be1c-9f89446be2b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807146350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.807146350
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.3677386869
Short name T138
Test name
Test status
Simulation time 29081447 ps
CPU time 0.74 seconds
Started Mar 31 12:27:31 PM PDT 24
Finished Mar 31 12:27:32 PM PDT 24
Peak memory 203468 kb
Host smart-15fbecba-7aeb-4f34-986d-14ddbf4a344f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677386869 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.3677386869
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.913907557
Short name T149
Test name
Test status
Simulation time 330484840 ps
CPU time 0.76 seconds
Started Mar 31 12:27:46 PM PDT 24
Finished Mar 31 12:27:47 PM PDT 24
Peak memory 203160 kb
Host smart-f4542531-63bb-44c9-b8de-d8037a5d6001
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913907557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.913907557
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.1942590070
Short name T239
Test name
Test status
Simulation time 45727976 ps
CPU time 0.63 seconds
Started Mar 31 12:27:27 PM PDT 24
Finished Mar 31 12:27:28 PM PDT 24
Peak memory 203220 kb
Host smart-a13f3d31-2501-4a79-89ec-2dd88af1f9ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942590070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.1942590070
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3188078442
Short name T154
Test name
Test status
Simulation time 55063678 ps
CPU time 1.16 seconds
Started Mar 31 12:27:00 PM PDT 24
Finished Mar 31 12:27:01 PM PDT 24
Peak memory 203484 kb
Host smart-4bf3d2e6-591b-4f85-8b29-c09334fb586a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188078442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.3188078442
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.4211497340
Short name T105
Test name
Test status
Simulation time 640635096 ps
CPU time 1.6 seconds
Started Mar 31 12:26:52 PM PDT 24
Finished Mar 31 12:26:54 PM PDT 24
Peak memory 203712 kb
Host smart-9dea6fd8-81d9-4ab5-9dcf-c5ad541b5acc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211497340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.4211497340
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.2246449128
Short name T133
Test name
Test status
Simulation time 262799848 ps
CPU time 1.35 seconds
Started Mar 31 12:27:02 PM PDT 24
Finished Mar 31 12:27:03 PM PDT 24
Peak memory 203544 kb
Host smart-86f3f696-7dea-431d-a35c-e9e63b1379b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246449128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.2246449128
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3895713770
Short name T78
Test name
Test status
Simulation time 111857275 ps
CPU time 1.11 seconds
Started Mar 31 12:27:23 PM PDT 24
Finished Mar 31 12:27:25 PM PDT 24
Peak memory 203644 kb
Host smart-d0d1ff39-eb62-4fd4-a5ac-9db6ec767a09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895713770 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.3895713770
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.1566201754
Short name T144
Test name
Test status
Simulation time 28607178 ps
CPU time 0.67 seconds
Started Mar 31 12:27:03 PM PDT 24
Finished Mar 31 12:27:05 PM PDT 24
Peak memory 203192 kb
Host smart-8f4cc6e8-a60c-44e0-914a-de75908bc81b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566201754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.1566201754
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.2658297222
Short name T235
Test name
Test status
Simulation time 17476086 ps
CPU time 0.65 seconds
Started Mar 31 12:27:42 PM PDT 24
Finished Mar 31 12:27:43 PM PDT 24
Peak memory 203220 kb
Host smart-0f8d9ff1-57fe-4a12-9ec4-13ce3ba94615
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658297222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.2658297222
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2437506233
Short name T1226
Test name
Test status
Simulation time 30260612 ps
CPU time 0.8 seconds
Started Mar 31 12:27:26 PM PDT 24
Finished Mar 31 12:27:27 PM PDT 24
Peak memory 203264 kb
Host smart-492405c8-9b68-4a38-93e1-fe016a0d3be7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437506233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.2437506233
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.4050449812
Short name T1279
Test name
Test status
Simulation time 110199745 ps
CPU time 1.32 seconds
Started Mar 31 12:27:35 PM PDT 24
Finished Mar 31 12:27:36 PM PDT 24
Peak memory 203572 kb
Host smart-c12cd79e-91dc-4df6-ade4-835bea52a85f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050449812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.4050449812
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.2947988634
Short name T136
Test name
Test status
Simulation time 19156661 ps
CPU time 0.77 seconds
Started Mar 31 12:27:30 PM PDT 24
Finished Mar 31 12:27:30 PM PDT 24
Peak memory 203384 kb
Host smart-6877ce88-d88d-49af-bdba-d470d5aefb58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947988634 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.2947988634
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.3327731598
Short name T1257
Test name
Test status
Simulation time 24994978 ps
CPU time 0.68 seconds
Started Mar 31 12:27:19 PM PDT 24
Finished Mar 31 12:27:20 PM PDT 24
Peak memory 203212 kb
Host smart-71407294-5589-4fcc-b18f-1ce6a40441eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327731598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.3327731598
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.386751160
Short name T1247
Test name
Test status
Simulation time 19928307 ps
CPU time 0.65 seconds
Started Mar 31 12:27:02 PM PDT 24
Finished Mar 31 12:27:03 PM PDT 24
Peak memory 203264 kb
Host smart-4113c523-f9f1-4ac5-b81f-bf07f2a779f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386751160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.386751160
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2905399729
Short name T1307
Test name
Test status
Simulation time 20757599 ps
CPU time 0.8 seconds
Started Mar 31 12:27:01 PM PDT 24
Finished Mar 31 12:27:01 PM PDT 24
Peak memory 203284 kb
Host smart-882a1aaf-520e-45e7-b4ac-20f51fa253b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905399729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o
utstanding.2905399729
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.3809442415
Short name T1243
Test name
Test status
Simulation time 223740501 ps
CPU time 1.37 seconds
Started Mar 31 12:27:36 PM PDT 24
Finished Mar 31 12:27:38 PM PDT 24
Peak memory 203496 kb
Host smart-39490caf-8a24-4c10-bf3a-c033fcbe97bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809442415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.3809442415
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3902615773
Short name T223
Test name
Test status
Simulation time 297103699 ps
CPU time 1.9 seconds
Started Mar 31 12:27:24 PM PDT 24
Finished Mar 31 12:27:27 PM PDT 24
Peak memory 203536 kb
Host smart-91afef73-b15a-4859-81a0-02cfb27bd37f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902615773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.3902615773
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.4065733089
Short name T1254
Test name
Test status
Simulation time 85483828 ps
CPU time 1.29 seconds
Started Mar 31 12:27:20 PM PDT 24
Finished Mar 31 12:27:22 PM PDT 24
Peak memory 203636 kb
Host smart-989148cc-c08f-468d-8434-f5f4f57f08e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065733089 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.4065733089
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1316539893
Short name T76
Test name
Test status
Simulation time 15633129 ps
CPU time 0.66 seconds
Started Mar 31 12:27:13 PM PDT 24
Finished Mar 31 12:27:15 PM PDT 24
Peak memory 203228 kb
Host smart-ad331e3e-c2a1-4ebd-a596-3526a1eadd71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316539893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.1316539893
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.3110117685
Short name T232
Test name
Test status
Simulation time 71561038 ps
CPU time 0.62 seconds
Started Mar 31 12:27:00 PM PDT 24
Finished Mar 31 12:27:01 PM PDT 24
Peak memory 203224 kb
Host smart-abac484e-5e9a-4ff9-8fbf-0fc532c3a6e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110117685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.3110117685
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1596237830
Short name T1277
Test name
Test status
Simulation time 118113378 ps
CPU time 0.79 seconds
Started Mar 31 12:27:29 PM PDT 24
Finished Mar 31 12:27:29 PM PDT 24
Peak memory 203304 kb
Host smart-1a1a7d77-390e-4564-aed6-c89d38bde0fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596237830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.1596237830
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.3775387099
Short name T1297
Test name
Test status
Simulation time 162341404 ps
CPU time 1.78 seconds
Started Mar 31 12:27:32 PM PDT 24
Finished Mar 31 12:27:34 PM PDT 24
Peak memory 203560 kb
Host smart-9223c0e7-adc8-4eb1-8dd1-73266c777a47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775387099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.3775387099
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.792973558
Short name T168
Test name
Test status
Simulation time 293028580 ps
CPU time 0.76 seconds
Started Mar 31 12:27:06 PM PDT 24
Finished Mar 31 12:27:06 PM PDT 24
Peak memory 203388 kb
Host smart-343ea86a-3657-4e97-9a5e-4ac022105739
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792973558 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.792973558
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.1885782559
Short name T151
Test name
Test status
Simulation time 19796663 ps
CPU time 0.75 seconds
Started Mar 31 12:27:40 PM PDT 24
Finished Mar 31 12:27:41 PM PDT 24
Peak memory 203196 kb
Host smart-accff41c-9030-4425-ac48-3280f924d77d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885782559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.1885782559
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.1134148242
Short name T1214
Test name
Test status
Simulation time 25225566 ps
CPU time 0.63 seconds
Started Mar 31 12:27:20 PM PDT 24
Finished Mar 31 12:27:22 PM PDT 24
Peak memory 203200 kb
Host smart-a0fe99d1-5c85-4478-8853-ee8613153d83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134148242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.1134148242
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.558666457
Short name T1313
Test name
Test status
Simulation time 57043117 ps
CPU time 0.83 seconds
Started Mar 31 12:26:54 PM PDT 24
Finished Mar 31 12:26:55 PM PDT 24
Peak memory 203268 kb
Host smart-40900a5c-d63f-47bb-b9e8-90eb0eda96bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558666457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_ou
tstanding.558666457
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.2423941780
Short name T1217
Test name
Test status
Simulation time 96271404 ps
CPU time 1.2 seconds
Started Mar 31 12:27:10 PM PDT 24
Finished Mar 31 12:27:12 PM PDT 24
Peak memory 203556 kb
Host smart-a5b3245b-38c6-47cc-a7d5-f6ca3f6f9596
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423941780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.2423941780
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.1909279248
Short name T1299
Test name
Test status
Simulation time 183451378 ps
CPU time 1.41 seconds
Started Mar 31 12:27:34 PM PDT 24
Finished Mar 31 12:27:35 PM PDT 24
Peak memory 203556 kb
Host smart-93ab824b-1270-452a-8ef8-7b965524eb47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909279248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.1909279248
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3615684889
Short name T1289
Test name
Test status
Simulation time 121095599 ps
CPU time 1.62 seconds
Started Mar 31 12:27:27 PM PDT 24
Finished Mar 31 12:27:29 PM PDT 24
Peak memory 203640 kb
Host smart-9ba0cc2f-b560-47c8-9783-a47f8fa3ea5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615684889 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.3615684889
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.3219806249
Short name T140
Test name
Test status
Simulation time 19516540 ps
CPU time 0.72 seconds
Started Mar 31 12:27:06 PM PDT 24
Finished Mar 31 12:27:07 PM PDT 24
Peak memory 203448 kb
Host smart-f6d21814-47f5-41b4-9f29-179724a5abec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219806249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.3219806249
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.1414506169
Short name T1282
Test name
Test status
Simulation time 14894928 ps
CPU time 0.7 seconds
Started Mar 31 12:26:54 PM PDT 24
Finished Mar 31 12:26:55 PM PDT 24
Peak memory 203192 kb
Host smart-361958df-2627-4065-8404-f421d9316e2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414506169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.1414506169
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.1356292698
Short name T1248
Test name
Test status
Simulation time 39280609 ps
CPU time 0.81 seconds
Started Mar 31 12:26:53 PM PDT 24
Finished Mar 31 12:26:54 PM PDT 24
Peak memory 203312 kb
Host smart-778f4dec-555f-4649-b897-c118118ce639
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356292698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.1356292698
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.3234790490
Short name T127
Test name
Test status
Simulation time 27358845 ps
CPU time 1.36 seconds
Started Mar 31 12:27:06 PM PDT 24
Finished Mar 31 12:27:07 PM PDT 24
Peak memory 203508 kb
Host smart-173a78a2-1e1b-486a-860f-49cd9a8934b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234790490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.3234790490
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.3114008458
Short name T121
Test name
Test status
Simulation time 273480366 ps
CPU time 1.33 seconds
Started Mar 31 12:27:50 PM PDT 24
Finished Mar 31 12:27:52 PM PDT 24
Peak memory 203572 kb
Host smart-d5ef6ca8-63b3-4272-8b89-f2b611068a7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114008458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.3114008458
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2458659172
Short name T128
Test name
Test status
Simulation time 224934982 ps
CPU time 1.31 seconds
Started Mar 31 12:27:03 PM PDT 24
Finished Mar 31 12:27:05 PM PDT 24
Peak memory 203584 kb
Host smart-445a6763-7260-4313-83c4-0b8bf5f93a0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458659172 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.2458659172
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.2548072637
Short name T147
Test name
Test status
Simulation time 88801720 ps
CPU time 0.75 seconds
Started Mar 31 12:27:28 PM PDT 24
Finished Mar 31 12:27:29 PM PDT 24
Peak memory 203208 kb
Host smart-5624ac79-f0e5-4935-b44f-e405917bb71b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548072637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.2548072637
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.2140086869
Short name T1256
Test name
Test status
Simulation time 15293368 ps
CPU time 0.67 seconds
Started Mar 31 12:26:58 PM PDT 24
Finished Mar 31 12:26:59 PM PDT 24
Peak memory 203268 kb
Host smart-4aed21b1-3b80-463e-9ec4-86fa1fca37dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140086869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.2140086869
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3842572868
Short name T1252
Test name
Test status
Simulation time 81650245 ps
CPU time 0.98 seconds
Started Mar 31 12:27:06 PM PDT 24
Finished Mar 31 12:27:08 PM PDT 24
Peak memory 203484 kb
Host smart-7aff4b75-9d90-405f-9809-e8f4d57f0de4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842572868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.3842572868
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.3291100932
Short name T1312
Test name
Test status
Simulation time 142977188 ps
CPU time 2.64 seconds
Started Mar 31 12:27:22 PM PDT 24
Finished Mar 31 12:27:25 PM PDT 24
Peak memory 203520 kb
Host smart-76a79875-b3c1-41c7-afc2-a765f7d97df0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291100932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.3291100932
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.3083496657
Short name T120
Test name
Test status
Simulation time 187201892 ps
CPU time 2.11 seconds
Started Mar 31 12:27:06 PM PDT 24
Finished Mar 31 12:27:08 PM PDT 24
Peak memory 203544 kb
Host smart-995fd645-b7b7-4df9-9c8a-ed6f52a09b10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083496657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.3083496657
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3536165710
Short name T146
Test name
Test status
Simulation time 38507284 ps
CPU time 1.67 seconds
Started Mar 31 12:27:35 PM PDT 24
Finished Mar 31 12:27:36 PM PDT 24
Peak memory 203452 kb
Host smart-f8564e61-8c15-4035-9eb1-05bbdd83191b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536165710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.3536165710
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.3934997673
Short name T1220
Test name
Test status
Simulation time 395636590 ps
CPU time 2.91 seconds
Started Mar 31 12:27:03 PM PDT 24
Finished Mar 31 12:27:07 PM PDT 24
Peak memory 203388 kb
Host smart-98d55a0c-3f00-485f-acbc-67d6fdd3a952
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934997673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.3934997673
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.902688042
Short name T1233
Test name
Test status
Simulation time 40444281 ps
CPU time 0.74 seconds
Started Mar 31 12:26:52 PM PDT 24
Finished Mar 31 12:26:53 PM PDT 24
Peak memory 203208 kb
Host smart-d9fd6578-c560-4534-92d6-1e313f0f465d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902688042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.902688042
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.4271473641
Short name T169
Test name
Test status
Simulation time 137433763 ps
CPU time 0.92 seconds
Started Mar 31 12:26:59 PM PDT 24
Finished Mar 31 12:27:00 PM PDT 24
Peak memory 203400 kb
Host smart-0ea89a96-9fd8-4411-bf99-b9d8c0305e11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271473641 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.4271473641
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.275446298
Short name T1265
Test name
Test status
Simulation time 200599044 ps
CPU time 0.71 seconds
Started Mar 31 12:27:04 PM PDT 24
Finished Mar 31 12:27:05 PM PDT 24
Peak memory 203208 kb
Host smart-6d255e1e-14df-4187-b4d5-082ff42b6380
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275446298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.275446298
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.3236587285
Short name T1218
Test name
Test status
Simulation time 20335189 ps
CPU time 0.64 seconds
Started Mar 31 12:26:57 PM PDT 24
Finished Mar 31 12:26:58 PM PDT 24
Peak memory 203236 kb
Host smart-41412c0c-8209-4ad3-90f7-8b7bd8117f19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236587285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.3236587285
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2949078755
Short name T1238
Test name
Test status
Simulation time 58855653 ps
CPU time 0.78 seconds
Started Mar 31 12:27:52 PM PDT 24
Finished Mar 31 12:27:53 PM PDT 24
Peak memory 203296 kb
Host smart-449a3e24-cd68-4a9b-962b-d8b4c2d01a58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949078755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.2949078755
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.2940851686
Short name T167
Test name
Test status
Simulation time 290286552 ps
CPU time 2.26 seconds
Started Mar 31 12:27:51 PM PDT 24
Finished Mar 31 12:27:55 PM PDT 24
Peak memory 203548 kb
Host smart-9f99c271-6133-4c3a-afa5-dd2e8da20c01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940851686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.2940851686
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.1134212396
Short name T236
Test name
Test status
Simulation time 16925763 ps
CPU time 0.69 seconds
Started Mar 31 12:27:27 PM PDT 24
Finished Mar 31 12:27:28 PM PDT 24
Peak memory 203240 kb
Host smart-2e6288a5-5b2a-4074-bc9d-0ac71900bf24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134212396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.1134212396
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.3741369582
Short name T1221
Test name
Test status
Simulation time 42760184 ps
CPU time 0.63 seconds
Started Mar 31 12:27:38 PM PDT 24
Finished Mar 31 12:27:39 PM PDT 24
Peak memory 203244 kb
Host smart-bfaa41ac-2417-432d-9808-2000c6f0695b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741369582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.3741369582
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.4055271308
Short name T238
Test name
Test status
Simulation time 19245422 ps
CPU time 0.65 seconds
Started Mar 31 12:27:00 PM PDT 24
Finished Mar 31 12:27:06 PM PDT 24
Peak memory 203224 kb
Host smart-62a63b8c-58a3-4700-a4f1-35f1e54fc8a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055271308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.4055271308
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.3750145250
Short name T1303
Test name
Test status
Simulation time 17030351 ps
CPU time 0.65 seconds
Started Mar 31 12:27:00 PM PDT 24
Finished Mar 31 12:27:00 PM PDT 24
Peak memory 203264 kb
Host smart-b3635638-f506-4f26-80c5-4643e0d7f49c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750145250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.3750145250
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.498627918
Short name T1304
Test name
Test status
Simulation time 17786597 ps
CPU time 0.64 seconds
Started Mar 31 12:27:03 PM PDT 24
Finished Mar 31 12:27:04 PM PDT 24
Peak memory 203200 kb
Host smart-f1a7e780-56b3-4942-8bad-840e3214c107
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498627918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.498627918
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.1485955480
Short name T1246
Test name
Test status
Simulation time 43410815 ps
CPU time 0.68 seconds
Started Mar 31 12:27:30 PM PDT 24
Finished Mar 31 12:27:31 PM PDT 24
Peak memory 203252 kb
Host smart-0ff456cd-8254-4db6-a85c-77e376bae445
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485955480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.1485955480
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.1485013824
Short name T1275
Test name
Test status
Simulation time 36214794 ps
CPU time 0.65 seconds
Started Mar 31 12:27:00 PM PDT 24
Finished Mar 31 12:27:01 PM PDT 24
Peak memory 203240 kb
Host smart-e5521843-94f5-49e4-81e6-7ddf5f57ad4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485013824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.1485013824
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.3776776737
Short name T1301
Test name
Test status
Simulation time 17652516 ps
CPU time 0.64 seconds
Started Mar 31 12:27:02 PM PDT 24
Finished Mar 31 12:27:03 PM PDT 24
Peak memory 203556 kb
Host smart-9470f774-a057-4770-9460-a2c5c9c68b88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776776737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.3776776737
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.2490116751
Short name T1292
Test name
Test status
Simulation time 80029991 ps
CPU time 0.66 seconds
Started Mar 31 12:27:19 PM PDT 24
Finished Mar 31 12:27:20 PM PDT 24
Peak memory 203192 kb
Host smart-587cd7ac-57f3-4fe5-a799-7ba4f2e47a7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490116751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.2490116751
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.2815685500
Short name T1215
Test name
Test status
Simulation time 52422806 ps
CPU time 0.68 seconds
Started Mar 31 12:28:26 PM PDT 24
Finished Mar 31 12:28:27 PM PDT 24
Peak memory 201768 kb
Host smart-53643395-5131-4c48-a968-7612618a45ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815685500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.2815685500
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2855367042
Short name T1300
Test name
Test status
Simulation time 215369671 ps
CPU time 1.24 seconds
Started Mar 31 12:27:17 PM PDT 24
Finished Mar 31 12:27:19 PM PDT 24
Peak memory 203492 kb
Host smart-faed551f-7eb8-467a-a3e0-2ffc4c79a2b6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855367042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.2855367042
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.4111837048
Short name T1244
Test name
Test status
Simulation time 69883637 ps
CPU time 2.6 seconds
Started Mar 31 12:27:23 PM PDT 24
Finished Mar 31 12:27:26 PM PDT 24
Peak memory 203620 kb
Host smart-cb66de20-9bd3-429d-9c33-145b5b9dd5cf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111837048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.4111837048
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.3631412079
Short name T1245
Test name
Test status
Simulation time 22768068 ps
CPU time 0.67 seconds
Started Mar 31 12:26:52 PM PDT 24
Finished Mar 31 12:26:53 PM PDT 24
Peak memory 203048 kb
Host smart-6ee7fc03-a3b3-4c6d-a28e-e9d2b4872c3c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631412079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.3631412079
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.2129351320
Short name T1305
Test name
Test status
Simulation time 35359282 ps
CPU time 1.11 seconds
Started Mar 31 12:27:36 PM PDT 24
Finished Mar 31 12:27:37 PM PDT 24
Peak memory 203576 kb
Host smart-5e262ade-aac3-4679-9838-588751d61578
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129351320 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.2129351320
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.32934596
Short name T1271
Test name
Test status
Simulation time 24648648 ps
CPU time 0.72 seconds
Started Mar 31 12:26:52 PM PDT 24
Finished Mar 31 12:26:53 PM PDT 24
Peak memory 203200 kb
Host smart-6c80e206-5ee7-4860-be07-a9d8c986fa52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32934596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.32934596
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.891089205
Short name T1224
Test name
Test status
Simulation time 22017104 ps
CPU time 0.67 seconds
Started Mar 31 12:27:24 PM PDT 24
Finished Mar 31 12:27:25 PM PDT 24
Peak memory 203244 kb
Host smart-40d39518-8c51-4709-8ad6-bfb6f72e3877
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891089205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.891089205
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1475185623
Short name T1264
Test name
Test status
Simulation time 32395295 ps
CPU time 0.78 seconds
Started Mar 31 12:26:54 PM PDT 24
Finished Mar 31 12:26:55 PM PDT 24
Peak memory 203316 kb
Host smart-c8e4bcfa-9ef6-4a23-8d6e-7da6d55eaa4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475185623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.1475185623
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.3028244488
Short name T1272
Test name
Test status
Simulation time 331030736 ps
CPU time 2.11 seconds
Started Mar 31 12:26:50 PM PDT 24
Finished Mar 31 12:26:53 PM PDT 24
Peak memory 203548 kb
Host smart-a9ab4760-41f6-48ee-a3e5-a5dffbff2dbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028244488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.3028244488
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2108945802
Short name T221
Test name
Test status
Simulation time 136318127 ps
CPU time 2.11 seconds
Started Mar 31 12:27:17 PM PDT 24
Finished Mar 31 12:27:20 PM PDT 24
Peak memory 203692 kb
Host smart-03c03271-b8ab-4238-818d-7b78d666ad4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108945802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.2108945802
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.1000587377
Short name T1302
Test name
Test status
Simulation time 19350852 ps
CPU time 0.65 seconds
Started Mar 31 12:27:17 PM PDT 24
Finished Mar 31 12:27:19 PM PDT 24
Peak memory 203280 kb
Host smart-ca992857-6e27-4b92-918e-c3d3ea0e1c9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000587377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.1000587377
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.302300241
Short name T1262
Test name
Test status
Simulation time 38333149 ps
CPU time 0.64 seconds
Started Mar 31 12:27:41 PM PDT 24
Finished Mar 31 12:27:42 PM PDT 24
Peak memory 203244 kb
Host smart-70bc1514-051c-4ebe-9490-2405627430af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302300241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.302300241
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.3929028961
Short name T240
Test name
Test status
Simulation time 229244253 ps
CPU time 0.65 seconds
Started Mar 31 12:27:00 PM PDT 24
Finished Mar 31 12:27:00 PM PDT 24
Peak memory 203184 kb
Host smart-0654a2ee-4460-4445-9b58-a2a0fc9665ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929028961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.3929028961
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.2255763420
Short name T1231
Test name
Test status
Simulation time 22311729 ps
CPU time 0.73 seconds
Started Mar 31 12:27:46 PM PDT 24
Finished Mar 31 12:27:48 PM PDT 24
Peak memory 203260 kb
Host smart-18749142-4b64-4d2f-ba0b-e29f2e47c8ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255763420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.2255763420
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.2225383048
Short name T1216
Test name
Test status
Simulation time 58016942 ps
CPU time 0.68 seconds
Started Mar 31 12:26:54 PM PDT 24
Finished Mar 31 12:26:55 PM PDT 24
Peak memory 203236 kb
Host smart-20df5a4c-75ea-42be-aaf7-506762c3dc91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225383048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.2225383048
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.1713965484
Short name T1267
Test name
Test status
Simulation time 120488563 ps
CPU time 0.64 seconds
Started Mar 31 12:27:44 PM PDT 24
Finished Mar 31 12:27:45 PM PDT 24
Peak memory 203244 kb
Host smart-789a5eaf-97e9-44a3-a9e4-83b4deae0714
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713965484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.1713965484
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.2650354161
Short name T1229
Test name
Test status
Simulation time 19616901 ps
CPU time 0.63 seconds
Started Mar 31 12:27:03 PM PDT 24
Finished Mar 31 12:27:03 PM PDT 24
Peak memory 203220 kb
Host smart-4322c7d3-cabf-4484-b089-56bc10716c12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650354161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.2650354161
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.369512073
Short name T1296
Test name
Test status
Simulation time 40503057 ps
CPU time 0.66 seconds
Started Mar 31 12:27:51 PM PDT 24
Finished Mar 31 12:27:57 PM PDT 24
Peak memory 203248 kb
Host smart-8787f329-ef92-4c03-9d22-05280ba83e26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369512073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.369512073
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.2650187551
Short name T1219
Test name
Test status
Simulation time 17449308 ps
CPU time 0.67 seconds
Started Mar 31 12:27:26 PM PDT 24
Finished Mar 31 12:27:27 PM PDT 24
Peak memory 203260 kb
Host smart-3a67169b-ba9d-4676-b6ed-6d7bbd7022f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650187551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.2650187551
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.2681098230
Short name T1259
Test name
Test status
Simulation time 19007522 ps
CPU time 0.65 seconds
Started Mar 31 12:28:44 PM PDT 24
Finished Mar 31 12:28:44 PM PDT 24
Peak memory 203128 kb
Host smart-abebebec-d839-4910-994c-9aad296a0e97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681098230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.2681098230
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1757882130
Short name T143
Test name
Test status
Simulation time 85097651 ps
CPU time 1.14 seconds
Started Mar 31 12:27:01 PM PDT 24
Finished Mar 31 12:27:02 PM PDT 24
Peak memory 203424 kb
Host smart-d1ddc6aa-5fe0-40ec-a180-b63d911a60d0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757882130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.1757882130
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.1935650632
Short name T1235
Test name
Test status
Simulation time 35693311 ps
CPU time 0.67 seconds
Started Mar 31 12:26:56 PM PDT 24
Finished Mar 31 12:26:56 PM PDT 24
Peak memory 203008 kb
Host smart-55773f45-41d0-41db-95ae-00871aa2db56
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935650632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.1935650632
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.4148491206
Short name T1239
Test name
Test status
Simulation time 76329470 ps
CPU time 1.08 seconds
Started Mar 31 12:27:18 PM PDT 24
Finished Mar 31 12:27:20 PM PDT 24
Peak memory 203620 kb
Host smart-4b7fb1db-1117-4e59-a275-8b2d118881e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148491206 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.4148491206
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.550225940
Short name T141
Test name
Test status
Simulation time 47378813 ps
CPU time 0.67 seconds
Started Mar 31 12:26:52 PM PDT 24
Finished Mar 31 12:26:53 PM PDT 24
Peak memory 203244 kb
Host smart-6d6551d0-8740-447b-ba95-012828dbf0db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550225940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.550225940
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.213111704
Short name T1298
Test name
Test status
Simulation time 18815543 ps
CPU time 0.67 seconds
Started Mar 31 12:26:53 PM PDT 24
Finished Mar 31 12:26:54 PM PDT 24
Peak memory 203268 kb
Host smart-7b3122e2-eca7-4a90-9e6d-cfebc1918889
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213111704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.213111704
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1831643320
Short name T1266
Test name
Test status
Simulation time 222566976 ps
CPU time 1.11 seconds
Started Mar 31 12:27:17 PM PDT 24
Finished Mar 31 12:27:18 PM PDT 24
Peak memory 203620 kb
Host smart-3c7710df-f130-449a-b72d-56197054cef6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831643320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.1831643320
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.1338832677
Short name T1263
Test name
Test status
Simulation time 49500847 ps
CPU time 1.18 seconds
Started Mar 31 12:27:30 PM PDT 24
Finished Mar 31 12:27:32 PM PDT 24
Peak memory 203388 kb
Host smart-7c7b7d1a-f721-4279-99cc-5a22fa5110cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338832677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.1338832677
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.2354602991
Short name T224
Test name
Test status
Simulation time 152613600 ps
CPU time 1.36 seconds
Started Mar 31 12:27:03 PM PDT 24
Finished Mar 31 12:27:05 PM PDT 24
Peak memory 203588 kb
Host smart-ba705407-b6b6-495f-bf3b-2d44eb3fd0ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354602991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.2354602991
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.3580119613
Short name T1260
Test name
Test status
Simulation time 26569878 ps
CPU time 0.67 seconds
Started Mar 31 12:28:26 PM PDT 24
Finished Mar 31 12:28:27 PM PDT 24
Peak memory 201644 kb
Host smart-fa8020ce-c90f-4e2e-b43a-a3c3de4b3dba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580119613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.3580119613
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.3729635959
Short name T1293
Test name
Test status
Simulation time 93334872 ps
CPU time 0.69 seconds
Started Mar 31 12:27:47 PM PDT 24
Finished Mar 31 12:27:48 PM PDT 24
Peak memory 203192 kb
Host smart-4746346e-305e-45b4-b4d8-c8bc606bdb60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729635959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.3729635959
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.2745622442
Short name T1253
Test name
Test status
Simulation time 30274423 ps
CPU time 0.68 seconds
Started Mar 31 12:28:44 PM PDT 24
Finished Mar 31 12:28:45 PM PDT 24
Peak memory 203124 kb
Host smart-5c9d6b97-5f58-4eec-8525-1013bda1c5c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745622442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.2745622442
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.2963229004
Short name T237
Test name
Test status
Simulation time 22539782 ps
CPU time 0.66 seconds
Started Mar 31 12:27:19 PM PDT 24
Finished Mar 31 12:27:21 PM PDT 24
Peak memory 203332 kb
Host smart-584a413b-39e1-4ea7-affe-b116577e279f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963229004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.2963229004
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.1195027398
Short name T1223
Test name
Test status
Simulation time 27690723 ps
CPU time 0.65 seconds
Started Mar 31 12:27:51 PM PDT 24
Finished Mar 31 12:27:53 PM PDT 24
Peak memory 203248 kb
Host smart-b9470f24-11e3-42ca-b522-3957b9582087
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195027398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.1195027398
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.437894294
Short name T1294
Test name
Test status
Simulation time 74931854 ps
CPU time 0.65 seconds
Started Mar 31 12:26:54 PM PDT 24
Finished Mar 31 12:26:59 PM PDT 24
Peak memory 203264 kb
Host smart-66a0819b-2af5-4b2c-8b01-c95e9a52fedb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437894294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.437894294
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.3254491092
Short name T1250
Test name
Test status
Simulation time 17976680 ps
CPU time 0.68 seconds
Started Mar 31 12:28:26 PM PDT 24
Finished Mar 31 12:28:27 PM PDT 24
Peak memory 202728 kb
Host smart-5ddf8406-3afd-489c-9fb0-b7838259496a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254491092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.3254491092
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.3913290487
Short name T1273
Test name
Test status
Simulation time 16882226 ps
CPU time 0.61 seconds
Started Mar 31 12:28:44 PM PDT 24
Finished Mar 31 12:28:45 PM PDT 24
Peak memory 203128 kb
Host smart-f379ab48-48d9-4152-ae60-c9eff52fe76e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913290487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.3913290487
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.1434805538
Short name T1309
Test name
Test status
Simulation time 16862639 ps
CPU time 0.64 seconds
Started Mar 31 12:28:46 PM PDT 24
Finished Mar 31 12:28:52 PM PDT 24
Peak memory 203192 kb
Host smart-5a193087-93ad-46dd-81a2-7db56572ed68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434805538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.1434805538
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.362267015
Short name T1268
Test name
Test status
Simulation time 32355577 ps
CPU time 0.66 seconds
Started Mar 31 12:27:03 PM PDT 24
Finished Mar 31 12:27:04 PM PDT 24
Peak memory 203256 kb
Host smart-32e64ffc-7fd5-4122-85b3-899ee333869f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362267015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.362267015
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3417492490
Short name T170
Test name
Test status
Simulation time 122502890 ps
CPU time 0.75 seconds
Started Mar 31 12:27:10 PM PDT 24
Finished Mar 31 12:27:11 PM PDT 24
Peak memory 203404 kb
Host smart-14ab2131-f333-4d4c-bd17-7342c65f4b70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417492490 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.3417492490
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.274388741
Short name T77
Test name
Test status
Simulation time 60528946 ps
CPU time 0.73 seconds
Started Mar 31 12:27:18 PM PDT 24
Finished Mar 31 12:27:19 PM PDT 24
Peak memory 203372 kb
Host smart-92cc0fcf-4c2e-4a69-9467-778e95716b3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274388741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.274388741
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.559540014
Short name T234
Test name
Test status
Simulation time 80127612 ps
CPU time 0.61 seconds
Started Mar 31 12:27:06 PM PDT 24
Finished Mar 31 12:27:06 PM PDT 24
Peak memory 203272 kb
Host smart-1e3a1a23-e601-41b0-bc32-1495201158a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559540014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.559540014
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.2005855585
Short name T156
Test name
Test status
Simulation time 119574813 ps
CPU time 1 seconds
Started Mar 31 12:27:50 PM PDT 24
Finished Mar 31 12:27:56 PM PDT 24
Peak memory 203508 kb
Host smart-3a638bff-7607-46df-91cd-56d2c21e61e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005855585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.2005855585
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.544959829
Short name T104
Test name
Test status
Simulation time 76766198 ps
CPU time 1.9 seconds
Started Mar 31 12:27:42 PM PDT 24
Finished Mar 31 12:27:44 PM PDT 24
Peak memory 203528 kb
Host smart-b8754dbf-c99d-425b-9b8f-be0b22474c20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544959829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.544959829
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3652867443
Short name T131
Test name
Test status
Simulation time 49725797 ps
CPU time 1.31 seconds
Started Mar 31 12:27:31 PM PDT 24
Finished Mar 31 12:27:33 PM PDT 24
Peak memory 203580 kb
Host smart-f8be71c5-20ab-49bf-91a6-fe909bfa0cb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652867443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.3652867443
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.2160008784
Short name T1255
Test name
Test status
Simulation time 40349888 ps
CPU time 1.09 seconds
Started Mar 31 12:27:00 PM PDT 24
Finished Mar 31 12:27:02 PM PDT 24
Peak memory 203640 kb
Host smart-a3cb5328-d52d-47a0-bbb7-6a76f5b92d74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160008784 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.2160008784
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.3914600309
Short name T142
Test name
Test status
Simulation time 212000990 ps
CPU time 0.73 seconds
Started Mar 31 12:27:34 PM PDT 24
Finished Mar 31 12:27:35 PM PDT 24
Peak memory 203236 kb
Host smart-f55a6750-e6d6-481e-8dd9-6e7cacafe899
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914600309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.3914600309
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.2395068516
Short name T1306
Test name
Test status
Simulation time 23646964 ps
CPU time 0.63 seconds
Started Mar 31 12:26:59 PM PDT 24
Finished Mar 31 12:27:00 PM PDT 24
Peak memory 203220 kb
Host smart-c6617202-0fe2-4c4b-8847-7fd49c0e0b10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395068516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.2395068516
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.3512571307
Short name T1241
Test name
Test status
Simulation time 168534430 ps
CPU time 1.1 seconds
Started Mar 31 12:27:48 PM PDT 24
Finished Mar 31 12:27:49 PM PDT 24
Peak memory 203556 kb
Host smart-f0718e93-ba68-439a-8135-bf6c059b5e7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512571307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.3512571307
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.2122981255
Short name T1288
Test name
Test status
Simulation time 130260860 ps
CPU time 2.27 seconds
Started Mar 31 12:27:09 PM PDT 24
Finished Mar 31 12:27:12 PM PDT 24
Peak memory 203528 kb
Host smart-35bae242-4b16-47cd-ae02-1ce26f51063b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122981255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.2122981255
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.3106195586
Short name T134
Test name
Test status
Simulation time 273732470 ps
CPU time 1.39 seconds
Started Mar 31 12:27:51 PM PDT 24
Finished Mar 31 12:27:54 PM PDT 24
Peak memory 203588 kb
Host smart-822f880c-74ff-4fc3-b5a9-c2094a92badf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106195586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.3106195586
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.742153322
Short name T1285
Test name
Test status
Simulation time 42101191 ps
CPU time 0.91 seconds
Started Mar 31 12:27:23 PM PDT 24
Finished Mar 31 12:27:24 PM PDT 24
Peak memory 203460 kb
Host smart-02f6f1f2-b113-4e98-8cc3-bb009e25fc4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742153322 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.742153322
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.3719480339
Short name T152
Test name
Test status
Simulation time 24527101 ps
CPU time 0.74 seconds
Started Mar 31 12:27:08 PM PDT 24
Finished Mar 31 12:27:09 PM PDT 24
Peak memory 203184 kb
Host smart-0d80b538-f444-4811-b323-8003910ba05d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719480339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.3719480339
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.1118019791
Short name T1283
Test name
Test status
Simulation time 63099589 ps
CPU time 0.69 seconds
Started Mar 31 12:27:45 PM PDT 24
Finished Mar 31 12:27:46 PM PDT 24
Peak memory 203264 kb
Host smart-b58c642c-c6ac-4bd8-8d68-34d82d564011
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118019791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.1118019791
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.148452861
Short name T1281
Test name
Test status
Simulation time 46025938 ps
CPU time 1.12 seconds
Started Mar 31 12:27:17 PM PDT 24
Finished Mar 31 12:27:19 PM PDT 24
Peak memory 203408 kb
Host smart-775e04e2-b8ce-420e-81e6-5c1941364895
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148452861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_out
standing.148452861
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.2371392562
Short name T1280
Test name
Test status
Simulation time 141164775 ps
CPU time 1.58 seconds
Started Mar 31 12:27:01 PM PDT 24
Finished Mar 31 12:27:03 PM PDT 24
Peak memory 203552 kb
Host smart-6b7e16a1-1ca0-4b7e-b2a0-76ad7214501f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371392562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.2371392562
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.3467672413
Short name T129
Test name
Test status
Simulation time 126221502 ps
CPU time 1.98 seconds
Started Mar 31 12:27:08 PM PDT 24
Finished Mar 31 12:27:10 PM PDT 24
Peak memory 203476 kb
Host smart-b4ed8b37-92e9-41ee-be63-00857e8ecda2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467672413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.3467672413
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2946675155
Short name T1261
Test name
Test status
Simulation time 20125566 ps
CPU time 0.77 seconds
Started Mar 31 12:27:01 PM PDT 24
Finished Mar 31 12:27:02 PM PDT 24
Peak memory 203320 kb
Host smart-5e8b0645-395f-4e2d-9ea2-3d0b5b8553f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946675155 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.2946675155
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.473687171
Short name T148
Test name
Test status
Simulation time 66836312 ps
CPU time 0.71 seconds
Started Mar 31 12:27:13 PM PDT 24
Finished Mar 31 12:27:14 PM PDT 24
Peak memory 203340 kb
Host smart-9185c8cc-f0cd-42af-8321-aded222127ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473687171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.473687171
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.1822501182
Short name T1295
Test name
Test status
Simulation time 124666943 ps
CPU time 0.64 seconds
Started Mar 31 12:27:25 PM PDT 24
Finished Mar 31 12:27:26 PM PDT 24
Peak memory 203352 kb
Host smart-e803d82d-247d-4d13-8a47-dc92c05774af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822501182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.1822501182
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.474116472
Short name T1228
Test name
Test status
Simulation time 88056135 ps
CPU time 0.79 seconds
Started Mar 31 12:27:12 PM PDT 24
Finished Mar 31 12:27:13 PM PDT 24
Peak memory 203312 kb
Host smart-799454de-e584-4e18-8a6d-c1d1f4b77ca5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474116472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_out
standing.474116472
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.464097724
Short name T1269
Test name
Test status
Simulation time 152854342 ps
CPU time 2.55 seconds
Started Mar 31 12:27:23 PM PDT 24
Finished Mar 31 12:27:26 PM PDT 24
Peak memory 203592 kb
Host smart-e226edc5-24c6-4a36-923f-5ec140a208c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464097724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.464097724
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.3945634655
Short name T1274
Test name
Test status
Simulation time 153923540 ps
CPU time 2.15 seconds
Started Mar 31 12:27:12 PM PDT 24
Finished Mar 31 12:27:14 PM PDT 24
Peak memory 203520 kb
Host smart-7d3b63d4-2b6e-46c3-96ce-74b3c1fa99ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945634655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.3945634655
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3617263561
Short name T1258
Test name
Test status
Simulation time 24880310 ps
CPU time 0.74 seconds
Started Mar 31 12:27:54 PM PDT 24
Finished Mar 31 12:27:55 PM PDT 24
Peak memory 203352 kb
Host smart-c1d859b1-4fed-4a3c-b8e0-ccd1cb1a7b26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617263561 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.3617263561
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.1755587815
Short name T1234
Test name
Test status
Simulation time 54894149 ps
CPU time 0.66 seconds
Started Mar 31 12:27:02 PM PDT 24
Finished Mar 31 12:27:03 PM PDT 24
Peak memory 203252 kb
Host smart-2a310cb4-cfe1-4d4e-8b48-f2d07e9a12ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755587815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.1755587815
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.1420981781
Short name T233
Test name
Test status
Simulation time 15604147 ps
CPU time 0.66 seconds
Started Mar 31 12:27:01 PM PDT 24
Finished Mar 31 12:27:02 PM PDT 24
Peak memory 203220 kb
Host smart-6f7ecb1d-dcac-45ef-8eb2-035a1bd18d5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420981781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.1420981781
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.3433232870
Short name T153
Test name
Test status
Simulation time 150531177 ps
CPU time 1.18 seconds
Started Mar 31 12:27:46 PM PDT 24
Finished Mar 31 12:27:48 PM PDT 24
Peak memory 203524 kb
Host smart-6d42c93e-0d70-42c3-802b-04b1e2406ab6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433232870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.3433232870
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.2562222641
Short name T1270
Test name
Test status
Simulation time 252601147 ps
CPU time 1.53 seconds
Started Mar 31 12:27:01 PM PDT 24
Finished Mar 31 12:27:02 PM PDT 24
Peak memory 203452 kb
Host smart-6105aca3-c6e6-4a11-8ecb-dd966c709deb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562222641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.2562222641
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.993278873
Short name T1251
Test name
Test status
Simulation time 80762871 ps
CPU time 1.48 seconds
Started Mar 31 12:27:01 PM PDT 24
Finished Mar 31 12:27:02 PM PDT 24
Peak memory 203560 kb
Host smart-91ffb0fa-7dc9-42e8-a3a8-f1bc19edb07e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993278873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.993278873
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_alert_test.2206635207
Short name T178
Test name
Test status
Simulation time 22714742 ps
CPU time 0.61 seconds
Started Mar 31 03:43:50 PM PDT 24
Finished Mar 31 03:43:51 PM PDT 24
Peak memory 203688 kb
Host smart-85d63c50-1af1-451d-a18b-1b42e94ac6c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206635207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.2206635207
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.2762721383
Short name T687
Test name
Test status
Simulation time 100159593 ps
CPU time 1.4 seconds
Started Mar 31 03:43:42 PM PDT 24
Finished Mar 31 03:43:43 PM PDT 24
Peak memory 212092 kb
Host smart-843b1c5b-7b12-423a-a2d7-700680b43d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762721383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.2762721383
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.194808056
Short name T245
Test name
Test status
Simulation time 957494087 ps
CPU time 12.53 seconds
Started Mar 31 03:43:46 PM PDT 24
Finished Mar 31 03:43:58 PM PDT 24
Peak memory 251904 kb
Host smart-7c52a871-0c9f-465b-8dbd-af92732077ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194808056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empty
.194808056
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.3033029766
Short name T93
Test name
Test status
Simulation time 10378525972 ps
CPU time 213.57 seconds
Started Mar 31 03:43:41 PM PDT 24
Finished Mar 31 03:47:15 PM PDT 24
Peak memory 849000 kb
Host smart-1e2f80e5-ad86-422f-88ad-48f546e9f6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033029766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.3033029766
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.3425006135
Short name T872
Test name
Test status
Simulation time 25972065837 ps
CPU time 87.5 seconds
Started Mar 31 03:43:43 PM PDT 24
Finished Mar 31 03:45:10 PM PDT 24
Peak memory 785828 kb
Host smart-5776a8d3-7974-4763-9b34-bb24ac920e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425006135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.3425006135
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.4294444032
Short name T762
Test name
Test status
Simulation time 3812274842 ps
CPU time 71.88 seconds
Started Mar 31 03:43:40 PM PDT 24
Finished Mar 31 03:44:52 PM PDT 24
Peak memory 960212 kb
Host smart-f43a7ac6-a1a9-4d31-8542-210b37aa691c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294444032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.4294444032
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.3994653200
Short name T179
Test name
Test status
Simulation time 5064108484 ps
CPU time 15.43 seconds
Started Mar 31 03:43:45 PM PDT 24
Finished Mar 31 03:44:00 PM PDT 24
Peak memory 203944 kb
Host smart-5eadbe8a-da25-41ad-b4ee-e22bfaedc36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994653200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.3994653200
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_host_override.3437177425
Short name T1113
Test name
Test status
Simulation time 83565335 ps
CPU time 0.67 seconds
Started Mar 31 03:43:43 PM PDT 24
Finished Mar 31 03:43:44 PM PDT 24
Peak memory 203364 kb
Host smart-3a7cb9b5-2cd5-4291-949a-239223e2f2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437177425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.3437177425
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.3806341088
Short name T46
Test name
Test status
Simulation time 1043029631 ps
CPU time 20.88 seconds
Started Mar 31 03:43:42 PM PDT 24
Finished Mar 31 03:44:03 PM PDT 24
Peak memory 316148 kb
Host smart-100c4890-66a6-4bdc-87db-5add69d0f769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806341088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.3806341088
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.673736305
Short name T107
Test name
Test status
Simulation time 245034076 ps
CPU time 0.95 seconds
Started Mar 31 03:43:52 PM PDT 24
Finished Mar 31 03:43:53 PM PDT 24
Peak memory 222396 kb
Host smart-6b7ef020-a51d-4a87-a896-d653407fa074
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673736305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.673736305
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.1537489770
Short name T591
Test name
Test status
Simulation time 10195294012 ps
CPU time 34.97 seconds
Started Mar 31 03:43:44 PM PDT 24
Finished Mar 31 03:44:19 PM PDT 24
Peak memory 402696 kb
Host smart-def1a037-2c19-4018-b5e3-4e1d8b12c709
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537489770 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.1537489770
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.3568056560
Short name T707
Test name
Test status
Simulation time 10249072302 ps
CPU time 14.74 seconds
Started Mar 31 03:43:48 PM PDT 24
Finished Mar 31 03:44:03 PM PDT 24
Peak memory 323284 kb
Host smart-02e112e0-3aa5-477f-8122-67daacd7c7f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568056560 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_tx.3568056560
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.3463894570
Short name T952
Test name
Test status
Simulation time 847518382 ps
CPU time 2.54 seconds
Started Mar 31 03:43:44 PM PDT 24
Finished Mar 31 03:43:46 PM PDT 24
Peak memory 203776 kb
Host smart-1a4b2465-fd7c-42a7-8c41-ac70011ed367
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463894570 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_hrst.3463894570
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.33937386
Short name T443
Test name
Test status
Simulation time 3553496538 ps
CPU time 4.3 seconds
Started Mar 31 03:43:45 PM PDT 24
Finished Mar 31 03:43:49 PM PDT 24
Peak memory 203884 kb
Host smart-450bae7c-cbe7-475c-a9b0-6eac7d67d82b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33937386 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_intr_smoke.33937386
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.1725113766
Short name T1096
Test name
Test status
Simulation time 3274531791 ps
CPU time 7.42 seconds
Started Mar 31 03:43:46 PM PDT 24
Finished Mar 31 03:43:54 PM PDT 24
Peak memory 203844 kb
Host smart-a4b51a3f-0cfa-4b22-9d27-e2b0a0d2edc0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725113766 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.1725113766
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.229261564
Short name T1035
Test name
Test status
Simulation time 1358962365 ps
CPU time 20.27 seconds
Started Mar 31 03:43:45 PM PDT 24
Finished Mar 31 03:44:06 PM PDT 24
Peak memory 203856 kb
Host smart-3a648846-cb18-48de-8605-e71da082aa92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229261564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_targ
et_smoke.229261564
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.2357794224
Short name T748
Test name
Test status
Simulation time 6509058917 ps
CPU time 23.68 seconds
Started Mar 31 03:43:44 PM PDT 24
Finished Mar 31 03:44:08 PM PDT 24
Peak memory 224592 kb
Host smart-072d6ce8-fe72-4854-af52-eac816094b19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357794224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_rd.2357794224
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.703835688
Short name T432
Test name
Test status
Simulation time 2595635582 ps
CPU time 7.05 seconds
Started Mar 31 03:43:46 PM PDT 24
Finished Mar 31 03:43:53 PM PDT 24
Peak memory 210408 kb
Host smart-a919dceb-f47a-4cc2-854e-53c2a4259962
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703835688 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_timeout.703835688
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_unexp_stop.486857194
Short name T47
Test name
Test status
Simulation time 938955631 ps
CPU time 5.47 seconds
Started Mar 31 03:43:46 PM PDT 24
Finished Mar 31 03:43:51 PM PDT 24
Peak memory 205736 kb
Host smart-ca0c3a2a-1923-4ba2-b50b-ad5bceff53c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486857194 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_unexp_stop.486857194
Directory /workspace/0.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.2140528589
Short name T293
Test name
Test status
Simulation time 86616088 ps
CPU time 1.77 seconds
Started Mar 31 03:43:49 PM PDT 24
Finished Mar 31 03:43:51 PM PDT 24
Peak memory 211836 kb
Host smart-8e1e673d-c16f-46d6-8cf2-7cc73012369c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140528589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.2140528589
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.3524293514
Short name T915
Test name
Test status
Simulation time 2771763340 ps
CPU time 10.39 seconds
Started Mar 31 03:43:49 PM PDT 24
Finished Mar 31 03:43:59 PM PDT 24
Peak memory 242016 kb
Host smart-e34c8cef-e0cc-450c-ba8f-7cff5f73dc9c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524293514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empt
y.3524293514
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.2596606840
Short name T1166
Test name
Test status
Simulation time 3105013984 ps
CPU time 85.86 seconds
Started Mar 31 03:43:47 PM PDT 24
Finished Mar 31 03:45:13 PM PDT 24
Peak memory 333912 kb
Host smart-9da6bfa7-cd89-4837-9ad5-8773caaa994a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596606840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.2596606840
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.3385208961
Short name T1144
Test name
Test status
Simulation time 1876733345 ps
CPU time 61.25 seconds
Started Mar 31 03:43:46 PM PDT 24
Finished Mar 31 03:44:48 PM PDT 24
Peak memory 651720 kb
Host smart-ec67005c-c9ea-4fd4-9009-e58df2314581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385208961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.3385208961
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.4014581561
Short name T369
Test name
Test status
Simulation time 218038684 ps
CPU time 0.81 seconds
Started Mar 31 03:43:48 PM PDT 24
Finished Mar 31 03:43:49 PM PDT 24
Peak memory 203672 kb
Host smart-834ff632-5a02-4941-bdac-fb8102f3d46f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014581561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.4014581561
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.4197194678
Short name T668
Test name
Test status
Simulation time 262537589 ps
CPU time 4 seconds
Started Mar 31 03:43:50 PM PDT 24
Finished Mar 31 03:43:54 PM PDT 24
Peak memory 228380 kb
Host smart-9c63e3e6-657b-4a6e-9acb-16d8b744d3e9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197194678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.
4197194678
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.2932983876
Short name T985
Test name
Test status
Simulation time 466631914 ps
CPU time 5.49 seconds
Started Mar 31 03:43:54 PM PDT 24
Finished Mar 31 03:43:59 PM PDT 24
Peak memory 203860 kb
Host smart-d2ae14aa-f74e-450d-9559-0ba7d9315e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932983876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.2932983876
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.3559611038
Short name T857
Test name
Test status
Simulation time 1744988907 ps
CPU time 41.35 seconds
Started Mar 31 03:43:56 PM PDT 24
Finished Mar 31 03:44:38 PM PDT 24
Peak memory 293296 kb
Host smart-65b1d514-2225-471b-9fbd-2b69c0e77721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559611038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.3559611038
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/1.i2c_host_override.2703425511
Short name T766
Test name
Test status
Simulation time 94667564 ps
CPU time 0.67 seconds
Started Mar 31 03:43:45 PM PDT 24
Finished Mar 31 03:43:45 PM PDT 24
Peak memory 203620 kb
Host smart-9e82ee7b-6597-4956-aad5-0cb79c341c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703425511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.2703425511
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.2370209262
Short name T675
Test name
Test status
Simulation time 1188476623 ps
CPU time 21.14 seconds
Started Mar 31 03:43:42 PM PDT 24
Finished Mar 31 03:44:03 PM PDT 24
Peak memory 359196 kb
Host smart-753120a5-54cd-49b4-9d42-7a1d33ec5f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370209262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.2370209262
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.1763440768
Short name T109
Test name
Test status
Simulation time 400472075 ps
CPU time 0.85 seconds
Started Mar 31 03:43:56 PM PDT 24
Finished Mar 31 03:43:57 PM PDT 24
Peak memory 221344 kb
Host smart-ee9a5953-9296-4a51-9a41-7fc31f4a42e2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763440768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.1763440768
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.839648198
Short name T730
Test name
Test status
Simulation time 4940188885 ps
CPU time 3.19 seconds
Started Mar 31 03:43:59 PM PDT 24
Finished Mar 31 03:44:02 PM PDT 24
Peak memory 203860 kb
Host smart-bece34bb-c9b1-4835-8269-2464aa0c51a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839648198 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.839648198
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.3794515894
Short name T569
Test name
Test status
Simulation time 10691362486 ps
CPU time 12.82 seconds
Started Mar 31 03:43:49 PM PDT 24
Finished Mar 31 03:44:02 PM PDT 24
Peak memory 286828 kb
Host smart-b3929c14-afdc-4385-b5c3-f31eed75400c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794515894 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.3794515894
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.3346725456
Short name T283
Test name
Test status
Simulation time 1973989231 ps
CPU time 2.87 seconds
Started Mar 31 03:44:02 PM PDT 24
Finished Mar 31 03:44:05 PM PDT 24
Peak memory 203856 kb
Host smart-17f54f90-c428-4a1d-89df-fcb65db652b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346725456 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_hrst.3346725456
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.769541224
Short name T758
Test name
Test status
Simulation time 1726756077 ps
CPU time 4.54 seconds
Started Mar 31 03:43:48 PM PDT 24
Finished Mar 31 03:43:52 PM PDT 24
Peak memory 203844 kb
Host smart-efbe8e2a-7c55-4afe-9636-a0ba0e61acb8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769541224 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_intr_smoke.769541224
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.1086075195
Short name T595
Test name
Test status
Simulation time 1481289787 ps
CPU time 29.53 seconds
Started Mar 31 03:43:47 PM PDT 24
Finished Mar 31 03:44:17 PM PDT 24
Peak memory 203772 kb
Host smart-dcadc4cc-67f3-4ace-9a04-9bfdf23a5f2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086075195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_smoke.1086075195
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.3624392041
Short name T1110
Test name
Test status
Simulation time 4853157938 ps
CPU time 49.78 seconds
Started Mar 31 03:43:48 PM PDT 24
Finished Mar 31 03:44:38 PM PDT 24
Peak memory 205124 kb
Host smart-06224539-5004-4c89-9220-e038d27a445b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624392041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.3624392041
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.4191127934
Short name T1186
Test name
Test status
Simulation time 29740345957 ps
CPU time 2464.2 seconds
Started Mar 31 03:43:48 PM PDT 24
Finished Mar 31 04:24:53 PM PDT 24
Peak memory 7423464 kb
Host smart-b1360b65-f0d2-424b-893f-500e47c48806
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191127934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stretch.4191127934
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.1319636855
Short name T1064
Test name
Test status
Simulation time 1349831553 ps
CPU time 6.27 seconds
Started Mar 31 03:43:52 PM PDT 24
Finished Mar 31 03:43:58 PM PDT 24
Peak memory 212012 kb
Host smart-710d42b1-8873-4c3f-b2dd-6edff5209c4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319636855 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_timeout.1319636855
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_target_unexp_stop.182414882
Short name T476
Test name
Test status
Simulation time 877399169 ps
CPU time 4.92 seconds
Started Mar 31 03:43:48 PM PDT 24
Finished Mar 31 03:43:53 PM PDT 24
Peak memory 212008 kb
Host smart-8a59ed31-3c67-4740-9ebe-ae3779cfc6ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182414882 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_unexp_stop.182414882
Directory /workspace/1.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/10.i2c_alert_test.3712393739
Short name T426
Test name
Test status
Simulation time 23347438 ps
CPU time 0.62 seconds
Started Mar 31 03:44:38 PM PDT 24
Finished Mar 31 03:44:39 PM PDT 24
Peak memory 203668 kb
Host smart-c694f3d3-2179-419c-84a8-942e816072fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712393739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.3712393739
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.1970496758
Short name T1040
Test name
Test status
Simulation time 331079699 ps
CPU time 1.46 seconds
Started Mar 31 03:44:32 PM PDT 24
Finished Mar 31 03:44:34 PM PDT 24
Peak memory 220160 kb
Host smart-7e81d22a-3e4a-43b8-a566-707a863ff40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970496758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.1970496758
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.338505319
Short name T349
Test name
Test status
Simulation time 1342373726 ps
CPU time 5.39 seconds
Started Mar 31 03:44:35 PM PDT 24
Finished Mar 31 03:44:41 PM PDT 24
Peak memory 265664 kb
Host smart-5ce116ba-244c-4bfa-883a-b766cd5d6dfe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338505319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_empt
y.338505319
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.2778395370
Short name T959
Test name
Test status
Simulation time 3359068311 ps
CPU time 83.71 seconds
Started Mar 31 03:44:31 PM PDT 24
Finished Mar 31 03:45:55 PM PDT 24
Peak memory 721612 kb
Host smart-57b498f5-ede8-42b4-a39b-f473806de7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778395370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.2778395370
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.1846835097
Short name T460
Test name
Test status
Simulation time 1523736315 ps
CPU time 46.22 seconds
Started Mar 31 03:44:39 PM PDT 24
Finished Mar 31 03:45:26 PM PDT 24
Peak memory 582120 kb
Host smart-5b6e384e-1275-4610-a087-3ca950f96450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846835097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.1846835097
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.3946895664
Short name T941
Test name
Test status
Simulation time 124143893 ps
CPU time 0.94 seconds
Started Mar 31 03:44:37 PM PDT 24
Finished Mar 31 03:44:38 PM PDT 24
Peak memory 203688 kb
Host smart-bb476c12-e1d7-4c11-8ffe-2d1d0e962e7d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946895664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_f
mt.3946895664
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.2859148193
Short name T637
Test name
Test status
Simulation time 104739749 ps
CPU time 5.73 seconds
Started Mar 31 03:44:36 PM PDT 24
Finished Mar 31 03:44:43 PM PDT 24
Peak memory 218576 kb
Host smart-f81e8c57-4900-4337-bb5e-baa201e7730d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859148193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.2859148193
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.554632043
Short name T870
Test name
Test status
Simulation time 3555666898 ps
CPU time 98.22 seconds
Started Mar 31 03:44:38 PM PDT 24
Finished Mar 31 03:46:18 PM PDT 24
Peak memory 967948 kb
Host smart-336420c1-2cf9-4270-9225-eba446dca763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554632043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.554632043
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.1517010545
Short name T528
Test name
Test status
Simulation time 824224804 ps
CPU time 2.67 seconds
Started Mar 31 03:44:36 PM PDT 24
Finished Mar 31 03:44:39 PM PDT 24
Peak memory 203884 kb
Host smart-5ef327bb-b2d5-4c68-b70b-89ad1f63a4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517010545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.1517010545
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.2683773507
Short name T475
Test name
Test status
Simulation time 9674084513 ps
CPU time 18.74 seconds
Started Mar 31 03:44:38 PM PDT 24
Finished Mar 31 03:44:58 PM PDT 24
Peak memory 361388 kb
Host smart-66378f77-b257-4cc8-ab4b-d3fba27c642e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683773507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.2683773507
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_override.3553354855
Short name T297
Test name
Test status
Simulation time 28980904 ps
CPU time 0.66 seconds
Started Mar 31 03:44:32 PM PDT 24
Finished Mar 31 03:44:33 PM PDT 24
Peak memory 203592 kb
Host smart-2b588cf2-f835-4662-93a3-bd3bfabc4a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553354855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.3553354855
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.615101722
Short name T1136
Test name
Test status
Simulation time 12986263475 ps
CPU time 123.49 seconds
Started Mar 31 03:44:39 PM PDT 24
Finished Mar 31 03:46:43 PM PDT 24
Peak memory 902160 kb
Host smart-970c6188-703a-45d9-8c95-1084c3a9a554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615101722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.615101722
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.2934438690
Short name T258
Test name
Test status
Simulation time 1086237251 ps
CPU time 56.86 seconds
Started Mar 31 03:44:33 PM PDT 24
Finished Mar 31 03:45:29 PM PDT 24
Peak memory 378772 kb
Host smart-5d21b5de-c815-4c1f-98bf-b92f1b00898e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934438690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.2934438690
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.638293956
Short name T534
Test name
Test status
Simulation time 712022355 ps
CPU time 3.68 seconds
Started Mar 31 03:44:39 PM PDT 24
Finished Mar 31 03:44:43 PM PDT 24
Peak memory 203840 kb
Host smart-76c752c6-393e-4a33-be5f-1ae86035c05f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638293956 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.638293956
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.3843282135
Short name T243
Test name
Test status
Simulation time 10412564034 ps
CPU time 12.77 seconds
Started Mar 31 03:44:37 PM PDT 24
Finished Mar 31 03:44:50 PM PDT 24
Peak memory 294920 kb
Host smart-a797db60-8fd1-45d7-805a-ed25101042e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843282135 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.3843282135
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.1552055729
Short name T1131
Test name
Test status
Simulation time 10117567377 ps
CPU time 14.57 seconds
Started Mar 31 03:44:39 PM PDT 24
Finished Mar 31 03:44:54 PM PDT 24
Peak memory 308944 kb
Host smart-acdcbeed-2d59-428b-95e9-1f267340aad6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552055729 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_tx.1552055729
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.3995610054
Short name T994
Test name
Test status
Simulation time 375043327 ps
CPU time 2.23 seconds
Started Mar 31 03:44:39 PM PDT 24
Finished Mar 31 03:44:42 PM PDT 24
Peak memory 203688 kb
Host smart-d7d8cfa3-5a1a-489c-9236-49febf2a2c86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995610054 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_hrst.3995610054
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.2654915086
Short name T831
Test name
Test status
Simulation time 3432296827 ps
CPU time 4.57 seconds
Started Mar 31 03:44:36 PM PDT 24
Finished Mar 31 03:44:41 PM PDT 24
Peak memory 203860 kb
Host smart-2e8491d4-baeb-4f6a-9ea3-07bd916ae3cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654915086 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_intr_smoke.2654915086
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.2914522655
Short name T839
Test name
Test status
Simulation time 635812204 ps
CPU time 8.25 seconds
Started Mar 31 03:44:40 PM PDT 24
Finished Mar 31 03:44:49 PM PDT 24
Peak memory 203792 kb
Host smart-cf9d1bec-6ede-462f-885a-61332fb5e26e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914522655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.2914522655
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.2537698601
Short name T738
Test name
Test status
Simulation time 2563385692 ps
CPU time 23.36 seconds
Started Mar 31 03:44:37 PM PDT 24
Finished Mar 31 03:45:01 PM PDT 24
Peak memory 221920 kb
Host smart-7ee73675-ce13-4a76-8a9f-cb86ed3f6222
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537698601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.2537698601
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.2896789180
Short name T754
Test name
Test status
Simulation time 1016835900 ps
CPU time 6 seconds
Started Mar 31 03:44:34 PM PDT 24
Finished Mar 31 03:44:40 PM PDT 24
Peak memory 212224 kb
Host smart-e4c6a27d-d781-41d9-ad80-8ca7ed4be2fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896789180 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.2896789180
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_alert_test.1158056469
Short name T281
Test name
Test status
Simulation time 16876616 ps
CPU time 0.61 seconds
Started Mar 31 03:44:42 PM PDT 24
Finished Mar 31 03:44:42 PM PDT 24
Peak memory 203700 kb
Host smart-948ce25e-619f-4cdf-a547-f8425676164e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158056469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.1158056469
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.694021605
Short name T739
Test name
Test status
Simulation time 84106190 ps
CPU time 1.42 seconds
Started Mar 31 03:44:40 PM PDT 24
Finished Mar 31 03:44:41 PM PDT 24
Peak memory 215540 kb
Host smart-523ab0e2-a4c4-4b86-a8cb-9cd2f7539886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694021605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.694021605
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.1002213852
Short name T1067
Test name
Test status
Simulation time 1495447509 ps
CPU time 6.01 seconds
Started Mar 31 03:44:45 PM PDT 24
Finished Mar 31 03:44:51 PM PDT 24
Peak memory 257512 kb
Host smart-c29dfc36-90a2-4d99-99f2-68d61dfa1e2a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002213852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.1002213852
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.1933580028
Short name T1208
Test name
Test status
Simulation time 1286305786 ps
CPU time 37.28 seconds
Started Mar 31 03:44:41 PM PDT 24
Finished Mar 31 03:45:18 PM PDT 24
Peak memory 409360 kb
Host smart-d925592c-b79e-470e-993c-1d512c5500b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933580028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.1933580028
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.1076035337
Short name T286
Test name
Test status
Simulation time 2271538988 ps
CPU time 83.7 seconds
Started Mar 31 03:44:40 PM PDT 24
Finished Mar 31 03:46:04 PM PDT 24
Peak memory 746208 kb
Host smart-f96128bb-556c-42a5-9e11-ee7623462205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076035337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.1076035337
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.3834783228
Short name T1190
Test name
Test status
Simulation time 74691802 ps
CPU time 0.87 seconds
Started Mar 31 03:44:42 PM PDT 24
Finished Mar 31 03:44:43 PM PDT 24
Peak memory 203688 kb
Host smart-dbad8d03-eb17-4071-83b3-09725161627f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834783228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.3834783228
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.3186356684
Short name T899
Test name
Test status
Simulation time 636700753 ps
CPU time 7.71 seconds
Started Mar 31 03:44:41 PM PDT 24
Finished Mar 31 03:44:49 PM PDT 24
Peak memory 226552 kb
Host smart-7f0026e2-20ee-4534-b00e-cb584136cb3e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186356684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.3186356684
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.2883024523
Short name T1201
Test name
Test status
Simulation time 5988927171 ps
CPU time 63.54 seconds
Started Mar 31 03:44:42 PM PDT 24
Finished Mar 31 03:45:46 PM PDT 24
Peak memory 917152 kb
Host smart-e9f0353b-b49f-454f-bd49-c89dedc0c4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883024523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.2883024523
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.1612054478
Short name T1049
Test name
Test status
Simulation time 472440465 ps
CPU time 4.54 seconds
Started Mar 31 03:44:42 PM PDT 24
Finished Mar 31 03:44:47 PM PDT 24
Peak memory 203828 kb
Host smart-31ba8783-2d35-471e-baee-3a16fb75e817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612054478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.1612054478
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.3963997045
Short name T680
Test name
Test status
Simulation time 1549959681 ps
CPU time 75.93 seconds
Started Mar 31 03:44:43 PM PDT 24
Finished Mar 31 03:45:59 PM PDT 24
Peak memory 431324 kb
Host smart-60e78080-ed15-4be0-9930-a8a384717cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963997045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.3963997045
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_override.3228630997
Short name T491
Test name
Test status
Simulation time 80188279 ps
CPU time 0.69 seconds
Started Mar 31 03:44:41 PM PDT 24
Finished Mar 31 03:44:42 PM PDT 24
Peak memory 203600 kb
Host smart-98516801-2256-4257-bd0a-23ffd2beb2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228630997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.3228630997
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.2351640435
Short name T562
Test name
Test status
Simulation time 4895689230 ps
CPU time 26.92 seconds
Started Mar 31 03:44:42 PM PDT 24
Finished Mar 31 03:45:09 PM PDT 24
Peak memory 359504 kb
Host smart-3f1a348b-7197-4d8c-a144-c42f77b92aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351640435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.2351640435
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.1755828255
Short name T1207
Test name
Test status
Simulation time 431301085 ps
CPU time 2.63 seconds
Started Mar 31 03:44:38 PM PDT 24
Finished Mar 31 03:44:42 PM PDT 24
Peak memory 203804 kb
Host smart-c30ed373-acf9-4209-ada4-c27cf57644a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755828255 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.1755828255
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.3859786837
Short name T1086
Test name
Test status
Simulation time 10305830437 ps
CPU time 36.83 seconds
Started Mar 31 03:44:38 PM PDT 24
Finished Mar 31 03:45:15 PM PDT 24
Peak memory 429112 kb
Host smart-59edf6c1-5e4f-437c-a4f2-f9d7eed83191
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859786837 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.3859786837
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.2784735404
Short name T447
Test name
Test status
Simulation time 10133726085 ps
CPU time 15.31 seconds
Started Mar 31 03:44:38 PM PDT 24
Finished Mar 31 03:44:53 PM PDT 24
Peak memory 307468 kb
Host smart-62915f31-33bf-432c-b1b3-5aa8afb31e39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784735404 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.2784735404
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.924247392
Short name T1041
Test name
Test status
Simulation time 1325019157 ps
CPU time 2.29 seconds
Started Mar 31 03:44:47 PM PDT 24
Finished Mar 31 03:44:50 PM PDT 24
Peak memory 203732 kb
Host smart-6ced36d7-a35d-48e7-9725-044267ecd09c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924247392 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 11.i2c_target_hrst.924247392
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.1632817943
Short name T365
Test name
Test status
Simulation time 3209662874 ps
CPU time 4.75 seconds
Started Mar 31 03:44:38 PM PDT 24
Finished Mar 31 03:44:43 PM PDT 24
Peak memory 203872 kb
Host smart-38e03a02-9c29-4199-88f2-7d14aa135870
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632817943 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_intr_smoke.1632817943
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.1643879630
Short name T882
Test name
Test status
Simulation time 17094949122 ps
CPU time 12.09 seconds
Started Mar 31 03:44:46 PM PDT 24
Finished Mar 31 03:44:58 PM PDT 24
Peak memory 203752 kb
Host smart-5dc75c3d-3897-4f96-904f-2494d0946827
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643879630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta
rget_smoke.1643879630
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.3415073122
Short name T628
Test name
Test status
Simulation time 9361274233 ps
CPU time 30.54 seconds
Started Mar 31 03:44:43 PM PDT 24
Finished Mar 31 03:45:14 PM PDT 24
Peak memory 226288 kb
Host smart-ea1e1a69-6a98-4340-a65f-4360ae858e4c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415073122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.3415073122
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.1884749684
Short name T287
Test name
Test status
Simulation time 6316473958 ps
CPU time 13.99 seconds
Started Mar 31 03:44:49 PM PDT 24
Finished Mar 31 03:45:03 PM PDT 24
Peak memory 346084 kb
Host smart-c586cc4e-ae09-4884-9653-7cbade7c4ebc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884749684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_
target_stretch.1884749684
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.1423786888
Short name T288
Test name
Test status
Simulation time 1404264657 ps
CPU time 6.91 seconds
Started Mar 31 03:44:38 PM PDT 24
Finished Mar 31 03:44:45 PM PDT 24
Peak memory 216940 kb
Host smart-66770f63-bc0f-4df6-9f42-0e473d1eb8fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423786888 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_timeout.1423786888
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_alert_test.992124653
Short name T981
Test name
Test status
Simulation time 28176136 ps
CPU time 0.63 seconds
Started Mar 31 03:44:50 PM PDT 24
Finished Mar 31 03:44:51 PM PDT 24
Peak memory 203676 kb
Host smart-c16122be-b40f-4b50-ba39-97d497801a77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992124653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.992124653
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.3619277364
Short name T1004
Test name
Test status
Simulation time 292948565 ps
CPU time 1.73 seconds
Started Mar 31 03:44:42 PM PDT 24
Finished Mar 31 03:44:44 PM PDT 24
Peak memory 212020 kb
Host smart-be50db77-022b-4853-980c-3fd0299b45b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619277364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.3619277364
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.398152915
Short name T588
Test name
Test status
Simulation time 216301855 ps
CPU time 11.53 seconds
Started Mar 31 03:44:43 PM PDT 24
Finished Mar 31 03:44:55 PM PDT 24
Peak memory 244400 kb
Host smart-b0e55c29-f547-44b2-a92c-4b42e1aed240
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398152915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_empt
y.398152915
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.3809478334
Short name T688
Test name
Test status
Simulation time 10816319807 ps
CPU time 179.33 seconds
Started Mar 31 03:44:45 PM PDT 24
Finished Mar 31 03:47:44 PM PDT 24
Peak memory 771512 kb
Host smart-d77cd6f3-ff11-4c53-b1d5-ceed76ae4222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809478334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.3809478334
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.3275125847
Short name T356
Test name
Test status
Simulation time 3618744704 ps
CPU time 53.28 seconds
Started Mar 31 03:44:43 PM PDT 24
Finished Mar 31 03:45:36 PM PDT 24
Peak memory 588152 kb
Host smart-ff521fce-7750-47da-a876-22f908d273f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275125847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.3275125847
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.1626757426
Short name T291
Test name
Test status
Simulation time 412778020 ps
CPU time 1.06 seconds
Started Mar 31 03:44:42 PM PDT 24
Finished Mar 31 03:44:43 PM PDT 24
Peak memory 203760 kb
Host smart-db6d2d4e-b8c4-45fb-ace8-8e5b3f105d9b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626757426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_f
mt.1626757426
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.1279656837
Short name T1074
Test name
Test status
Simulation time 634380984 ps
CPU time 4.75 seconds
Started Mar 31 03:44:47 PM PDT 24
Finished Mar 31 03:44:52 PM PDT 24
Peak memory 231492 kb
Host smart-906f81f9-7203-4f21-87c6-5ef47fec22ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279656837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.1279656837
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.2019659612
Short name T698
Test name
Test status
Simulation time 12116926438 ps
CPU time 72 seconds
Started Mar 31 03:44:43 PM PDT 24
Finished Mar 31 03:45:55 PM PDT 24
Peak memory 926176 kb
Host smart-ba172211-0e6f-4d26-bff9-1a168154c3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019659612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.2019659612
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.191007157
Short name T1003
Test name
Test status
Simulation time 167670452 ps
CPU time 6.31 seconds
Started Mar 31 03:44:49 PM PDT 24
Finished Mar 31 03:44:55 PM PDT 24
Peak memory 203804 kb
Host smart-787f4950-6979-439e-b4ff-e0a5fc0685f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191007157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.191007157
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.3248352353
Short name T924
Test name
Test status
Simulation time 14199489717 ps
CPU time 53.03 seconds
Started Mar 31 03:44:46 PM PDT 24
Finished Mar 31 03:45:39 PM PDT 24
Peak memory 363300 kb
Host smart-a158a5d6-fbcd-424a-b63d-aa19b5072973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248352353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.3248352353
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_host_override.3118500059
Short name T713
Test name
Test status
Simulation time 46120018 ps
CPU time 0.62 seconds
Started Mar 31 03:44:47 PM PDT 24
Finished Mar 31 03:44:48 PM PDT 24
Peak memory 203536 kb
Host smart-fc0bc437-7cab-44fb-a463-9991d3c5d749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118500059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.3118500059
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.2346834735
Short name T966
Test name
Test status
Simulation time 1222009350 ps
CPU time 63.62 seconds
Started Mar 31 03:44:47 PM PDT 24
Finished Mar 31 03:45:51 PM PDT 24
Peak memory 357408 kb
Host smart-c9778486-f5bb-4696-8c83-271a546b71dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346834735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.2346834735
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.211513871
Short name T31
Test name
Test status
Simulation time 1749370703 ps
CPU time 2.6 seconds
Started Mar 31 03:44:50 PM PDT 24
Finished Mar 31 03:44:53 PM PDT 24
Peak memory 203872 kb
Host smart-0f33fae8-5ef3-4bee-86ee-73b877232bab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211513871 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.211513871
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.310958880
Short name T922
Test name
Test status
Simulation time 10714461803 ps
CPU time 8.24 seconds
Started Mar 31 03:44:47 PM PDT 24
Finished Mar 31 03:44:56 PM PDT 24
Peak memory 250568 kb
Host smart-edef6381-99a7-40a0-aa40-78b6921053c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310958880 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_acq.310958880
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.194288319
Short name T68
Test name
Test status
Simulation time 10086721006 ps
CPU time 64.19 seconds
Started Mar 31 03:44:47 PM PDT 24
Finished Mar 31 03:45:51 PM PDT 24
Peak memory 542816 kb
Host smart-9e49895b-1fb2-4ff0-b1f5-4b08bcb6be09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194288319 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.i2c_target_fifo_reset_tx.194288319
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.1431887839
Short name T574
Test name
Test status
Simulation time 788884961 ps
CPU time 4.37 seconds
Started Mar 31 03:44:44 PM PDT 24
Finished Mar 31 03:44:48 PM PDT 24
Peak memory 204376 kb
Host smart-41b05250-0581-4e4b-a1cf-a8207fdb8790
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431887839 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.1431887839
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.2198268139
Short name T829
Test name
Test status
Simulation time 4539529270 ps
CPU time 6.1 seconds
Started Mar 31 03:44:41 PM PDT 24
Finished Mar 31 03:44:48 PM PDT 24
Peak memory 203816 kb
Host smart-14853d23-8a76-4123-8e8f-30ad08e46223
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198268139 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.2198268139
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.2805320994
Short name T1133
Test name
Test status
Simulation time 3102547436 ps
CPU time 9.86 seconds
Started Mar 31 03:44:44 PM PDT 24
Finished Mar 31 03:44:54 PM PDT 24
Peak memory 203820 kb
Host smart-58f62205-ad20-45de-8fc5-abd3389156a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805320994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_smoke.2805320994
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.1347508268
Short name T449
Test name
Test status
Simulation time 1140930649 ps
CPU time 10.78 seconds
Started Mar 31 03:44:41 PM PDT 24
Finished Mar 31 03:44:52 PM PDT 24
Peak memory 212164 kb
Host smart-4ca0e678-686c-4f01-9327-22e70207fbc8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347508268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_rd.1347508268
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.195303512
Short name T481
Test name
Test status
Simulation time 24242864256 ps
CPU time 1959.36 seconds
Started Mar 31 03:44:47 PM PDT 24
Finished Mar 31 04:17:28 PM PDT 24
Peak memory 6168316 kb
Host smart-fcacaacb-dab8-4090-86d2-5a4cd29ee8da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195303512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_t
arget_stretch.195303512
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.1857288539
Short name T409
Test name
Test status
Simulation time 1263063091 ps
CPU time 7.13 seconds
Started Mar 31 03:44:44 PM PDT 24
Finished Mar 31 03:44:51 PM PDT 24
Peak memory 220036 kb
Host smart-6ad4b77d-5d46-4201-93a2-4f6d3d249e13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857288539 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.1857288539
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_alert_test.3117894572
Short name T101
Test name
Test status
Simulation time 17728016 ps
CPU time 0.64 seconds
Started Mar 31 03:44:55 PM PDT 24
Finished Mar 31 03:44:58 PM PDT 24
Peak memory 203668 kb
Host smart-5e303489-e433-406e-82fd-2833cfe49edb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117894572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.3117894572
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.3643160614
Short name T382
Test name
Test status
Simulation time 491825897 ps
CPU time 1.64 seconds
Started Mar 31 03:44:50 PM PDT 24
Finished Mar 31 03:44:52 PM PDT 24
Peak memory 212004 kb
Host smart-e20b06f3-9453-43a4-bf06-ce2d1780d9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643160614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.3643160614
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.1909169367
Short name T508
Test name
Test status
Simulation time 283425187 ps
CPU time 6.29 seconds
Started Mar 31 03:44:49 PM PDT 24
Finished Mar 31 03:44:56 PM PDT 24
Peak memory 258752 kb
Host smart-d9ebcf95-8ae6-48ce-aa52-120415496fa6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909169367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.1909169367
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.159230904
Short name T442
Test name
Test status
Simulation time 13358012023 ps
CPU time 48.33 seconds
Started Mar 31 03:44:48 PM PDT 24
Finished Mar 31 03:45:36 PM PDT 24
Peak memory 568124 kb
Host smart-a382ccf6-3682-49ac-afdd-ae3ca4530188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159230904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.159230904
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.2782106271
Short name T1169
Test name
Test status
Simulation time 11979366693 ps
CPU time 65.59 seconds
Started Mar 31 03:44:51 PM PDT 24
Finished Mar 31 03:45:57 PM PDT 24
Peak memory 713184 kb
Host smart-f8a1c94c-8129-4bb9-b963-78b764b72d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782106271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.2782106271
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.2142044468
Short name T332
Test name
Test status
Simulation time 197137782 ps
CPU time 0.9 seconds
Started Mar 31 03:44:50 PM PDT 24
Finished Mar 31 03:44:52 PM PDT 24
Peak memory 203724 kb
Host smart-7678dfa1-f4a0-4ab4-b3e6-829e1baf9f19
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142044468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.2142044468
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.3239281130
Short name T822
Test name
Test status
Simulation time 299652354 ps
CPU time 9.19 seconds
Started Mar 31 03:44:49 PM PDT 24
Finished Mar 31 03:44:58 PM PDT 24
Peak memory 232776 kb
Host smart-3b3b8a71-16a0-4a97-81bb-63f4d00dac49
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239281130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.3239281130
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.850309599
Short name T1165
Test name
Test status
Simulation time 11688507885 ps
CPU time 60.96 seconds
Started Mar 31 03:44:49 PM PDT 24
Finished Mar 31 03:45:50 PM PDT 24
Peak memory 784076 kb
Host smart-20510477-8292-454c-95b4-2f9ebc90defe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850309599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.850309599
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.986979543
Short name T586
Test name
Test status
Simulation time 21907464429 ps
CPU time 40.98 seconds
Started Mar 31 03:44:51 PM PDT 24
Finished Mar 31 03:45:33 PM PDT 24
Peak memory 425152 kb
Host smart-41c7f496-1f1a-4a66-ad5d-f457b0db2c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986979543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.986979543
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_override.3783993503
Short name T51
Test name
Test status
Simulation time 52886235 ps
CPU time 0.63 seconds
Started Mar 31 03:44:46 PM PDT 24
Finished Mar 31 03:44:47 PM PDT 24
Peak memory 203600 kb
Host smart-22a77525-cdc3-4b5d-ad2b-850237d6c4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783993503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.3783993503
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.2342904026
Short name T1071
Test name
Test status
Simulation time 201325233 ps
CPU time 3.38 seconds
Started Mar 31 03:44:48 PM PDT 24
Finished Mar 31 03:44:52 PM PDT 24
Peak memory 220760 kb
Host smart-7fcd9352-892b-439f-a2ed-87221e471d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342904026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.2342904026
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.3361251425
Short name T869
Test name
Test status
Simulation time 4541246715 ps
CPU time 28.16 seconds
Started Mar 31 03:44:50 PM PDT 24
Finished Mar 31 03:45:18 PM PDT 24
Peak memory 402104 kb
Host smart-99cf070d-e6ac-45de-802f-5745220cc8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361251425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.3361251425
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.2024531571
Short name T700
Test name
Test status
Simulation time 966385837 ps
CPU time 4.19 seconds
Started Mar 31 03:44:49 PM PDT 24
Finished Mar 31 03:44:53 PM PDT 24
Peak memory 203864 kb
Host smart-d03361d4-ad9f-459b-970e-49e21c5ac952
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024531571 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.2024531571
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.3282916517
Short name T1015
Test name
Test status
Simulation time 10081581871 ps
CPU time 87.72 seconds
Started Mar 31 03:44:51 PM PDT 24
Finished Mar 31 03:46:19 PM PDT 24
Peak memory 537068 kb
Host smart-187bde16-dd00-4b41-8a30-bbae81c64e52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282916517 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_fifo_reset_acq.3282916517
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.1967816150
Short name T511
Test name
Test status
Simulation time 10998789239 ps
CPU time 7.62 seconds
Started Mar 31 03:44:55 PM PDT 24
Finished Mar 31 03:45:03 PM PDT 24
Peak memory 285176 kb
Host smart-df162921-c99d-450c-92db-33546e1442e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967816150 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_tx.1967816150
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.3843966839
Short name T614
Test name
Test status
Simulation time 425957718 ps
CPU time 2.61 seconds
Started Mar 31 03:44:53 PM PDT 24
Finished Mar 31 03:44:58 PM PDT 24
Peak memory 203784 kb
Host smart-c54f990e-6354-45f3-9c09-07e865603b0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843966839 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_hrst.3843966839
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.2120709078
Short name T284
Test name
Test status
Simulation time 3928881613 ps
CPU time 5.09 seconds
Started Mar 31 03:44:51 PM PDT 24
Finished Mar 31 03:44:57 PM PDT 24
Peak memory 212036 kb
Host smart-82df80e2-1c05-487a-b60a-8726b1cb803e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120709078 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_intr_smoke.2120709078
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.1626392629
Short name T418
Test name
Test status
Simulation time 4611965740 ps
CPU time 3.96 seconds
Started Mar 31 03:44:49 PM PDT 24
Finished Mar 31 03:44:53 PM PDT 24
Peak memory 203892 kb
Host smart-34d09894-839c-4b31-aa5c-52add7eef5fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626392629 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.1626392629
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.2706355272
Short name T53
Test name
Test status
Simulation time 847404660 ps
CPU time 32.92 seconds
Started Mar 31 03:44:51 PM PDT 24
Finished Mar 31 03:45:24 PM PDT 24
Peak memory 203792 kb
Host smart-2626acce-638f-4437-8121-67686547c080
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706355272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ta
rget_smoke.2706355272
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.2663976798
Short name T593
Test name
Test status
Simulation time 2862977053 ps
CPU time 10.58 seconds
Started Mar 31 03:44:49 PM PDT 24
Finished Mar 31 03:45:00 PM PDT 24
Peak memory 211096 kb
Host smart-090b11e9-686b-4728-806f-dd84822bbeab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663976798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_rd.2663976798
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.3199594701
Short name T804
Test name
Test status
Simulation time 8884017353 ps
CPU time 27.17 seconds
Started Mar 31 03:44:50 PM PDT 24
Finished Mar 31 03:45:18 PM PDT 24
Peak memory 455204 kb
Host smart-380d4087-7da6-4f49-bf86-8f983cf21e3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199594701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stretch.3199594701
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.2386797507
Short name T459
Test name
Test status
Simulation time 19082646510 ps
CPU time 7.16 seconds
Started Mar 31 03:44:51 PM PDT 24
Finished Mar 31 03:44:59 PM PDT 24
Peak memory 212068 kb
Host smart-a374b0f8-c2f7-4f96-9403-6df78d7a91df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386797507 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.2386797507
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_alert_test.576549257
Short name T969
Test name
Test status
Simulation time 16635905 ps
CPU time 0.62 seconds
Started Mar 31 03:44:59 PM PDT 24
Finished Mar 31 03:45:00 PM PDT 24
Peak memory 203672 kb
Host smart-c8502d55-2bdb-47b0-8fa8-8414b2ab878c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576549257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.576549257
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.2347672956
Short name T846
Test name
Test status
Simulation time 366203923 ps
CPU time 1.64 seconds
Started Mar 31 03:44:53 PM PDT 24
Finished Mar 31 03:44:56 PM PDT 24
Peak memory 212064 kb
Host smart-18d2f9d7-28f7-4399-8a24-1cf6786838f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347672956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.2347672956
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.3592713018
Short name T80
Test name
Test status
Simulation time 235908753 ps
CPU time 5.29 seconds
Started Mar 31 03:44:53 PM PDT 24
Finished Mar 31 03:44:59 PM PDT 24
Peak memory 249096 kb
Host smart-f85adfe9-976a-4600-bd0d-dabd8fbf5e02
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592713018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.3592713018
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.1913352258
Short name T56
Test name
Test status
Simulation time 4100091768 ps
CPU time 158.99 seconds
Started Mar 31 03:44:54 PM PDT 24
Finished Mar 31 03:47:33 PM PDT 24
Peak memory 681256 kb
Host smart-9479ba36-3b83-4aa9-acaa-bc9dd6a28875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913352258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.1913352258
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.80610822
Short name T933
Test name
Test status
Simulation time 3881150454 ps
CPU time 28.03 seconds
Started Mar 31 03:44:55 PM PDT 24
Finished Mar 31 03:45:25 PM PDT 24
Peak memory 465468 kb
Host smart-5741f17a-39cb-4819-81d6-6c9e2a26f02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80610822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.80610822
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.2550312030
Short name T267
Test name
Test status
Simulation time 116461261 ps
CPU time 1.02 seconds
Started Mar 31 03:44:53 PM PDT 24
Finished Mar 31 03:44:56 PM PDT 24
Peak memory 203676 kb
Host smart-bf5cd4e1-580d-4d9e-a75c-9192e41fab99
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550312030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.2550312030
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.1089214436
Short name T565
Test name
Test status
Simulation time 786514701 ps
CPU time 4.7 seconds
Started Mar 31 03:44:56 PM PDT 24
Finished Mar 31 03:45:02 PM PDT 24
Peak memory 232900 kb
Host smart-1f5646ee-afd8-4bfa-986d-12628c1659f1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089214436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.1089214436
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.1308645601
Short name T902
Test name
Test status
Simulation time 3619851499 ps
CPU time 75.91 seconds
Started Mar 31 03:44:51 PM PDT 24
Finished Mar 31 03:46:07 PM PDT 24
Peak memory 991152 kb
Host smart-4a13e753-7910-49ae-9269-512fbbcc69e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308645601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.1308645601
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.2432054835
Short name T493
Test name
Test status
Simulation time 2781467154 ps
CPU time 4.48 seconds
Started Mar 31 03:45:03 PM PDT 24
Finished Mar 31 03:45:08 PM PDT 24
Peak memory 203912 kb
Host smart-acaa61b8-8166-4016-90c6-a3d7c441a6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432054835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.2432054835
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.2249699785
Short name T231
Test name
Test status
Simulation time 1124205854 ps
CPU time 21.14 seconds
Started Mar 31 03:44:55 PM PDT 24
Finished Mar 31 03:45:18 PM PDT 24
Peak memory 346392 kb
Host smart-dd651189-ff55-42c2-8a93-38c2802df44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249699785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.2249699785
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_override.1500738261
Short name T1140
Test name
Test status
Simulation time 26332296 ps
CPU time 0.68 seconds
Started Mar 31 03:44:55 PM PDT 24
Finished Mar 31 03:44:57 PM PDT 24
Peak memory 203508 kb
Host smart-4c25c0d5-a893-4957-b218-0fddf1c7df77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500738261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.1500738261
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.2465385496
Short name T24
Test name
Test status
Simulation time 12570316989 ps
CPU time 111.28 seconds
Started Mar 31 03:44:54 PM PDT 24
Finished Mar 31 03:46:46 PM PDT 24
Peak memory 938308 kb
Host smart-24e199f4-34c0-47e5-adfd-bf205419f445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465385496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.2465385496
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.2427942989
Short name T773
Test name
Test status
Simulation time 3907766847 ps
CPU time 52.28 seconds
Started Mar 31 03:44:56 PM PDT 24
Finished Mar 31 03:45:49 PM PDT 24
Peak memory 345240 kb
Host smart-ed01677d-55f5-4538-9415-09e225912d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427942989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.2427942989
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.3028121596
Short name T548
Test name
Test status
Simulation time 2878745256 ps
CPU time 3.54 seconds
Started Mar 31 03:44:57 PM PDT 24
Finished Mar 31 03:45:01 PM PDT 24
Peak memory 203900 kb
Host smart-fa51a172-9e54-4a87-96a6-7d3ab26d4d23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028121596 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.3028121596
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.494690242
Short name T1202
Test name
Test status
Simulation time 10252677455 ps
CPU time 19.98 seconds
Started Mar 31 03:44:57 PM PDT 24
Finished Mar 31 03:45:18 PM PDT 24
Peak memory 330368 kb
Host smart-4fe294b2-8513-4814-a558-c463f4d6ae0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494690242 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_acq.494690242
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.1618272565
Short name T697
Test name
Test status
Simulation time 10210151994 ps
CPU time 16.36 seconds
Started Mar 31 03:44:57 PM PDT 24
Finished Mar 31 03:45:13 PM PDT 24
Peak memory 372968 kb
Host smart-733fff0a-8769-4aaa-a67c-147d0884deb7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618272565 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.1618272565
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.2438525879
Short name T261
Test name
Test status
Simulation time 400077625 ps
CPU time 2.33 seconds
Started Mar 31 03:45:02 PM PDT 24
Finished Mar 31 03:45:05 PM PDT 24
Peak memory 203796 kb
Host smart-49c01191-b317-44b9-b94e-50542c49fe57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438525879 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_hrst.2438525879
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.2323662516
Short name T289
Test name
Test status
Simulation time 3582089259 ps
CPU time 5.04 seconds
Started Mar 31 03:45:02 PM PDT 24
Finished Mar 31 03:45:07 PM PDT 24
Peak memory 203880 kb
Host smart-12567dbc-3afe-4d62-a65d-c1854d27f2b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323662516 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.2323662516
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.4142042497
Short name T986
Test name
Test status
Simulation time 5143614075 ps
CPU time 47.61 seconds
Started Mar 31 03:44:52 PM PDT 24
Finished Mar 31 03:45:40 PM PDT 24
Peak memory 203868 kb
Host smart-a7c2f8d4-fcd7-49ef-928f-c3111bd2b265
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142042497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_ta
rget_smoke.4142042497
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.2723569833
Short name T260
Test name
Test status
Simulation time 1356036339 ps
CPU time 20.98 seconds
Started Mar 31 03:44:53 PM PDT 24
Finished Mar 31 03:45:14 PM PDT 24
Peak memory 228624 kb
Host smart-afe066ef-8721-486b-a09d-f362d9e417fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723569833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_rd.2723569833
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.3303908514
Short name T262
Test name
Test status
Simulation time 20695001692 ps
CPU time 12.06 seconds
Started Mar 31 03:44:54 PM PDT 24
Finished Mar 31 03:45:07 PM PDT 24
Peak memory 203884 kb
Host smart-665fcac5-7f12-4410-af8a-b7d57d15e901
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303908514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_wr.3303908514
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.1446856658
Short name T780
Test name
Test status
Simulation time 43508208757 ps
CPU time 382.7 seconds
Started Mar 31 03:44:58 PM PDT 24
Finished Mar 31 03:51:21 PM PDT 24
Peak memory 2369384 kb
Host smart-5ce2df78-24ac-462f-8545-c84434c32a9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446856658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.1446856658
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.105119034
Short name T624
Test name
Test status
Simulation time 2118490802 ps
CPU time 6.73 seconds
Started Mar 31 03:45:03 PM PDT 24
Finished Mar 31 03:45:10 PM PDT 24
Peak memory 203844 kb
Host smart-f6e308ce-f1d5-458b-8d23-19ed3155305c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105119034 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_timeout.105119034
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_alert_test.3654982121
Short name T1084
Test name
Test status
Simulation time 27882359 ps
CPU time 0.61 seconds
Started Mar 31 03:45:12 PM PDT 24
Finished Mar 31 03:45:13 PM PDT 24
Peak memory 203644 kb
Host smart-cee63d9a-daea-4835-9b77-d3ce6cdb17b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654982121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.3654982121
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.1712247922
Short name T499
Test name
Test status
Simulation time 49057126 ps
CPU time 1.35 seconds
Started Mar 31 03:45:10 PM PDT 24
Finished Mar 31 03:45:11 PM PDT 24
Peak memory 211988 kb
Host smart-14c727ec-ab23-4fc1-9f06-1f1625a8e47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712247922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.1712247922
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.2672219799
Short name T263
Test name
Test status
Simulation time 1153517629 ps
CPU time 4.94 seconds
Started Mar 31 03:45:06 PM PDT 24
Finished Mar 31 03:45:11 PM PDT 24
Peak memory 257112 kb
Host smart-29b226b3-8b43-44bc-b3ea-b9b150454362
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672219799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.2672219799
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.275765849
Short name T1061
Test name
Test status
Simulation time 6450477144 ps
CPU time 54.98 seconds
Started Mar 31 03:45:08 PM PDT 24
Finished Mar 31 03:46:03 PM PDT 24
Peak memory 588644 kb
Host smart-f65edcc6-3270-4c2e-b63c-8ad57b52d9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275765849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.275765849
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.418127795
Short name T1196
Test name
Test status
Simulation time 8428090386 ps
CPU time 160.99 seconds
Started Mar 31 03:45:02 PM PDT 24
Finished Mar 31 03:47:44 PM PDT 24
Peak memory 699768 kb
Host smart-811c5f0e-25c9-452f-8416-095e7d488883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418127795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.418127795
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.4226925328
Short name T112
Test name
Test status
Simulation time 143863642 ps
CPU time 1.05 seconds
Started Mar 31 03:45:08 PM PDT 24
Finished Mar 31 03:45:09 PM PDT 24
Peak memory 203728 kb
Host smart-7bcd1bb0-5aa0-4937-8db9-430c94f40d64
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226925328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_f
mt.4226925328
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.1679023196
Short name T880
Test name
Test status
Simulation time 268321777 ps
CPU time 2.94 seconds
Started Mar 31 03:45:07 PM PDT 24
Finished Mar 31 03:45:10 PM PDT 24
Peak memory 203792 kb
Host smart-93a23216-11ad-4e69-9657-d5ca741760a6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679023196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.1679023196
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.2558664227
Short name T660
Test name
Test status
Simulation time 32854606054 ps
CPU time 272.81 seconds
Started Mar 31 03:45:00 PM PDT 24
Finished Mar 31 03:49:33 PM PDT 24
Peak memory 1104924 kb
Host smart-5fb1a194-8f39-46cc-96ca-e92f2176785c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558664227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.2558664227
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.3898005602
Short name T206
Test name
Test status
Simulation time 1643348843 ps
CPU time 5.43 seconds
Started Mar 31 03:45:14 PM PDT 24
Finished Mar 31 03:45:19 PM PDT 24
Peak memory 203860 kb
Host smart-05d86b1d-3545-47e8-ad23-226eac167775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898005602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.3898005602
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.1918065235
Short name T1090
Test name
Test status
Simulation time 1498053414 ps
CPU time 77.69 seconds
Started Mar 31 03:45:13 PM PDT 24
Finished Mar 31 03:46:31 PM PDT 24
Peak memory 383164 kb
Host smart-d7fc1b9b-4637-4f33-b061-3229f485da0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918065235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.1918065235
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_host_override.1053810076
Short name T336
Test name
Test status
Simulation time 87878754 ps
CPU time 0.74 seconds
Started Mar 31 03:45:01 PM PDT 24
Finished Mar 31 03:45:03 PM PDT 24
Peak memory 203588 kb
Host smart-83259ff4-9d2e-4af9-9191-fa8e445cf926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053810076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.1053810076
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.3909358040
Short name T1154
Test name
Test status
Simulation time 2570679915 ps
CPU time 178.34 seconds
Started Mar 31 03:45:08 PM PDT 24
Finished Mar 31 03:48:06 PM PDT 24
Peak memory 825048 kb
Host smart-1f956bbd-600b-4aa1-8992-9e5f4c250402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909358040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.3909358040
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.455926402
Short name T417
Test name
Test status
Simulation time 5801430456 ps
CPU time 33.11 seconds
Started Mar 31 03:44:58 PM PDT 24
Finished Mar 31 03:45:31 PM PDT 24
Peak memory 383180 kb
Host smart-e88702ca-5166-4c58-937b-e6ab804c621d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455926402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.455926402
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.3589323693
Short name T664
Test name
Test status
Simulation time 997476761 ps
CPU time 5.1 seconds
Started Mar 31 03:45:03 PM PDT 24
Finished Mar 31 03:45:08 PM PDT 24
Peak memory 212028 kb
Host smart-aa732139-375c-43c7-932d-80901fea1ca8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589323693 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.3589323693
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.2087143362
Short name T989
Test name
Test status
Simulation time 10058896374 ps
CPU time 84.7 seconds
Started Mar 31 03:45:03 PM PDT 24
Finished Mar 31 03:46:28 PM PDT 24
Peak memory 557868 kb
Host smart-df121535-c383-4f49-924b-f1a2262fb3c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087143362 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_fifo_reset_acq.2087143362
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.3892384805
Short name T86
Test name
Test status
Simulation time 10080481762 ps
CPU time 99.91 seconds
Started Mar 31 03:45:09 PM PDT 24
Finished Mar 31 03:46:49 PM PDT 24
Peak memory 748448 kb
Host smart-7cd6aae4-9adf-47be-b356-765f4c06b3ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892384805 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_tx.3892384805
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.242650293
Short name T948
Test name
Test status
Simulation time 343440669 ps
CPU time 2.25 seconds
Started Mar 31 03:45:04 PM PDT 24
Finished Mar 31 03:45:07 PM PDT 24
Peak memory 203844 kb
Host smart-f4b036a5-b9a8-4368-9ac5-52e68cc6f912
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242650293 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 15.i2c_target_hrst.242650293
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.1512518525
Short name T855
Test name
Test status
Simulation time 1078784440 ps
CPU time 5.32 seconds
Started Mar 31 03:45:02 PM PDT 24
Finished Mar 31 03:45:08 PM PDT 24
Peak memory 203800 kb
Host smart-aed1707b-a5b8-4292-ace4-df8928a3ef7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512518525 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_intr_smoke.1512518525
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.176439374
Short name T644
Test name
Test status
Simulation time 2723655938 ps
CPU time 56.71 seconds
Started Mar 31 03:45:06 PM PDT 24
Finished Mar 31 03:46:03 PM PDT 24
Peak memory 203832 kb
Host smart-0ce4492a-4c3f-4a4f-9085-33fd5cf38186
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176439374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_tar
get_smoke.176439374
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.1827133592
Short name T845
Test name
Test status
Simulation time 1495146142 ps
CPU time 32.11 seconds
Started Mar 31 03:45:05 PM PDT 24
Finished Mar 31 03:45:37 PM PDT 24
Peak memory 203784 kb
Host smart-3386ea64-7e40-4e76-8a42-d09d4a6ac2b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827133592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.1827133592
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.2507685111
Short name T1112
Test name
Test status
Simulation time 20143894050 ps
CPU time 736.37 seconds
Started Mar 31 03:45:08 PM PDT 24
Finished Mar 31 03:57:25 PM PDT 24
Peak memory 3856704 kb
Host smart-cb7304fe-14e5-4ea2-8e63-06a8fe9a5681
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507685111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_
target_stretch.2507685111
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.662199467
Short name T1141
Test name
Test status
Simulation time 2511515594 ps
CPU time 6.44 seconds
Started Mar 31 03:45:09 PM PDT 24
Finished Mar 31 03:45:16 PM PDT 24
Peak memory 209956 kb
Host smart-16de9b9e-a300-4f49-8add-26abff205f8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662199467 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_timeout.662199467
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_alert_test.3758304387
Short name T949
Test name
Test status
Simulation time 17591816 ps
CPU time 0.61 seconds
Started Mar 31 03:45:16 PM PDT 24
Finished Mar 31 03:45:17 PM PDT 24
Peak memory 203736 kb
Host smart-f1323085-e075-4c16-a5ed-ce7eb311d2f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758304387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.3758304387
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.2766258682
Short name T1150
Test name
Test status
Simulation time 63254995 ps
CPU time 1.51 seconds
Started Mar 31 03:45:11 PM PDT 24
Finished Mar 31 03:45:13 PM PDT 24
Peak memory 212040 kb
Host smart-1a6e3c4c-c015-4a5f-89a2-d8a07786fb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766258682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.2766258682
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.135583359
Short name T573
Test name
Test status
Simulation time 1639268421 ps
CPU time 4.75 seconds
Started Mar 31 03:45:11 PM PDT 24
Finished Mar 31 03:45:16 PM PDT 24
Peak memory 244028 kb
Host smart-5669dfa9-f5a9-4b09-a53d-4e98fce34196
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135583359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_empt
y.135583359
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.3617322841
Short name T691
Test name
Test status
Simulation time 4480400365 ps
CPU time 85.26 seconds
Started Mar 31 03:45:11 PM PDT 24
Finished Mar 31 03:46:36 PM PDT 24
Peak memory 761184 kb
Host smart-42daaec1-0855-42d1-b443-c18a86d398d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617322841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.3617322841
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.854755617
Short name T900
Test name
Test status
Simulation time 1850701981 ps
CPU time 49.08 seconds
Started Mar 31 03:45:09 PM PDT 24
Finished Mar 31 03:45:58 PM PDT 24
Peak memory 536008 kb
Host smart-c2a3c992-9f54-4a8e-81d5-76125927ebfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854755617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.854755617
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.2768810110
Short name T765
Test name
Test status
Simulation time 131094215 ps
CPU time 1.07 seconds
Started Mar 31 03:45:11 PM PDT 24
Finished Mar 31 03:45:12 PM PDT 24
Peak memory 203800 kb
Host smart-74f08aa4-4e84-46e1-9ac3-3eda3d817236
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768810110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_f
mt.2768810110
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.604563045
Short name T497
Test name
Test status
Simulation time 478302700 ps
CPU time 3.43 seconds
Started Mar 31 03:45:11 PM PDT 24
Finished Mar 31 03:45:15 PM PDT 24
Peak memory 221252 kb
Host smart-5a05cb92-7713-44eb-8e64-13068ec1c9ef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604563045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx.
604563045
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.1642018881
Short name T520
Test name
Test status
Simulation time 6437383614 ps
CPU time 218.82 seconds
Started Mar 31 03:45:14 PM PDT 24
Finished Mar 31 03:48:53 PM PDT 24
Peak memory 902600 kb
Host smart-8d48c0be-216e-4b0e-b310-9b6e10656738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642018881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.1642018881
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.2879416388
Short name T833
Test name
Test status
Simulation time 356423553 ps
CPU time 14.22 seconds
Started Mar 31 03:45:21 PM PDT 24
Finished Mar 31 03:45:35 PM PDT 24
Peak memory 203844 kb
Host smart-91a4a3d4-d522-4170-a054-a7108a8d2e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879416388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.2879416388
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.2965771397
Short name T581
Test name
Test status
Simulation time 3651702595 ps
CPU time 48.91 seconds
Started Mar 31 03:45:21 PM PDT 24
Finished Mar 31 03:46:10 PM PDT 24
Peak memory 318224 kb
Host smart-79c87292-e073-4a76-b5fe-3b2785445976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965771397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.2965771397
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_override.4124692103
Short name T184
Test name
Test status
Simulation time 188860642 ps
CPU time 0.69 seconds
Started Mar 31 03:45:11 PM PDT 24
Finished Mar 31 03:45:12 PM PDT 24
Peak memory 203564 kb
Host smart-bc7e2272-e0f6-4373-b517-463377aaf41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124692103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.4124692103
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.2776699203
Short name T590
Test name
Test status
Simulation time 2685544582 ps
CPU time 79.35 seconds
Started Mar 31 03:45:17 PM PDT 24
Finished Mar 31 03:46:36 PM PDT 24
Peak memory 804772 kb
Host smart-29ad2d2b-fa87-433e-a985-182c566e7564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776699203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.2776699203
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.3342184945
Short name T306
Test name
Test status
Simulation time 4426141333 ps
CPU time 57.91 seconds
Started Mar 31 03:45:14 PM PDT 24
Finished Mar 31 03:46:13 PM PDT 24
Peak memory 310344 kb
Host smart-cdef8d29-f7c3-40e6-8782-1651d1c31b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342184945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.3342184945
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.1687361180
Short name T853
Test name
Test status
Simulation time 1022510184 ps
CPU time 4.78 seconds
Started Mar 31 03:45:23 PM PDT 24
Finished Mar 31 03:45:28 PM PDT 24
Peak memory 203940 kb
Host smart-a65a3474-8fc2-4631-8f6c-223eaa1f68e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687361180 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.1687361180
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.2433482611
Short name T987
Test name
Test status
Simulation time 10642939943 ps
CPU time 6.93 seconds
Started Mar 31 03:45:14 PM PDT 24
Finished Mar 31 03:45:21 PM PDT 24
Peak memory 245536 kb
Host smart-94605ed9-be0f-436d-a24d-ac02ea664c64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433482611 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_reset_acq.2433482611
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.441120239
Short name T1118
Test name
Test status
Simulation time 10090480365 ps
CPU time 38.98 seconds
Started Mar 31 03:45:16 PM PDT 24
Finished Mar 31 03:45:55 PM PDT 24
Peak memory 443256 kb
Host smart-0a6a0604-acac-493b-9d6d-d5480088233c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441120239 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.i2c_target_fifo_reset_tx.441120239
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.2505515881
Short name T1194
Test name
Test status
Simulation time 2046417158 ps
CPU time 3.06 seconds
Started Mar 31 03:45:21 PM PDT 24
Finished Mar 31 03:45:24 PM PDT 24
Peak memory 203824 kb
Host smart-2129d419-2401-432a-9768-5debd689d5a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505515881 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_hrst.2505515881
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.3365857116
Short name T936
Test name
Test status
Simulation time 537990849 ps
CPU time 2.94 seconds
Started Mar 31 03:45:10 PM PDT 24
Finished Mar 31 03:45:14 PM PDT 24
Peak memory 203804 kb
Host smart-cbf37a86-fb2f-4278-9311-afc323baab3b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365857116 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.3365857116
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.1759092810
Short name T397
Test name
Test status
Simulation time 5872113311 ps
CPU time 41.68 seconds
Started Mar 31 03:45:12 PM PDT 24
Finished Mar 31 03:45:54 PM PDT 24
Peak memory 203864 kb
Host smart-a3ccea85-6b1d-47ed-8cdf-a58e1949fcef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759092810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta
rget_smoke.1759092810
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.3051794244
Short name T835
Test name
Test status
Simulation time 7085460305 ps
CPU time 26.17 seconds
Started Mar 31 03:45:16 PM PDT 24
Finished Mar 31 03:45:43 PM PDT 24
Peak memory 232848 kb
Host smart-acfbeae7-4ed3-448c-a2a3-732a62a9a043
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051794244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_rd.3051794244
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.3038016766
Short name T1048
Test name
Test status
Simulation time 25720585177 ps
CPU time 4.66 seconds
Started Mar 31 03:45:15 PM PDT 24
Finished Mar 31 03:45:20 PM PDT 24
Peak memory 203848 kb
Host smart-15111642-1db4-4981-80ef-93af64cc5060
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038016766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_wr.3038016766
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.512876987
Short name T1135
Test name
Test status
Simulation time 6921977342 ps
CPU time 88.78 seconds
Started Mar 31 03:45:13 PM PDT 24
Finished Mar 31 03:46:42 PM PDT 24
Peak memory 559152 kb
Host smart-6ad74b7d-01ee-4129-b63f-f9e0465beb7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512876987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_t
arget_stretch.512876987
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.136387760
Short name T650
Test name
Test status
Simulation time 6794141537 ps
CPU time 7.15 seconds
Started Mar 31 03:45:13 PM PDT 24
Finished Mar 31 03:45:20 PM PDT 24
Peak memory 212076 kb
Host smart-a18d7f3c-558c-45ea-89a1-f27414290b19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136387760 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_timeout.136387760
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_unexp_stop.1264818756
Short name T457
Test name
Test status
Simulation time 4677637446 ps
CPU time 6.45 seconds
Started Mar 31 03:45:12 PM PDT 24
Finished Mar 31 03:45:19 PM PDT 24
Peak memory 206900 kb
Host smart-9de23153-8d0d-4ca5-8b38-aeb1aa7bbb8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264818756 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.i2c_target_unexp_stop.1264818756
Directory /workspace/16.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/17.i2c_alert_test.3495862813
Short name T929
Test name
Test status
Simulation time 38632711 ps
CPU time 0.6 seconds
Started Mar 31 03:45:21 PM PDT 24
Finished Mar 31 03:45:21 PM PDT 24
Peak memory 203668 kb
Host smart-541343b4-0f5c-4a41-8493-fdb7d067b192
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495862813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.3495862813
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.3579258798
Short name T338
Test name
Test status
Simulation time 103146952 ps
CPU time 1.96 seconds
Started Mar 31 03:45:17 PM PDT 24
Finished Mar 31 03:45:20 PM PDT 24
Peak memory 212012 kb
Host smart-7a443c4a-874e-4d80-b3e0-56a125b1b68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579258798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.3579258798
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.3976831223
Short name T305
Test name
Test status
Simulation time 4303348398 ps
CPU time 7.48 seconds
Started Mar 31 03:45:29 PM PDT 24
Finished Mar 31 03:45:37 PM PDT 24
Peak memory 271280 kb
Host smart-413d48b7-63d5-4097-b60c-284d141db5a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976831223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_emp
ty.3976831223
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.1075820917
Short name T65
Test name
Test status
Simulation time 9221890773 ps
CPU time 172.63 seconds
Started Mar 31 03:45:17 PM PDT 24
Finished Mar 31 03:48:10 PM PDT 24
Peak memory 734976 kb
Host smart-b323769e-a113-493e-8e08-978aa171ec5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075820917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.1075820917
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.1306913182
Short name T622
Test name
Test status
Simulation time 1280196823 ps
CPU time 33.61 seconds
Started Mar 31 03:45:20 PM PDT 24
Finished Mar 31 03:45:54 PM PDT 24
Peak memory 485420 kb
Host smart-5c69ef62-8b31-42df-9466-69b6c363fedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306913182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.1306913182
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.1202020308
Short name T750
Test name
Test status
Simulation time 126995063 ps
CPU time 1.12 seconds
Started Mar 31 03:45:19 PM PDT 24
Finished Mar 31 03:45:20 PM PDT 24
Peak memory 203752 kb
Host smart-31976a0a-4f14-43fc-8c38-cd2c773c494b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202020308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.1202020308
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.479671614
Short name T311
Test name
Test status
Simulation time 841123888 ps
CPU time 8.15 seconds
Started Mar 31 03:45:17 PM PDT 24
Finished Mar 31 03:45:25 PM PDT 24
Peak memory 203840 kb
Host smart-f92f61e3-f6cb-4dc8-b6b9-0fc4d7f6e4cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479671614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx.
479671614
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.1997476834
Short name T1051
Test name
Test status
Simulation time 13203970215 ps
CPU time 84.42 seconds
Started Mar 31 03:45:23 PM PDT 24
Finished Mar 31 03:46:48 PM PDT 24
Peak memory 994100 kb
Host smart-302c2e7b-34a2-428b-a3fe-ab5ae4e7997f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997476834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.1997476834
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.1372021288
Short name T1103
Test name
Test status
Simulation time 471519337 ps
CPU time 3.83 seconds
Started Mar 31 03:45:21 PM PDT 24
Finished Mar 31 03:45:25 PM PDT 24
Peak memory 203844 kb
Host smart-3ae0ec62-195e-4bb6-975f-d6dc79764c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372021288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.1372021288
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.878527819
Short name T856
Test name
Test status
Simulation time 4626879053 ps
CPU time 24.19 seconds
Started Mar 31 03:45:18 PM PDT 24
Finished Mar 31 03:45:42 PM PDT 24
Peak memory 344164 kb
Host smart-579fa426-1431-4203-8a86-948dde2765ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878527819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.878527819
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.3427573132
Short name T1082
Test name
Test status
Simulation time 25769977 ps
CPU time 0.67 seconds
Started Mar 31 03:45:18 PM PDT 24
Finished Mar 31 03:45:19 PM PDT 24
Peak memory 203580 kb
Host smart-88b5689b-2e8c-494d-ba3e-1a295c3aa77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427573132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.3427573132
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.3719904244
Short name T1108
Test name
Test status
Simulation time 11537710939 ps
CPU time 28.78 seconds
Started Mar 31 03:45:22 PM PDT 24
Finished Mar 31 03:45:51 PM PDT 24
Peak memory 332028 kb
Host smart-e65aea85-5666-46e1-bd8d-93bd8a7a8ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719904244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.3719904244
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stress_all.2049995538
Short name T172
Test name
Test status
Simulation time 43391032672 ps
CPU time 200.95 seconds
Started Mar 31 03:45:18 PM PDT 24
Finished Mar 31 03:48:39 PM PDT 24
Peak memory 851548 kb
Host smart-685efaec-deeb-4126-bcbb-2b8d76960bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049995538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.2049995538
Directory /workspace/17.i2c_host_stress_all/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.3996874404
Short name T1206
Test name
Test status
Simulation time 1642021493 ps
CPU time 4.16 seconds
Started Mar 31 03:45:18 PM PDT 24
Finished Mar 31 03:45:22 PM PDT 24
Peak memory 213144 kb
Host smart-111b49d9-0074-4f78-b20e-f4fe0ad2b580
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996874404 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.3996874404
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.3650363858
Short name T704
Test name
Test status
Simulation time 10221913706 ps
CPU time 16.51 seconds
Started Mar 31 03:45:21 PM PDT 24
Finished Mar 31 03:45:37 PM PDT 24
Peak memory 294008 kb
Host smart-4a444b79-f3d3-4b66-a06c-856a2128010c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650363858 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_fifo_reset_acq.3650363858
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.3290838046
Short name T415
Test name
Test status
Simulation time 10175112210 ps
CPU time 110.93 seconds
Started Mar 31 03:45:20 PM PDT 24
Finished Mar 31 03:47:11 PM PDT 24
Peak memory 732908 kb
Host smart-83c97106-7a8a-4c80-83fa-458149c0e980
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290838046 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_tx.3290838046
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.475631192
Short name T219
Test name
Test status
Simulation time 1470021845 ps
CPU time 2.28 seconds
Started Mar 31 03:45:21 PM PDT 24
Finished Mar 31 03:45:23 PM PDT 24
Peak memory 203772 kb
Host smart-c5a54ec9-aa9d-4cd8-8d45-f919b931559d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475631192 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 17.i2c_target_hrst.475631192
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.885667204
Short name T1028
Test name
Test status
Simulation time 778419727 ps
CPU time 3.87 seconds
Started Mar 31 03:45:23 PM PDT 24
Finished Mar 31 03:45:27 PM PDT 24
Peak memory 203884 kb
Host smart-10852c19-226b-4954-90f0-0bf9256f7cc9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885667204 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_intr_smoke.885667204
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.204919795
Short name T115
Test name
Test status
Simulation time 5073841713 ps
CPU time 6.79 seconds
Started Mar 31 03:45:21 PM PDT 24
Finished Mar 31 03:45:28 PM PDT 24
Peak memory 203880 kb
Host smart-0f1c1368-a0fc-4fbd-9c5b-f251358e72ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204919795 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.204919795
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.3273739288
Short name T1213
Test name
Test status
Simulation time 2429782913 ps
CPU time 22.49 seconds
Started Mar 31 03:45:17 PM PDT 24
Finished Mar 31 03:45:39 PM PDT 24
Peak memory 203872 kb
Host smart-8f5a6ce6-8b51-457b-9907-04e79f291d12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273739288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.3273739288
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.3594306840
Short name T583
Test name
Test status
Simulation time 2349716356 ps
CPU time 52.73 seconds
Started Mar 31 03:45:18 PM PDT 24
Finished Mar 31 03:46:11 PM PDT 24
Peak memory 205284 kb
Host smart-25c81e8e-a5bd-4fca-8c93-23b4e7b7d8ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594306840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_rd.3594306840
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.1841446666
Short name T1142
Test name
Test status
Simulation time 7578222086 ps
CPU time 20.92 seconds
Started Mar 31 03:45:18 PM PDT 24
Finished Mar 31 03:45:39 PM PDT 24
Peak memory 415428 kb
Host smart-3b7f1185-b46f-4bc1-853e-de297735a254
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841446666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.1841446666
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.703288426
Short name T826
Test name
Test status
Simulation time 20569123951 ps
CPU time 7.44 seconds
Started Mar 31 03:45:23 PM PDT 24
Finished Mar 31 03:45:31 PM PDT 24
Peak memory 212176 kb
Host smart-95879000-1f8d-4df7-8314-1989fdb3a8b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703288426 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_timeout.703288426
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_alert_test.3676849133
Short name T321
Test name
Test status
Simulation time 47716314 ps
CPU time 0.62 seconds
Started Mar 31 03:45:28 PM PDT 24
Finished Mar 31 03:45:29 PM PDT 24
Peak memory 203704 kb
Host smart-58744da0-5298-4afd-91d2-76a51d52eda6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676849133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.3676849133
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.1000256699
Short name T810
Test name
Test status
Simulation time 360341858 ps
CPU time 1.87 seconds
Started Mar 31 03:45:22 PM PDT 24
Finished Mar 31 03:45:24 PM PDT 24
Peak memory 211972 kb
Host smart-138a9946-abb2-4741-9e42-c29426f4f774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000256699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.1000256699
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.2160320014
Short name T1037
Test name
Test status
Simulation time 507597091 ps
CPU time 3.07 seconds
Started Mar 31 03:45:22 PM PDT 24
Finished Mar 31 03:45:25 PM PDT 24
Peak memory 221900 kb
Host smart-67e2ea8e-8c1e-493d-bced-214461b9395b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160320014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_emp
ty.2160320014
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.2963768834
Short name T610
Test name
Test status
Simulation time 2438031618 ps
CPU time 39.49 seconds
Started Mar 31 03:45:21 PM PDT 24
Finished Mar 31 03:46:00 PM PDT 24
Peak memory 497216 kb
Host smart-0cddd6e4-499e-4b78-8077-f80e35589b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963768834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.2963768834
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.263694906
Short name T330
Test name
Test status
Simulation time 30036479626 ps
CPU time 44.96 seconds
Started Mar 31 03:45:15 PM PDT 24
Finished Mar 31 03:46:00 PM PDT 24
Peak memory 576868 kb
Host smart-1734f18b-a522-47bb-b822-3b0460361a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263694906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.263694906
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.3389394584
Short name T523
Test name
Test status
Simulation time 142447282 ps
CPU time 1 seconds
Started Mar 31 03:45:17 PM PDT 24
Finished Mar 31 03:45:19 PM PDT 24
Peak memory 203692 kb
Host smart-286cb23d-c1e7-41a7-bf44-74248637b556
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389394584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f
mt.3389394584
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.2247304976
Short name T865
Test name
Test status
Simulation time 130417721 ps
CPU time 7.17 seconds
Started Mar 31 03:45:16 PM PDT 24
Finished Mar 31 03:45:23 PM PDT 24
Peak memory 226384 kb
Host smart-317c69ea-50c1-44da-ae72-3d446b016c61
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247304976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.2247304976
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.2074098312
Short name T571
Test name
Test status
Simulation time 3775316975 ps
CPU time 285.3 seconds
Started Mar 31 03:45:25 PM PDT 24
Finished Mar 31 03:50:10 PM PDT 24
Peak memory 1113636 kb
Host smart-445a7e10-9fd8-4701-bb20-0fb002ce5ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074098312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.2074098312
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.817322240
Short name T535
Test name
Test status
Simulation time 595062281 ps
CPU time 23.59 seconds
Started Mar 31 03:45:22 PM PDT 24
Finished Mar 31 03:45:46 PM PDT 24
Peak memory 203792 kb
Host smart-9e2aac67-26c8-4692-b868-f7f211894927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817322240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.817322240
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.2355874095
Short name T1072
Test name
Test status
Simulation time 3173444269 ps
CPU time 32.58 seconds
Started Mar 31 03:45:19 PM PDT 24
Finished Mar 31 03:45:52 PM PDT 24
Peak memory 454084 kb
Host smart-f53bff31-44c5-4c9f-8e97-dc634e4b311d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355874095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.2355874095
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/18.i2c_host_override.2765064446
Short name T477
Test name
Test status
Simulation time 16462953 ps
CPU time 0.66 seconds
Started Mar 31 03:45:15 PM PDT 24
Finished Mar 31 03:45:16 PM PDT 24
Peak memory 203624 kb
Host smart-421db6cc-51bf-40f7-a537-cfcfb99244e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765064446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.2765064446
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.2199460632
Short name T746
Test name
Test status
Simulation time 1712197540 ps
CPU time 12.83 seconds
Started Mar 31 03:45:20 PM PDT 24
Finished Mar 31 03:45:33 PM PDT 24
Peak memory 242128 kb
Host smart-516a641f-3d31-4064-9d87-deb6f510a993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199460632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.2199460632
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.3931635779
Short name T215
Test name
Test status
Simulation time 1169156125 ps
CPU time 22.15 seconds
Started Mar 31 03:45:16 PM PDT 24
Finished Mar 31 03:45:38 PM PDT 24
Peak memory 330080 kb
Host smart-a7c31a54-00e6-4c8f-ad0b-5b649fa13c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931635779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.3931635779
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.2950187053
Short name T735
Test name
Test status
Simulation time 1844765303 ps
CPU time 4.34 seconds
Started Mar 31 03:45:22 PM PDT 24
Finished Mar 31 03:45:26 PM PDT 24
Peak memory 203812 kb
Host smart-124fe568-867b-41f5-a930-19ab47c92ab8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950187053 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.2950187053
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.1458060157
Short name T97
Test name
Test status
Simulation time 11057299673 ps
CPU time 5.62 seconds
Started Mar 31 03:45:24 PM PDT 24
Finished Mar 31 03:45:30 PM PDT 24
Peak memory 239920 kb
Host smart-548dbc09-071e-4450-bc34-a405cfc1110c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458060157 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_fifo_reset_acq.1458060157
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.4190086314
Short name T616
Test name
Test status
Simulation time 10071815636 ps
CPU time 83.65 seconds
Started Mar 31 03:45:23 PM PDT 24
Finished Mar 31 03:46:47 PM PDT 24
Peak memory 642028 kb
Host smart-4b6ca403-ef14-4138-8f4e-8b1d1bf44cb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190086314 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.4190086314
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.2079614927
Short name T580
Test name
Test status
Simulation time 876809663 ps
CPU time 2.59 seconds
Started Mar 31 03:45:26 PM PDT 24
Finished Mar 31 03:45:29 PM PDT 24
Peak memory 203816 kb
Host smart-1b177e0f-f5c9-4933-8000-c706f7426b82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079614927 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_hrst.2079614927
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.2008073027
Short name T1198
Test name
Test status
Simulation time 3035973511 ps
CPU time 4.48 seconds
Started Mar 31 03:45:21 PM PDT 24
Finished Mar 31 03:45:26 PM PDT 24
Peak memory 205204 kb
Host smart-6b7dc483-1ad0-4bdf-80c4-4faa2095e625
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008073027 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.2008073027
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.836288400
Short name T1062
Test name
Test status
Simulation time 6715948059 ps
CPU time 18.42 seconds
Started Mar 31 03:45:24 PM PDT 24
Finished Mar 31 03:45:43 PM PDT 24
Peak memory 203836 kb
Host smart-89ed78aa-2e33-40e9-865d-f7ec12ab1e96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836288400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_tar
get_smoke.836288400
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.2835436926
Short name T1205
Test name
Test status
Simulation time 7431447430 ps
CPU time 34.37 seconds
Started Mar 31 03:45:20 PM PDT 24
Finished Mar 31 03:45:54 PM PDT 24
Peak memory 228248 kb
Host smart-9258c371-1dbc-4656-8a14-11948b6dab44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835436926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_rd.2835436926
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.3094174829
Short name T634
Test name
Test status
Simulation time 37108421042 ps
CPU time 256.09 seconds
Started Mar 31 03:45:21 PM PDT 24
Finished Mar 31 03:49:38 PM PDT 24
Peak memory 2104608 kb
Host smart-d83cdb13-b50b-45af-9dc5-58745b90d584
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094174829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.3094174829
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.3094115175
Short name T1105
Test name
Test status
Simulation time 1455602238 ps
CPU time 7.36 seconds
Started Mar 31 03:45:22 PM PDT 24
Finished Mar 31 03:45:29 PM PDT 24
Peak memory 212412 kb
Host smart-1830fe6a-d36e-4acd-b3da-2c5bd45086f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094115175 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_timeout.3094115175
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_alert_test.1826286222
Short name T791
Test name
Test status
Simulation time 19874024 ps
CPU time 0.63 seconds
Started Mar 31 03:45:29 PM PDT 24
Finished Mar 31 03:45:30 PM PDT 24
Peak memory 203680 kb
Host smart-5ff4d8b9-9a0e-465a-bfc8-36e175aa96f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826286222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.1826286222
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.4131900500
Short name T673
Test name
Test status
Simulation time 99664526 ps
CPU time 1.74 seconds
Started Mar 31 03:45:21 PM PDT 24
Finished Mar 31 03:45:23 PM PDT 24
Peak memory 212008 kb
Host smart-1d3bf2fb-9a66-4c41-8153-4774d60bfd68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131900500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.4131900500
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.1698955276
Short name T703
Test name
Test status
Simulation time 375469501 ps
CPU time 8.21 seconds
Started Mar 31 03:45:25 PM PDT 24
Finished Mar 31 03:45:34 PM PDT 24
Peak memory 283652 kb
Host smart-c726ec58-9a0c-4654-8310-eac52e56eb3f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698955276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_emp
ty.1698955276
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.832379019
Short name T488
Test name
Test status
Simulation time 7381659159 ps
CPU time 119.27 seconds
Started Mar 31 03:45:21 PM PDT 24
Finished Mar 31 03:47:21 PM PDT 24
Peak memory 606784 kb
Host smart-4d80a6a2-af53-46e9-bb48-e2fb92e4ed04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832379019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.832379019
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.2609807235
Short name T951
Test name
Test status
Simulation time 5948678586 ps
CPU time 104.19 seconds
Started Mar 31 03:45:21 PM PDT 24
Finished Mar 31 03:47:06 PM PDT 24
Peak memory 559936 kb
Host smart-0781b93f-5241-467a-aa9b-ffa00202a66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609807235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.2609807235
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.1984288631
Short name T1070
Test name
Test status
Simulation time 119126451 ps
CPU time 0.94 seconds
Started Mar 31 03:45:23 PM PDT 24
Finished Mar 31 03:45:24 PM PDT 24
Peak memory 203672 kb
Host smart-1a4a7d83-0e55-4676-941c-d883353ad50e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984288631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.1984288631
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.1606890701
Short name T884
Test name
Test status
Simulation time 360110364 ps
CPU time 7.44 seconds
Started Mar 31 03:45:20 PM PDT 24
Finished Mar 31 03:45:28 PM PDT 24
Peak memory 203840 kb
Host smart-951fb36c-0d1a-4d2a-9a81-07fe22a50762
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606890701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx
.1606890701
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.2879927139
Short name T649
Test name
Test status
Simulation time 17890038847 ps
CPU time 110.25 seconds
Started Mar 31 03:45:25 PM PDT 24
Finished Mar 31 03:47:16 PM PDT 24
Peak memory 1246984 kb
Host smart-ac655683-5e51-48c6-a19e-30992b80c3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879927139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.2879927139
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.180051437
Short name T392
Test name
Test status
Simulation time 256498667 ps
CPU time 6.03 seconds
Started Mar 31 03:45:29 PM PDT 24
Finished Mar 31 03:45:35 PM PDT 24
Peak memory 203684 kb
Host smart-0ddbb89a-3a1f-4d3d-b21f-abb252c40eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180051437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.180051437
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.3433428108
Short name T1199
Test name
Test status
Simulation time 6645371188 ps
CPU time 28.3 seconds
Started Mar 31 03:45:26 PM PDT 24
Finished Mar 31 03:45:55 PM PDT 24
Peak memory 378044 kb
Host smart-12f74514-7df1-41b7-b249-c61ee2b330c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433428108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.3433428108
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_override.326424102
Short name T973
Test name
Test status
Simulation time 77376209 ps
CPU time 0.65 seconds
Started Mar 31 03:45:25 PM PDT 24
Finished Mar 31 03:45:26 PM PDT 24
Peak memory 203592 kb
Host smart-b0e9598b-52b5-4008-8044-360f045c8d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326424102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.326424102
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.1238773769
Short name T597
Test name
Test status
Simulation time 3078001365 ps
CPU time 81.63 seconds
Started Mar 31 03:45:22 PM PDT 24
Finished Mar 31 03:46:44 PM PDT 24
Peak memory 429760 kb
Host smart-5a76a6b8-bbc5-430f-9f65-6edc47ad49f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238773769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.1238773769
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.899821506
Short name T308
Test name
Test status
Simulation time 1522147637 ps
CPU time 2.37 seconds
Started Mar 31 03:45:31 PM PDT 24
Finished Mar 31 03:45:34 PM PDT 24
Peak memory 203792 kb
Host smart-b506312a-7e6f-4400-b8df-0c473409318e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899821506 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.899821506
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.1429675625
Short name T620
Test name
Test status
Simulation time 10092894690 ps
CPU time 110.29 seconds
Started Mar 31 03:45:27 PM PDT 24
Finished Mar 31 03:47:18 PM PDT 24
Peak memory 625148 kb
Host smart-05c6241a-4d82-4557-bee9-9b7226ec002c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429675625 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_fifo_reset_acq.1429675625
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.2443860307
Short name T905
Test name
Test status
Simulation time 10146120276 ps
CPU time 28.48 seconds
Started Mar 31 03:45:25 PM PDT 24
Finished Mar 31 03:45:53 PM PDT 24
Peak memory 408080 kb
Host smart-9688f18d-a24d-4f0e-bc5e-b23461f6c87f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443860307 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.2443860307
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.194084337
Short name T41
Test name
Test status
Simulation time 2797257986 ps
CPU time 2.34 seconds
Started Mar 31 03:45:25 PM PDT 24
Finished Mar 31 03:45:27 PM PDT 24
Peak memory 203924 kb
Host smart-457697ed-3076-4b63-9974-d1084b71f777
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194084337 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 19.i2c_target_hrst.194084337
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.2962596143
Short name T917
Test name
Test status
Simulation time 1068331798 ps
CPU time 4.27 seconds
Started Mar 31 03:45:24 PM PDT 24
Finished Mar 31 03:45:28 PM PDT 24
Peak memory 203836 kb
Host smart-06a69353-5cfb-4738-934e-39b856cf6440
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962596143 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_intr_smoke.2962596143
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.540516997
Short name T560
Test name
Test status
Simulation time 848250658 ps
CPU time 13.02 seconds
Started Mar 31 03:45:24 PM PDT 24
Finished Mar 31 03:45:37 PM PDT 24
Peak memory 203816 kb
Host smart-092df525-90d8-4469-aff6-0a89b30a8acc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540516997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_tar
get_smoke.540516997
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.4035979971
Short name T1020
Test name
Test status
Simulation time 1927631803 ps
CPU time 40.54 seconds
Started Mar 31 03:45:25 PM PDT 24
Finished Mar 31 03:46:06 PM PDT 24
Peak memory 203820 kb
Host smart-5d3b64b1-dfe2-42c2-8d27-e44700b7d476
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035979971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.4035979971
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.2764067019
Short name T360
Test name
Test status
Simulation time 8722612810 ps
CPU time 5.27 seconds
Started Mar 31 03:45:25 PM PDT 24
Finished Mar 31 03:45:30 PM PDT 24
Peak memory 203892 kb
Host smart-a7c289a5-5e7b-4ede-9db7-7cb109263514
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764067019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.2764067019
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.821143025
Short name T1060
Test name
Test status
Simulation time 4021575232 ps
CPU time 6.87 seconds
Started Mar 31 03:45:28 PM PDT 24
Finished Mar 31 03:45:35 PM PDT 24
Peak memory 203912 kb
Host smart-c2fd87f1-a502-4458-a2df-bdc62802b640
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821143025 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_timeout.821143025
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_alert_test.2824059979
Short name T355
Test name
Test status
Simulation time 22987263 ps
CPU time 0.58 seconds
Started Mar 31 03:43:56 PM PDT 24
Finished Mar 31 03:43:57 PM PDT 24
Peak memory 203656 kb
Host smart-34323530-0106-4fbf-b437-9e032d10a938
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824059979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.2824059979
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.1191259253
Short name T416
Test name
Test status
Simulation time 103411817 ps
CPU time 1.65 seconds
Started Mar 31 03:43:59 PM PDT 24
Finished Mar 31 03:44:01 PM PDT 24
Peak memory 211968 kb
Host smart-855325a1-51a6-419f-8761-c017491427dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191259253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.1191259253
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.1747416547
Short name T1100
Test name
Test status
Simulation time 832831119 ps
CPU time 7.16 seconds
Started Mar 31 03:43:51 PM PDT 24
Finished Mar 31 03:43:58 PM PDT 24
Peak memory 278512 kb
Host smart-5dacedc7-f8bc-40ff-afa4-d8008133899d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747416547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.1747416547
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.2806028406
Short name T935
Test name
Test status
Simulation time 7651926237 ps
CPU time 53.18 seconds
Started Mar 31 03:44:03 PM PDT 24
Finished Mar 31 03:44:56 PM PDT 24
Peak memory 520048 kb
Host smart-c40ded85-83d4-4468-ac81-5f5201609750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806028406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.2806028406
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.3049510789
Short name T410
Test name
Test status
Simulation time 5410810998 ps
CPU time 32.95 seconds
Started Mar 31 03:43:56 PM PDT 24
Finished Mar 31 03:44:29 PM PDT 24
Peak memory 457524 kb
Host smart-28437008-d618-41bf-b1c4-52ccf1909e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049510789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.3049510789
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.2132750309
Short name T368
Test name
Test status
Simulation time 438466525 ps
CPU time 1.03 seconds
Started Mar 31 03:43:59 PM PDT 24
Finished Mar 31 03:44:00 PM PDT 24
Peak memory 203808 kb
Host smart-5f82ca82-459e-4f8a-8abf-3d0da15eb72e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132750309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fm
t.2132750309
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.261370249
Short name T890
Test name
Test status
Simulation time 1273032288 ps
CPU time 4.33 seconds
Started Mar 31 03:43:54 PM PDT 24
Finished Mar 31 03:43:59 PM PDT 24
Peak memory 236664 kb
Host smart-a1847f7f-b1ca-4309-90e9-255e0782068e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261370249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.261370249
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.2975424028
Short name T164
Test name
Test status
Simulation time 5084683738 ps
CPU time 57.06 seconds
Started Mar 31 03:43:57 PM PDT 24
Finished Mar 31 03:44:54 PM PDT 24
Peak memory 824252 kb
Host smart-6b568ce7-d2a4-420d-9fb0-57a75ed9fd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975424028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.2975424028
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.2739725796
Short name T1016
Test name
Test status
Simulation time 2722523985 ps
CPU time 8.04 seconds
Started Mar 31 03:44:03 PM PDT 24
Finished Mar 31 03:44:11 PM PDT 24
Peak memory 203844 kb
Host smart-e0ac7d8f-ad0d-421d-b704-917660e751d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739725796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.2739725796
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.1704679109
Short name T916
Test name
Test status
Simulation time 6864493816 ps
CPU time 86.02 seconds
Started Mar 31 03:43:52 PM PDT 24
Finished Mar 31 03:45:18 PM PDT 24
Peak memory 415728 kb
Host smart-a4c6da55-5b29-4d52-a0f6-e8af6d567ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704679109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.1704679109
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_override.2934811025
Short name T868
Test name
Test status
Simulation time 88468932 ps
CPU time 0.68 seconds
Started Mar 31 03:43:50 PM PDT 24
Finished Mar 31 03:43:50 PM PDT 24
Peak memory 203612 kb
Host smart-80dda741-1f9c-42b5-bf9b-9b9fe7acfae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934811025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.2934811025
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.3608672207
Short name T736
Test name
Test status
Simulation time 28228478389 ps
CPU time 1160.94 seconds
Started Mar 31 03:43:51 PM PDT 24
Finished Mar 31 04:03:12 PM PDT 24
Peak memory 246856 kb
Host smart-1cfdc053-c567-47d5-80d6-1d616a0ea750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608672207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.3608672207
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.4055115554
Short name T509
Test name
Test status
Simulation time 19597141087 ps
CPU time 31.93 seconds
Started Mar 31 03:43:51 PM PDT 24
Finished Mar 31 03:44:23 PM PDT 24
Peak memory 415948 kb
Host smart-51f35b38-f686-4ba3-8301-2d9579af0b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055115554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.4055115554
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.2054018716
Short name T110
Test name
Test status
Simulation time 64985733 ps
CPU time 0.9 seconds
Started Mar 31 03:43:57 PM PDT 24
Finished Mar 31 03:43:58 PM PDT 24
Peak memory 222364 kb
Host smart-33349946-d60b-42cd-8ac7-3d50dda9f480
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054018716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.2054018716
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.2510697938
Short name T792
Test name
Test status
Simulation time 1269262914 ps
CPU time 5.73 seconds
Started Mar 31 03:44:03 PM PDT 24
Finished Mar 31 03:44:08 PM PDT 24
Peak memory 203812 kb
Host smart-683421bc-639d-4cae-9b87-dfd570178422
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510697938 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.2510697938
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.1584269547
Short name T1120
Test name
Test status
Simulation time 10048741242 ps
CPU time 83.19 seconds
Started Mar 31 03:43:56 PM PDT 24
Finished Mar 31 03:45:19 PM PDT 24
Peak memory 602460 kb
Host smart-1b1e184e-7c05-41b3-bac1-f837cb5f1e5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584269547 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_fifo_reset_acq.1584269547
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.2121490451
Short name T903
Test name
Test status
Simulation time 10127168319 ps
CPU time 93.55 seconds
Started Mar 31 03:44:03 PM PDT 24
Finished Mar 31 03:45:36 PM PDT 24
Peak memory 741320 kb
Host smart-09d1c989-78db-4bf2-9ef1-6b41df43d69d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121490451 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.2121490451
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.3986140876
Short name T1191
Test name
Test status
Simulation time 697067884 ps
CPU time 2.36 seconds
Started Mar 31 03:44:03 PM PDT 24
Finished Mar 31 03:44:05 PM PDT 24
Peak memory 203760 kb
Host smart-4b0c289a-27da-4629-8d4e-4bc7f12f70e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986140876 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_hrst.3986140876
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.2907969013
Short name T712
Test name
Test status
Simulation time 1783256152 ps
CPU time 4.76 seconds
Started Mar 31 03:43:53 PM PDT 24
Finished Mar 31 03:43:58 PM PDT 24
Peak memory 203840 kb
Host smart-38f7fd0b-d18b-4f7d-afa0-bb12874d34af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907969013 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.2907969013
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.3052373335
Short name T1081
Test name
Test status
Simulation time 4736125755 ps
CPU time 6.95 seconds
Started Mar 31 03:43:51 PM PDT 24
Finished Mar 31 03:43:58 PM PDT 24
Peak memory 203852 kb
Host smart-b8847219-1610-42e0-a1bd-0542fb97bf08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052373335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_smoke.3052373335
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.1892949875
Short name T656
Test name
Test status
Simulation time 997536753 ps
CPU time 15.7 seconds
Started Mar 31 03:43:54 PM PDT 24
Finished Mar 31 03:44:09 PM PDT 24
Peak memory 217732 kb
Host smart-30c210d2-860b-4f7f-9423-efd4899ee198
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892949875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.1892949875
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.3743393203
Short name T965
Test name
Test status
Simulation time 8610935408 ps
CPU time 297.01 seconds
Started Mar 31 03:43:52 PM PDT 24
Finished Mar 31 03:48:50 PM PDT 24
Peak memory 2274836 kb
Host smart-60946aca-3a84-4098-8627-35dd6957726d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743393203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_t
arget_stretch.3743393203
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_alert_test.342844786
Short name T731
Test name
Test status
Simulation time 48440500 ps
CPU time 0.63 seconds
Started Mar 31 03:45:30 PM PDT 24
Finished Mar 31 03:45:31 PM PDT 24
Peak memory 203680 kb
Host smart-2fa49e2c-a342-4ab0-b807-258d44b5e5bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342844786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.342844786
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.2966609982
Short name T757
Test name
Test status
Simulation time 460101942 ps
CPU time 1.42 seconds
Started Mar 31 03:45:26 PM PDT 24
Finished Mar 31 03:45:27 PM PDT 24
Peak memory 211984 kb
Host smart-37d87449-df70-46bd-a49a-97cfa71944c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966609982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.2966609982
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.257215587
Short name T728
Test name
Test status
Simulation time 374058243 ps
CPU time 10.86 seconds
Started Mar 31 03:45:25 PM PDT 24
Finished Mar 31 03:45:35 PM PDT 24
Peak memory 244316 kb
Host smart-1f4937a8-bb4c-4cca-9e0b-33e27a95e724
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257215587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_empt
y.257215587
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.2255150236
Short name T940
Test name
Test status
Simulation time 1403649378 ps
CPU time 89.68 seconds
Started Mar 31 03:45:27 PM PDT 24
Finished Mar 31 03:46:57 PM PDT 24
Peak memory 532536 kb
Host smart-5b09bcc3-56be-4cb0-9540-f15ff2f4fac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255150236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.2255150236
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.1794669123
Short name T1002
Test name
Test status
Simulation time 2810466543 ps
CPU time 34.78 seconds
Started Mar 31 03:45:25 PM PDT 24
Finished Mar 31 03:46:00 PM PDT 24
Peak memory 479776 kb
Host smart-6be92ffe-a03a-4645-901b-e42e5ef45fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794669123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.1794669123
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.464942312
Short name T554
Test name
Test status
Simulation time 842507990 ps
CPU time 1.01 seconds
Started Mar 31 03:45:27 PM PDT 24
Finished Mar 31 03:45:28 PM PDT 24
Peak memory 203696 kb
Host smart-29f31d65-31da-4a9b-97c5-8a55d2858467
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464942312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_fm
t.464942312
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.2685535823
Short name T564
Test name
Test status
Simulation time 712947309 ps
CPU time 3.72 seconds
Started Mar 31 03:45:32 PM PDT 24
Finished Mar 31 03:45:36 PM PDT 24
Peak memory 203776 kb
Host smart-c84ef093-2fd6-4479-88fd-dfb5bb12db90
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685535823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.2685535823
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.1242345609
Short name T35
Test name
Test status
Simulation time 8585394684 ps
CPU time 112.26 seconds
Started Mar 31 03:45:32 PM PDT 24
Finished Mar 31 03:47:24 PM PDT 24
Peak memory 1227948 kb
Host smart-9d8d8444-7979-44c1-9c4d-84001fae397d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242345609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.1242345609
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.258387760
Short name T671
Test name
Test status
Simulation time 300167435 ps
CPU time 4.86 seconds
Started Mar 31 03:45:32 PM PDT 24
Finished Mar 31 03:45:37 PM PDT 24
Peak memory 203804 kb
Host smart-a1c116b7-0a35-4779-ad2a-9f05fd1bbcbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258387760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.258387760
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.3960554645
Short name T883
Test name
Test status
Simulation time 1304990875 ps
CPU time 63.1 seconds
Started Mar 31 03:45:30 PM PDT 24
Finished Mar 31 03:46:33 PM PDT 24
Peak memory 310356 kb
Host smart-7c2e2ccf-c9c2-43f3-80b1-8fda931203c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960554645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.3960554645
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.459349471
Short name T764
Test name
Test status
Simulation time 78954063 ps
CPU time 0.61 seconds
Started Mar 31 03:45:32 PM PDT 24
Finished Mar 31 03:45:33 PM PDT 24
Peak memory 203588 kb
Host smart-2b786fef-94b9-45b8-a756-bc02589ada38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459349471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.459349471
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.405467636
Short name T26
Test name
Test status
Simulation time 6733478917 ps
CPU time 97.94 seconds
Started Mar 31 03:45:27 PM PDT 24
Finished Mar 31 03:47:05 PM PDT 24
Peak memory 576188 kb
Host smart-4d8f31ba-3958-4af7-9b14-ade00abb3e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405467636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.405467636
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.2086925536
Short name T776
Test name
Test status
Simulation time 6154539525 ps
CPU time 38.13 seconds
Started Mar 31 03:45:30 PM PDT 24
Finished Mar 31 03:46:09 PM PDT 24
Peak memory 427008 kb
Host smart-8e33932e-334d-4af9-82d7-a1d31faeaf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086925536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.2086925536
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.2071635008
Short name T1111
Test name
Test status
Simulation time 3320438414 ps
CPU time 3.82 seconds
Started Mar 31 03:45:32 PM PDT 24
Finished Mar 31 03:45:36 PM PDT 24
Peak memory 203908 kb
Host smart-b2bf6d76-1338-4070-9202-789d9a194803
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071635008 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.2071635008
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.3370948309
Short name T874
Test name
Test status
Simulation time 10388343435 ps
CPU time 15.11 seconds
Started Mar 31 03:45:30 PM PDT 24
Finished Mar 31 03:45:45 PM PDT 24
Peak memory 306944 kb
Host smart-87e1401b-7a9a-42e9-a682-4f7db1f796a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370948309 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_tx.3370948309
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.898880354
Short name T909
Test name
Test status
Simulation time 353503839 ps
CPU time 2.26 seconds
Started Mar 31 03:45:35 PM PDT 24
Finished Mar 31 03:45:37 PM PDT 24
Peak memory 203764 kb
Host smart-1c9a980f-90b6-4e3e-b609-157c74fe6842
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898880354 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 20.i2c_target_hrst.898880354
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.647283750
Short name T117
Test name
Test status
Simulation time 3864185241 ps
CPU time 5.24 seconds
Started Mar 31 03:45:31 PM PDT 24
Finished Mar 31 03:45:37 PM PDT 24
Peak memory 207396 kb
Host smart-23dba3fe-dc9e-4840-b385-e0a9540b0306
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647283750 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_intr_smoke.647283750
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.674114436
Short name T984
Test name
Test status
Simulation time 966472891 ps
CPU time 8.93 seconds
Started Mar 31 03:45:30 PM PDT 24
Finished Mar 31 03:45:39 PM PDT 24
Peak memory 203812 kb
Host smart-a8cb3470-f7f2-4c03-a0a5-4a01921fe82e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674114436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_tar
get_smoke.674114436
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.3870543903
Short name T1170
Test name
Test status
Simulation time 13685390490 ps
CPU time 20.83 seconds
Started Mar 31 03:45:27 PM PDT 24
Finished Mar 31 03:45:48 PM PDT 24
Peak memory 229588 kb
Host smart-ddce2a00-f956-4946-89d7-16a09a770006
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870543903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.3870543903
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.2049891804
Short name T79
Test name
Test status
Simulation time 12869931872 ps
CPU time 8.69 seconds
Started Mar 31 03:45:26 PM PDT 24
Finished Mar 31 03:45:35 PM PDT 24
Peak memory 203760 kb
Host smart-1c7d66b8-6d20-4e03-88da-5b3a885df18c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049891804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_wr.2049891804
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.3733883334
Short name T584
Test name
Test status
Simulation time 37464656797 ps
CPU time 2174.86 seconds
Started Mar 31 03:45:25 PM PDT 24
Finished Mar 31 04:21:41 PM PDT 24
Peak memory 7124792 kb
Host smart-151b4e67-cf8e-487e-984b-4d6abb829406
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733883334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stretch.3733883334
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.3873260303
Short name T678
Test name
Test status
Simulation time 4459194032 ps
CPU time 6.02 seconds
Started Mar 31 03:45:31 PM PDT 24
Finished Mar 31 03:45:37 PM PDT 24
Peak memory 214948 kb
Host smart-97a2ec1b-323f-4b41-a50a-1bc163c3441f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873260303 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_timeout.3873260303
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_unexp_stop.1924290604
Short name T995
Test name
Test status
Simulation time 1125251297 ps
CPU time 5.67 seconds
Started Mar 31 03:45:34 PM PDT 24
Finished Mar 31 03:45:40 PM PDT 24
Peak memory 203812 kb
Host smart-c63c507d-971e-4d80-9ad1-11945892d051
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924290604 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 20.i2c_target_unexp_stop.1924290604
Directory /workspace/20.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/21.i2c_alert_test.1721345963
Short name T939
Test name
Test status
Simulation time 149154714 ps
CPU time 0.62 seconds
Started Mar 31 03:45:39 PM PDT 24
Finished Mar 31 03:45:40 PM PDT 24
Peak memory 203708 kb
Host smart-267a4873-eefa-46fe-ace8-1dd51d2ef656
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721345963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.1721345963
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.2078625507
Short name T44
Test name
Test status
Simulation time 1236572916 ps
CPU time 1.5 seconds
Started Mar 31 03:45:33 PM PDT 24
Finished Mar 31 03:45:35 PM PDT 24
Peak memory 212060 kb
Host smart-6b717915-a2f2-492b-ac7b-001fdc327b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078625507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.2078625507
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.2500854260
Short name T1056
Test name
Test status
Simulation time 505027184 ps
CPU time 13.62 seconds
Started Mar 31 03:45:31 PM PDT 24
Finished Mar 31 03:45:45 PM PDT 24
Peak memory 256792 kb
Host smart-7115a3ff-2155-4572-a916-285dc0f35b0e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500854260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.2500854260
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.1316501856
Short name T226
Test name
Test status
Simulation time 7245944505 ps
CPU time 57.22 seconds
Started Mar 31 03:45:32 PM PDT 24
Finished Mar 31 03:46:29 PM PDT 24
Peak memory 654020 kb
Host smart-d9e203ae-484a-44c1-a25c-00558922c1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316501856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.1316501856
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.385513571
Short name T383
Test name
Test status
Simulation time 5901184027 ps
CPU time 47.68 seconds
Started Mar 31 03:45:34 PM PDT 24
Finished Mar 31 03:46:22 PM PDT 24
Peak memory 521148 kb
Host smart-30d94212-04f1-451d-a318-e6133d6468f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385513571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.385513571
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.1250850370
Short name T1053
Test name
Test status
Simulation time 406605189 ps
CPU time 0.89 seconds
Started Mar 31 03:45:31 PM PDT 24
Finished Mar 31 03:45:32 PM PDT 24
Peak memory 203692 kb
Host smart-874a901a-81cc-4016-8fc1-2ba4bc2bc244
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250850370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.1250850370
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.2182934956
Short name T641
Test name
Test status
Simulation time 680308149 ps
CPU time 9.33 seconds
Started Mar 31 03:45:35 PM PDT 24
Finished Mar 31 03:45:44 PM PDT 24
Peak memory 233884 kb
Host smart-eb8bbb71-b2c1-4da7-8981-0174264ec6ca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182934956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx
.2182934956
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.2869874882
Short name T630
Test name
Test status
Simulation time 14140893809 ps
CPU time 262.11 seconds
Started Mar 31 03:45:33 PM PDT 24
Finished Mar 31 03:49:55 PM PDT 24
Peak memory 1043744 kb
Host smart-5d10f63b-4977-485d-986b-c2507bd2c248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869874882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.2869874882
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.2337215299
Short name T1183
Test name
Test status
Simulation time 230552835 ps
CPU time 3.3 seconds
Started Mar 31 03:45:39 PM PDT 24
Finished Mar 31 03:45:42 PM PDT 24
Peak memory 203808 kb
Host smart-df0fab05-c878-4315-9f46-f83850ca881e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337215299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.2337215299
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.3595184655
Short name T348
Test name
Test status
Simulation time 1763006198 ps
CPU time 32.07 seconds
Started Mar 31 03:45:41 PM PDT 24
Finished Mar 31 03:46:14 PM PDT 24
Peak memory 388192 kb
Host smart-e14b06bb-5966-45e3-8381-b30123d237b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595184655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.3595184655
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_override.1379890050
Short name T340
Test name
Test status
Simulation time 88012862 ps
CPU time 0.78 seconds
Started Mar 31 03:45:34 PM PDT 24
Finished Mar 31 03:45:35 PM PDT 24
Peak memory 203588 kb
Host smart-4d6468cd-5309-4f25-af6b-9e2119e9ca64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379890050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.1379890050
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.613216937
Short name T769
Test name
Test status
Simulation time 13408761112 ps
CPU time 263.69 seconds
Started Mar 31 03:45:34 PM PDT 24
Finished Mar 31 03:49:58 PM PDT 24
Peak memory 731928 kb
Host smart-87ad3d31-7c7b-42f2-bcd3-7470b796b260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613216937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.613216937
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.435271020
Short name T271
Test name
Test status
Simulation time 2843853003 ps
CPU time 77.37 seconds
Started Mar 31 03:45:30 PM PDT 24
Finished Mar 31 03:46:47 PM PDT 24
Peak memory 333652 kb
Host smart-9ff0f141-8793-4c14-b71b-8ef3ab0d0e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435271020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.435271020
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.2285252316
Short name T636
Test name
Test status
Simulation time 696835196 ps
CPU time 3.33 seconds
Started Mar 31 03:45:39 PM PDT 24
Finished Mar 31 03:45:42 PM PDT 24
Peak memory 203788 kb
Host smart-5948a9d8-49f0-4ebe-b87b-ac9cea49b139
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285252316 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.2285252316
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.688766812
Short name T798
Test name
Test status
Simulation time 10085436646 ps
CPU time 27.85 seconds
Started Mar 31 03:45:37 PM PDT 24
Finished Mar 31 03:46:05 PM PDT 24
Peak memory 401364 kb
Host smart-85dcd948-c0e8-457b-946c-704ce9f7986f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688766812 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_acq.688766812
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.3665015947
Short name T180
Test name
Test status
Simulation time 10172651849 ps
CPU time 13.58 seconds
Started Mar 31 03:45:37 PM PDT 24
Finished Mar 31 03:45:51 PM PDT 24
Peak memory 307400 kb
Host smart-73335d35-03b2-4a46-9bf5-b1d38c06a2b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665015947 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.3665015947
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.3156852313
Short name T248
Test name
Test status
Simulation time 419213972 ps
CPU time 2.19 seconds
Started Mar 31 03:45:38 PM PDT 24
Finished Mar 31 03:45:40 PM PDT 24
Peak memory 203796 kb
Host smart-1cd197ef-b4a4-409b-9de9-2f77b45d12c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156852313 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_hrst.3156852313
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.2826710033
Short name T1115
Test name
Test status
Simulation time 2811523714 ps
CPU time 7.7 seconds
Started Mar 31 03:45:37 PM PDT 24
Finished Mar 31 03:45:45 PM PDT 24
Peak memory 203796 kb
Host smart-d3503993-e400-4d4e-ba03-3b95d335b457
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826710033 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.2826710033
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.1474591166
Short name T354
Test name
Test status
Simulation time 691435293 ps
CPU time 11.09 seconds
Started Mar 31 03:45:31 PM PDT 24
Finished Mar 31 03:45:43 PM PDT 24
Peak memory 203796 kb
Host smart-0753fa8b-ab95-4fde-9fdd-c21465d60f84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474591166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_ta
rget_smoke.1474591166
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.2017737058
Short name T734
Test name
Test status
Simulation time 3696254052 ps
CPU time 13.23 seconds
Started Mar 31 03:45:38 PM PDT 24
Finished Mar 31 03:45:52 PM PDT 24
Peak memory 203864 kb
Host smart-560276a3-0184-4324-bc08-70d7135c9908
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017737058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_rd.2017737058
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.2086603357
Short name T405
Test name
Test status
Simulation time 8363436640 ps
CPU time 240.65 seconds
Started Mar 31 03:45:41 PM PDT 24
Finished Mar 31 03:49:41 PM PDT 24
Peak memory 2121608 kb
Host smart-aece85a5-2bc8-4580-b8d3-80f36cb560e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086603357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stretch.2086603357
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.2431126450
Short name T1038
Test name
Test status
Simulation time 1284882866 ps
CPU time 6.49 seconds
Started Mar 31 03:45:39 PM PDT 24
Finished Mar 31 03:45:46 PM PDT 24
Peak memory 220060 kb
Host smart-f2932c1d-b815-477a-ab73-d9647f722379
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431126450 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.2431126450
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_unexp_stop.4160595925
Short name T717
Test name
Test status
Simulation time 1846263767 ps
CPU time 6.37 seconds
Started Mar 31 03:45:39 PM PDT 24
Finished Mar 31 03:45:46 PM PDT 24
Peak memory 203820 kb
Host smart-b8cccf96-c122-4baf-85d1-d9c4654b131d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160595925 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 21.i2c_target_unexp_stop.4160595925
Directory /workspace/21.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/22.i2c_alert_test.2481543957
Short name T282
Test name
Test status
Simulation time 15951764 ps
CPU time 0.6 seconds
Started Mar 31 03:45:43 PM PDT 24
Finished Mar 31 03:45:44 PM PDT 24
Peak memory 203664 kb
Host smart-092f0ee4-3d0b-4bb3-83b8-87d2ddf93f56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481543957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.2481543957
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.4188638847
Short name T1143
Test name
Test status
Simulation time 71207585 ps
CPU time 1.52 seconds
Started Mar 31 03:45:47 PM PDT 24
Finished Mar 31 03:45:49 PM PDT 24
Peak memory 212008 kb
Host smart-02fee85e-ca55-4dbe-8390-104f4668c486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188638847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.4188638847
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.304708164
Short name T532
Test name
Test status
Simulation time 924928968 ps
CPU time 11.93 seconds
Started Mar 31 03:45:44 PM PDT 24
Finished Mar 31 03:45:56 PM PDT 24
Peak memory 236224 kb
Host smart-5e7a338b-1b00-4a9a-8e64-c1b310752668
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304708164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_empt
y.304708164
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.616336055
Short name T709
Test name
Test status
Simulation time 8382730512 ps
CPU time 63.29 seconds
Started Mar 31 03:45:44 PM PDT 24
Finished Mar 31 03:46:48 PM PDT 24
Peak memory 644188 kb
Host smart-06c92ae7-ecc2-4a43-812c-d9372d183ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616336055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.616336055
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.2842740426
Short name T351
Test name
Test status
Simulation time 19489267980 ps
CPU time 61.94 seconds
Started Mar 31 03:45:47 PM PDT 24
Finished Mar 31 03:46:49 PM PDT 24
Peak memory 613124 kb
Host smart-de918d81-7fef-460c-b74e-e49d6867b7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842740426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.2842740426
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.3397781102
Short name T36
Test name
Test status
Simulation time 2110191260 ps
CPU time 1 seconds
Started Mar 31 03:45:47 PM PDT 24
Finished Mar 31 03:45:48 PM PDT 24
Peak memory 203844 kb
Host smart-874b8991-53ec-4350-9721-15c72048e6e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397781102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.3397781102
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.1824955323
Short name T1158
Test name
Test status
Simulation time 512287017 ps
CPU time 2.94 seconds
Started Mar 31 03:45:44 PM PDT 24
Finished Mar 31 03:45:47 PM PDT 24
Peak memory 203840 kb
Host smart-b98c552f-0dc9-4e7b-bcb9-7bdabbe35036
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824955323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.1824955323
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.3787427916
Short name T962
Test name
Test status
Simulation time 8828868905 ps
CPU time 61.94 seconds
Started Mar 31 03:45:44 PM PDT 24
Finished Mar 31 03:46:46 PM PDT 24
Peak memory 751436 kb
Host smart-8c78e4e6-757c-4f6e-bca5-13136d40fce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787427916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.3787427916
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.2618068608
Short name T539
Test name
Test status
Simulation time 1440963976 ps
CPU time 14.57 seconds
Started Mar 31 03:45:46 PM PDT 24
Finished Mar 31 03:46:01 PM PDT 24
Peak memory 203792 kb
Host smart-5edf11e8-eea5-44d6-a149-2f23392bdb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618068608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.2618068608
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.1586140040
Short name T821
Test name
Test status
Simulation time 1599535664 ps
CPU time 23.99 seconds
Started Mar 31 03:45:44 PM PDT 24
Finished Mar 31 03:46:08 PM PDT 24
Peak memory 319636 kb
Host smart-33031990-8ae4-4485-88ab-9a31fe78d3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586140040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.1586140040
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_host_override.3355869024
Short name T186
Test name
Test status
Simulation time 92715244 ps
CPU time 0.65 seconds
Started Mar 31 03:45:37 PM PDT 24
Finished Mar 31 03:45:37 PM PDT 24
Peak memory 203512 kb
Host smart-a455a4a8-183f-4bcd-bd47-14f196a9b887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355869024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.3355869024
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.2887475162
Short name T788
Test name
Test status
Simulation time 3355186546 ps
CPU time 43.23 seconds
Started Mar 31 03:45:44 PM PDT 24
Finished Mar 31 03:46:28 PM PDT 24
Peak memory 580904 kb
Host smart-b5de22da-8f32-4839-88a4-3c90ebe3d351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887475162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.2887475162
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.3506357774
Short name T376
Test name
Test status
Simulation time 5150070377 ps
CPU time 68.04 seconds
Started Mar 31 03:45:39 PM PDT 24
Finished Mar 31 03:46:47 PM PDT 24
Peak memory 350012 kb
Host smart-7d8f69e0-26d4-4b66-aa4d-d9d01bcadcae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506357774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.3506357774
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.787766649
Short name T461
Test name
Test status
Simulation time 611316978 ps
CPU time 3.21 seconds
Started Mar 31 03:45:44 PM PDT 24
Finished Mar 31 03:45:47 PM PDT 24
Peak memory 203804 kb
Host smart-33f55874-1059-4f34-9cb9-cb3e6227274d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787766649 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.787766649
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.834778887
Short name T378
Test name
Test status
Simulation time 10214249302 ps
CPU time 89.24 seconds
Started Mar 31 03:45:45 PM PDT 24
Finished Mar 31 03:47:14 PM PDT 24
Peak memory 679012 kb
Host smart-5d0a86ba-423a-4bc2-9ee0-22685d5290ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834778887 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_acq.834778887
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.1549568205
Short name T1077
Test name
Test status
Simulation time 10963895862 ps
CPU time 6.92 seconds
Started Mar 31 03:45:45 PM PDT 24
Finished Mar 31 03:45:53 PM PDT 24
Peak memory 254080 kb
Host smart-806206d4-d279-4631-ba77-ed834092ad1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549568205 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.1549568205
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.1659716931
Short name T676
Test name
Test status
Simulation time 2026270837 ps
CPU time 2.86 seconds
Started Mar 31 03:45:43 PM PDT 24
Finished Mar 31 03:45:46 PM PDT 24
Peak memory 203816 kb
Host smart-b1f9fdc6-a468-4ae1-a1aa-75c84a7cd2f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659716931 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_hrst.1659716931
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.2241236374
Short name T982
Test name
Test status
Simulation time 3141835755 ps
CPU time 4.63 seconds
Started Mar 31 03:45:44 PM PDT 24
Finished Mar 31 03:45:48 PM PDT 24
Peak memory 206540 kb
Host smart-0c88dc7f-acc0-44f1-aba8-c193656db144
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241236374 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.2241236374
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.652086640
Short name T364
Test name
Test status
Simulation time 3200880443 ps
CPU time 9.55 seconds
Started Mar 31 03:45:46 PM PDT 24
Finished Mar 31 03:45:56 PM PDT 24
Peak memory 203900 kb
Host smart-f86d264e-fac5-4e49-8bd7-15b87f3953e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652086640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_tar
get_smoke.652086640
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.4203522656
Short name T1034
Test name
Test status
Simulation time 385122182 ps
CPU time 5.51 seconds
Started Mar 31 03:45:43 PM PDT 24
Finished Mar 31 03:45:49 PM PDT 24
Peak memory 203864 kb
Host smart-eca570b6-d008-409f-a529-238d24d6f44a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203522656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_rd.4203522656
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.3797697048
Short name T767
Test name
Test status
Simulation time 8691600709 ps
CPU time 5.81 seconds
Started Mar 31 03:45:46 PM PDT 24
Finished Mar 31 03:45:52 PM PDT 24
Peak memory 203904 kb
Host smart-6d23d2f5-982a-49f7-9555-7e1db6d88f8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797697048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_wr.3797697048
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.1468788871
Short name T455
Test name
Test status
Simulation time 31078921854 ps
CPU time 80.53 seconds
Started Mar 31 03:45:47 PM PDT 24
Finished Mar 31 03:47:08 PM PDT 24
Peak memory 915208 kb
Host smart-9318ad27-a33f-4cc7-a1aa-c3ac50a0cec5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468788871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stretch.1468788871
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.3960810933
Short name T861
Test name
Test status
Simulation time 1453104586 ps
CPU time 7.2 seconds
Started Mar 31 03:45:44 PM PDT 24
Finished Mar 31 03:45:51 PM PDT 24
Peak memory 212064 kb
Host smart-6e044899-52e6-40f2-8922-98a3ea015852
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960810933 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_timeout.3960810933
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_alert_test.1861941885
Short name T466
Test name
Test status
Simulation time 46867443 ps
CPU time 0.61 seconds
Started Mar 31 03:45:49 PM PDT 24
Finished Mar 31 03:45:50 PM PDT 24
Peak memory 203636 kb
Host smart-8400f16c-e494-4bc4-aabb-c66d126fe405
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861941885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.1861941885
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.146706985
Short name T414
Test name
Test status
Simulation time 197501632 ps
CPU time 1.6 seconds
Started Mar 31 03:45:50 PM PDT 24
Finished Mar 31 03:45:52 PM PDT 24
Peak memory 212000 kb
Host smart-ae1d1113-a3d8-4e6d-9fd6-0720aee26fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146706985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.146706985
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.2000051361
Short name T723
Test name
Test status
Simulation time 229305495 ps
CPU time 12.09 seconds
Started Mar 31 03:45:48 PM PDT 24
Finished Mar 31 03:46:00 PM PDT 24
Peak memory 248044 kb
Host smart-17070639-15b5-43fa-abd0-10fd088675ab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000051361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_emp
ty.2000051361
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.1886560068
Short name T781
Test name
Test status
Simulation time 18493876932 ps
CPU time 157.26 seconds
Started Mar 31 03:45:49 PM PDT 24
Finished Mar 31 03:48:27 PM PDT 24
Peak memory 709460 kb
Host smart-8b269aba-6dc9-42e0-aa44-1aa7da246b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886560068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.1886560068
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.1034067044
Short name T1073
Test name
Test status
Simulation time 26641898587 ps
CPU time 161.72 seconds
Started Mar 31 03:45:57 PM PDT 24
Finished Mar 31 03:48:39 PM PDT 24
Peak memory 709464 kb
Host smart-cf9de925-4d16-49ab-88d3-ea20b0625380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034067044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.1034067044
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.3347603479
Short name T400
Test name
Test status
Simulation time 183934408 ps
CPU time 0.85 seconds
Started Mar 31 03:45:54 PM PDT 24
Finished Mar 31 03:45:55 PM PDT 24
Peak memory 203676 kb
Host smart-a6fe3bca-91b6-4b88-b55c-04bce5a3cad2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347603479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.3347603479
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.3706152071
Short name T567
Test name
Test status
Simulation time 1622325329 ps
CPU time 3 seconds
Started Mar 31 03:45:55 PM PDT 24
Finished Mar 31 03:45:58 PM PDT 24
Peak memory 203748 kb
Host smart-b68227da-9873-41d8-84e8-5f06bbbc03e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706152071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.3706152071
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.3337200940
Short name T531
Test name
Test status
Simulation time 6962981959 ps
CPU time 99.36 seconds
Started Mar 31 03:45:47 PM PDT 24
Finished Mar 31 03:47:26 PM PDT 24
Peak memory 1036392 kb
Host smart-bc7c776c-3d18-4082-a271-67930244eea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337200940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.3337200940
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.320150776
Short name T1156
Test name
Test status
Simulation time 358664650 ps
CPU time 5.43 seconds
Started Mar 31 03:45:51 PM PDT 24
Finished Mar 31 03:45:57 PM PDT 24
Peak memory 203772 kb
Host smart-51da05b9-c3a7-4e9a-9765-05fc6badd39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320150776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.320150776
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_mode_toggle.4119031320
Short name T699
Test name
Test status
Simulation time 1606779768 ps
CPU time 33.68 seconds
Started Mar 31 03:45:53 PM PDT 24
Finished Mar 31 03:46:27 PM PDT 24
Peak memory 413964 kb
Host smart-4aeb8281-5867-43af-a7c3-9b278a39290c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119031320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.4119031320
Directory /workspace/23.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/23.i2c_host_override.427061304
Short name T1036
Test name
Test status
Simulation time 37893820 ps
CPU time 0.63 seconds
Started Mar 31 03:45:49 PM PDT 24
Finished Mar 31 03:45:50 PM PDT 24
Peak memory 203588 kb
Host smart-4ee9ec72-589d-4811-bda1-ecf279830401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427061304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.427061304
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.3294869848
Short name T820
Test name
Test status
Simulation time 5326986811 ps
CPU time 195.18 seconds
Started Mar 31 03:45:52 PM PDT 24
Finished Mar 31 03:49:08 PM PDT 24
Peak memory 812212 kb
Host smart-23178b34-9f72-4573-8082-5268bfcbd9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294869848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.3294869848
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.1640673576
Short name T1172
Test name
Test status
Simulation time 5107103274 ps
CPU time 24.27 seconds
Started Mar 31 03:45:44 PM PDT 24
Finished Mar 31 03:46:08 PM PDT 24
Peak memory 359760 kb
Host smart-98b0c51f-9eba-4a13-92e8-10b9ad9da7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640673576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.1640673576
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.69546069
Short name T259
Test name
Test status
Simulation time 747052072 ps
CPU time 3.79 seconds
Started Mar 31 03:45:56 PM PDT 24
Finished Mar 31 03:46:00 PM PDT 24
Peak memory 203800 kb
Host smart-26cb830b-b468-4200-aecf-fa64d4713d47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69546069 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.i2c_target_bad_addr.69546069
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.4272716303
Short name T64
Test name
Test status
Simulation time 10122794004 ps
CPU time 31.13 seconds
Started Mar 31 03:45:54 PM PDT 24
Finished Mar 31 03:46:25 PM PDT 24
Peak memory 407268 kb
Host smart-4cd27b9d-6a2a-4a92-9845-9d7562c43257
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272716303 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_fifo_reset_acq.4272716303
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.1101247505
Short name T59
Test name
Test status
Simulation time 10049186578 ps
CPU time 99.98 seconds
Started Mar 31 03:45:54 PM PDT 24
Finished Mar 31 03:47:34 PM PDT 24
Peak memory 718324 kb
Host smart-99db993c-960e-4fce-904c-44b231626edb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101247505 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_tx.1101247505
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.3032974834
Short name T220
Test name
Test status
Simulation time 957543582 ps
CPU time 2.92 seconds
Started Mar 31 03:45:49 PM PDT 24
Finished Mar 31 03:45:52 PM PDT 24
Peak memory 203808 kb
Host smart-0c23d035-bf40-41b4-b1c9-9a31cb528140
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032974834 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_hrst.3032974834
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.1956797607
Short name T270
Test name
Test status
Simulation time 893624726 ps
CPU time 4.52 seconds
Started Mar 31 03:45:51 PM PDT 24
Finished Mar 31 03:45:56 PM PDT 24
Peak memory 212016 kb
Host smart-eacca93a-b895-437f-bf66-71b85b530b3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956797607 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_intr_smoke.1956797607
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.3236459443
Short name T427
Test name
Test status
Simulation time 819852142 ps
CPU time 10.61 seconds
Started Mar 31 03:45:50 PM PDT 24
Finished Mar 31 03:46:01 PM PDT 24
Peak memory 203756 kb
Host smart-d9fadb24-83b5-4663-ad09-6051dea7d15f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236459443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.3236459443
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.3214457737
Short name T827
Test name
Test status
Simulation time 4810820573 ps
CPU time 51.27 seconds
Started Mar 31 03:45:54 PM PDT 24
Finished Mar 31 03:46:46 PM PDT 24
Peak memory 206676 kb
Host smart-d5258876-fdba-4b73-bc29-94a183bb207c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214457737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.3214457737
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.3714797328
Short name T314
Test name
Test status
Simulation time 30347667965 ps
CPU time 205.28 seconds
Started Mar 31 03:45:47 PM PDT 24
Finished Mar 31 03:49:12 PM PDT 24
Peak memory 1744156 kb
Host smart-ae24a97b-41e2-4265-9cdb-bb8fd5799052
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714797328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stretch.3714797328
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.3464397755
Short name T16
Test name
Test status
Simulation time 1062952779 ps
CPU time 5.97 seconds
Started Mar 31 03:45:51 PM PDT 24
Finished Mar 31 03:45:57 PM PDT 24
Peak memory 203656 kb
Host smart-2fb9da5c-db67-4db0-8f84-5de68141b697
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464397755 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.3464397755
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_alert_test.3447422845
Short name T1152
Test name
Test status
Simulation time 21067832 ps
CPU time 0.61 seconds
Started Mar 31 03:45:58 PM PDT 24
Finished Mar 31 03:45:59 PM PDT 24
Peak memory 203704 kb
Host smart-fc17f2bd-9948-4e1f-ab4d-6d8316c7fadf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447422845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.3447422845
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.2811432793
Short name T1171
Test name
Test status
Simulation time 65714588 ps
CPU time 1.33 seconds
Started Mar 31 03:45:56 PM PDT 24
Finished Mar 31 03:45:58 PM PDT 24
Peak memory 212064 kb
Host smart-7ef4a9b6-056f-4c24-84d9-26ccde3ac592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811432793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.2811432793
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.542676734
Short name T1119
Test name
Test status
Simulation time 774125114 ps
CPU time 4.28 seconds
Started Mar 31 03:45:58 PM PDT 24
Finished Mar 31 03:46:03 PM PDT 24
Peak memory 233920 kb
Host smart-257474cd-7dfe-4def-aa1c-8ad361288bcb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542676734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_empt
y.542676734
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.1795425621
Short name T911
Test name
Test status
Simulation time 23857881662 ps
CPU time 52.04 seconds
Started Mar 31 03:45:58 PM PDT 24
Finished Mar 31 03:46:50 PM PDT 24
Peak memory 619584 kb
Host smart-93eebbb5-4a11-4807-81a9-2b9b19c2da2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795425621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.1795425621
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.2375507350
Short name T388
Test name
Test status
Simulation time 11857234796 ps
CPU time 85.67 seconds
Started Mar 31 03:45:54 PM PDT 24
Finished Mar 31 03:47:20 PM PDT 24
Peak memory 497636 kb
Host smart-a4aa4b77-8262-4c0f-aa60-9363892076f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375507350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.2375507350
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.2675623310
Short name T582
Test name
Test status
Simulation time 344594898 ps
CPU time 0.88 seconds
Started Mar 31 03:45:56 PM PDT 24
Finished Mar 31 03:45:57 PM PDT 24
Peak memory 203692 kb
Host smart-a4a12dd0-9720-4e02-9244-54368b442626
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675623310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.2675623310
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.2445522906
Short name T963
Test name
Test status
Simulation time 151753401 ps
CPU time 3.91 seconds
Started Mar 31 03:45:55 PM PDT 24
Finished Mar 31 03:45:59 PM PDT 24
Peak memory 229072 kb
Host smart-0468280c-2cab-45c6-a709-6b28658d978f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445522906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx
.2445522906
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.3034835333
Short name T113
Test name
Test status
Simulation time 3555102389 ps
CPU time 285.01 seconds
Started Mar 31 03:45:51 PM PDT 24
Finished Mar 31 03:50:37 PM PDT 24
Peak memory 1070048 kb
Host smart-dc34ba13-c1a3-4344-9882-ff2ea29fed53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034835333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.3034835333
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.3083736726
Short name T615
Test name
Test status
Simulation time 1397930124 ps
CPU time 14.61 seconds
Started Mar 31 03:46:01 PM PDT 24
Finished Mar 31 03:46:16 PM PDT 24
Peak memory 203840 kb
Host smart-35291739-d42c-4d47-b212-99c29389a83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083736726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.3083736726
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.1262939773
Short name T536
Test name
Test status
Simulation time 1104523529 ps
CPU time 26.33 seconds
Started Mar 31 03:45:59 PM PDT 24
Finished Mar 31 03:46:26 PM PDT 24
Peak memory 399832 kb
Host smart-2f024fcf-f54d-4b59-b77e-1b4f01fcc375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262939773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.1262939773
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.3039817388
Short name T722
Test name
Test status
Simulation time 27207828 ps
CPU time 0.67 seconds
Started Mar 31 03:45:57 PM PDT 24
Finished Mar 31 03:45:58 PM PDT 24
Peak memory 203568 kb
Host smart-e7347afe-fbac-43a9-a2b6-8285ac551759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039817388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.3039817388
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.2700439244
Short name T888
Test name
Test status
Simulation time 379731630 ps
CPU time 3.9 seconds
Started Mar 31 03:45:59 PM PDT 24
Finished Mar 31 03:46:04 PM PDT 24
Peak memory 235700 kb
Host smart-2edb4630-e560-4098-aa98-5ca1b2fc3916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700439244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.2700439244
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.4274948729
Short name T470
Test name
Test status
Simulation time 1734970729 ps
CPU time 40.78 seconds
Started Mar 31 03:45:52 PM PDT 24
Finished Mar 31 03:46:33 PM PDT 24
Peak memory 416188 kb
Host smart-ffb16e88-5091-4fe1-b400-39af678d9e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274948729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.4274948729
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stress_all.4044244008
Short name T55
Test name
Test status
Simulation time 83403898444 ps
CPU time 1561.68 seconds
Started Mar 31 03:45:58 PM PDT 24
Finished Mar 31 04:12:00 PM PDT 24
Peak memory 4642596 kb
Host smart-3b6374a3-8e24-44e7-952c-13481deec569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044244008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stress_all.4044244008
Directory /workspace/24.i2c_host_stress_all/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.255999882
Short name T265
Test name
Test status
Simulation time 2439484136 ps
CPU time 2.7 seconds
Started Mar 31 03:45:57 PM PDT 24
Finished Mar 31 03:46:00 PM PDT 24
Peak memory 203888 kb
Host smart-6f448323-b472-4489-8c5f-4e38fe9c2593
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255999882 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.255999882
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.3216942700
Short name T600
Test name
Test status
Simulation time 10220747390 ps
CPU time 31.41 seconds
Started Mar 31 03:45:59 PM PDT 24
Finished Mar 31 03:46:31 PM PDT 24
Peak memory 355316 kb
Host smart-1d87c8dc-a11d-464a-8df7-612adc080da4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216942700 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_reset_acq.3216942700
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.3170013010
Short name T830
Test name
Test status
Simulation time 10347527486 ps
CPU time 19.25 seconds
Started Mar 31 03:45:57 PM PDT 24
Finished Mar 31 03:46:17 PM PDT 24
Peak memory 356800 kb
Host smart-9e89c4db-da47-4837-b8b3-cd2497a665e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170013010 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.3170013010
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.1368763380
Short name T775
Test name
Test status
Simulation time 1770283141 ps
CPU time 2.61 seconds
Started Mar 31 03:45:59 PM PDT 24
Finished Mar 31 03:46:02 PM PDT 24
Peak memory 203740 kb
Host smart-0f8b1bbc-809b-4fba-ae56-02d7518a636b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368763380 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_hrst.1368763380
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.356755065
Short name T212
Test name
Test status
Simulation time 883235144 ps
CPU time 4.95 seconds
Started Mar 31 03:45:56 PM PDT 24
Finished Mar 31 03:46:01 PM PDT 24
Peak memory 204700 kb
Host smart-870fd0aa-461f-459c-8883-e701fe857a83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356755065 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_intr_smoke.356755065
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.832932467
Short name T525
Test name
Test status
Simulation time 5863556612 ps
CPU time 4.23 seconds
Started Mar 31 03:45:56 PM PDT 24
Finished Mar 31 03:46:01 PM PDT 24
Peak memory 203856 kb
Host smart-971ddb20-f08e-49f0-8418-157ec5782d5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832932467 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.832932467
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.3426976985
Short name T494
Test name
Test status
Simulation time 4889654777 ps
CPU time 20.84 seconds
Started Mar 31 03:46:00 PM PDT 24
Finished Mar 31 03:46:21 PM PDT 24
Peak memory 203820 kb
Host smart-13251a1b-8c5e-4e11-b7b6-8265cb6994e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426976985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_ta
rget_smoke.3426976985
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.843874398
Short name T502
Test name
Test status
Simulation time 719764720 ps
CPU time 6.39 seconds
Started Mar 31 03:45:55 PM PDT 24
Finished Mar 31 03:46:02 PM PDT 24
Peak memory 203796 kb
Host smart-3b84baba-6cba-45bc-bcf2-f8b5d8e98585
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843874398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c
_target_stress_rd.843874398
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.1141047425
Short name T598
Test name
Test status
Simulation time 3142281609 ps
CPU time 73.24 seconds
Started Mar 31 03:45:57 PM PDT 24
Finished Mar 31 03:47:10 PM PDT 24
Peak memory 517388 kb
Host smart-9aede8e6-cd52-45fb-b7ef-4daf33c2f488
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141047425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stretch.1141047425
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.474713834
Short name T1176
Test name
Test status
Simulation time 1505364458 ps
CPU time 7.36 seconds
Started Mar 31 03:45:55 PM PDT 24
Finished Mar 31 03:46:03 PM PDT 24
Peak memory 215788 kb
Host smart-6d92184a-a80e-4b5e-a1db-4a9bb079d1b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474713834 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_timeout.474713834
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_alert_test.1701333710
Short name T526
Test name
Test status
Simulation time 21699782 ps
CPU time 0.66 seconds
Started Mar 31 03:46:06 PM PDT 24
Finished Mar 31 03:46:07 PM PDT 24
Peak memory 203660 kb
Host smart-10629c20-b4e1-44c8-8aa8-b88c43b7f2a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701333710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.1701333710
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.3604017248
Short name T786
Test name
Test status
Simulation time 259870678 ps
CPU time 1.52 seconds
Started Mar 31 03:46:08 PM PDT 24
Finished Mar 31 03:46:10 PM PDT 24
Peak memory 212076 kb
Host smart-446dc637-1a4d-4aa4-936f-adfba295053f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604017248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.3604017248
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.3716751884
Short name T4
Test name
Test status
Simulation time 5172470954 ps
CPU time 5.72 seconds
Started Mar 31 03:46:07 PM PDT 24
Finished Mar 31 03:46:13 PM PDT 24
Peak memory 255372 kb
Host smart-d55190c7-cf08-4b01-b349-651a0063c49a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716751884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp
ty.3716751884
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.893673008
Short name T867
Test name
Test status
Simulation time 4842560973 ps
CPU time 73.04 seconds
Started Mar 31 03:46:05 PM PDT 24
Finished Mar 31 03:47:18 PM PDT 24
Peak memory 417332 kb
Host smart-5ef0e485-bcbe-4652-bf3e-0160c265249b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893673008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.893673008
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.2815983225
Short name T1085
Test name
Test status
Simulation time 1929972577 ps
CPU time 68.08 seconds
Started Mar 31 03:46:10 PM PDT 24
Finished Mar 31 03:47:18 PM PDT 24
Peak memory 671472 kb
Host smart-674ad9a5-4850-4a77-9058-9ebbaacbe465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815983225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.2815983225
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.787140764
Short name T469
Test name
Test status
Simulation time 482069576 ps
CPU time 1.05 seconds
Started Mar 31 03:46:04 PM PDT 24
Finished Mar 31 03:46:05 PM PDT 24
Peak memory 203784 kb
Host smart-e0a97e43-a631-45f3-894a-897ca753d89e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787140764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_fm
t.787140764
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.897207817
Short name T873
Test name
Test status
Simulation time 841524526 ps
CPU time 5.27 seconds
Started Mar 31 03:46:04 PM PDT 24
Finished Mar 31 03:46:09 PM PDT 24
Peak memory 245056 kb
Host smart-f1d0ea44-ca77-4d13-a922-a67f5a1786ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897207817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx.
897207817
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.4274170934
Short name T346
Test name
Test status
Simulation time 8341612908 ps
CPU time 322.25 seconds
Started Mar 31 03:46:09 PM PDT 24
Finished Mar 31 03:51:32 PM PDT 24
Peak memory 1219632 kb
Host smart-663ef8b1-6f3e-4325-8726-e2b4a6bd4866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274170934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.4274170934
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.3418177975
Short name T672
Test name
Test status
Simulation time 835359435 ps
CPU time 18.26 seconds
Started Mar 31 03:46:05 PM PDT 24
Finished Mar 31 03:46:24 PM PDT 24
Peak memory 203732 kb
Host smart-ef288c26-2744-46a9-b48e-450be0604cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418177975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.3418177975
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.1519309858
Short name T556
Test name
Test status
Simulation time 8312768354 ps
CPU time 57.44 seconds
Started Mar 31 03:46:06 PM PDT 24
Finished Mar 31 03:47:03 PM PDT 24
Peak memory 590920 kb
Host smart-897ddeba-083e-47e7-a194-bd6ae3c1813f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519309858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.1519309858
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.1865273260
Short name T790
Test name
Test status
Simulation time 113522054 ps
CPU time 0.7 seconds
Started Mar 31 03:46:07 PM PDT 24
Finished Mar 31 03:46:08 PM PDT 24
Peak memory 203608 kb
Host smart-d2d8f37b-8b11-4850-91d2-c9e4ccae2c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865273260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.1865273260
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.3449837919
Short name T789
Test name
Test status
Simulation time 5764995364 ps
CPU time 82.05 seconds
Started Mar 31 03:46:02 PM PDT 24
Finished Mar 31 03:47:24 PM PDT 24
Peak memory 203880 kb
Host smart-5bcb93ad-5052-4787-9188-4ae4e665b7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449837919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.3449837919
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.1601123004
Short name T544
Test name
Test status
Simulation time 5494195940 ps
CPU time 28.62 seconds
Started Mar 31 03:45:57 PM PDT 24
Finished Mar 31 03:46:25 PM PDT 24
Peak memory 341924 kb
Host smart-fafcbcf3-2e9e-465e-8e97-1bb063665c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601123004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.1601123004
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.2706890516
Short name T836
Test name
Test status
Simulation time 988326086 ps
CPU time 4.51 seconds
Started Mar 31 03:46:06 PM PDT 24
Finished Mar 31 03:46:11 PM PDT 24
Peak memory 203484 kb
Host smart-22f3997e-15aa-4339-85ae-1fca633854bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706890516 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.2706890516
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.3599135726
Short name T514
Test name
Test status
Simulation time 10211067260 ps
CPU time 12.46 seconds
Started Mar 31 03:46:06 PM PDT 24
Finished Mar 31 03:46:18 PM PDT 24
Peak memory 282876 kb
Host smart-49d1f990-c6f7-48f4-b8a8-603e57005473
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599135726 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_fifo_reset_acq.3599135726
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.3333565268
Short name T964
Test name
Test status
Simulation time 10089904204 ps
CPU time 10.04 seconds
Started Mar 31 03:46:09 PM PDT 24
Finished Mar 31 03:46:19 PM PDT 24
Peak memory 288024 kb
Host smart-558b8b42-5221-404c-9583-b59ecf2ba614
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333565268 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.3333565268
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.1841678690
Short name T577
Test name
Test status
Simulation time 3827663402 ps
CPU time 2.83 seconds
Started Mar 31 03:46:08 PM PDT 24
Finished Mar 31 03:46:11 PM PDT 24
Peak memory 203860 kb
Host smart-c713863d-3ae1-43ee-8025-0da9be4273e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841678690 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_hrst.1841678690
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.3893741771
Short name T785
Test name
Test status
Simulation time 1070208335 ps
CPU time 4.95 seconds
Started Mar 31 03:46:06 PM PDT 24
Finished Mar 31 03:46:11 PM PDT 24
Peak memory 205628 kb
Host smart-258bc460-c14e-4d3c-8c0d-539e14c2948c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893741771 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_intr_smoke.3893741771
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.880692514
Short name T756
Test name
Test status
Simulation time 650166943 ps
CPU time 22.73 seconds
Started Mar 31 03:46:05 PM PDT 24
Finished Mar 31 03:46:28 PM PDT 24
Peak memory 203776 kb
Host smart-8012f394-c9aa-42e9-b232-3d31f39e3f49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880692514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_tar
get_smoke.880692514
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.4131412375
Short name T498
Test name
Test status
Simulation time 1322721059 ps
CPU time 20.68 seconds
Started Mar 31 03:46:05 PM PDT 24
Finished Mar 31 03:46:26 PM PDT 24
Peak memory 219784 kb
Host smart-f9f78cfc-b6cd-45a2-8c99-d03a68a61a35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131412375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.4131412375
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.1714630251
Short name T749
Test name
Test status
Simulation time 15915471594 ps
CPU time 825.81 seconds
Started Mar 31 03:46:04 PM PDT 24
Finished Mar 31 03:59:51 PM PDT 24
Peak memory 4001556 kb
Host smart-060f4a46-e39e-4409-a08b-0d2705aaee22
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714630251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.1714630251
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.3595931171
Short name T15
Test name
Test status
Simulation time 9779273413 ps
CPU time 6.34 seconds
Started Mar 31 03:46:04 PM PDT 24
Finished Mar 31 03:46:11 PM PDT 24
Peak memory 212140 kb
Host smart-1fde3fa2-e6f1-499a-9215-e7bd9afef996
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595931171 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_timeout.3595931171
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_alert_test.365530437
Short name T977
Test name
Test status
Simulation time 39855760 ps
CPU time 0.63 seconds
Started Mar 31 03:46:11 PM PDT 24
Finished Mar 31 03:46:12 PM PDT 24
Peak memory 203696 kb
Host smart-95c63eef-a62d-41b7-b440-6214fa023aa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365530437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.365530437
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.2453720717
Short name T971
Test name
Test status
Simulation time 390045859 ps
CPU time 1.39 seconds
Started Mar 31 03:46:05 PM PDT 24
Finished Mar 31 03:46:06 PM PDT 24
Peak memory 212020 kb
Host smart-ad70fb5a-34df-43c2-951b-a2f72170fa2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453720717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.2453720717
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.1484444148
Short name T269
Test name
Test status
Simulation time 1463541135 ps
CPU time 6.71 seconds
Started Mar 31 03:46:04 PM PDT 24
Finished Mar 31 03:46:10 PM PDT 24
Peak memory 261532 kb
Host smart-aa474919-2138-4036-abbc-3ec71bc69028
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484444148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp
ty.1484444148
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.2021589206
Short name T529
Test name
Test status
Simulation time 1304488032 ps
CPU time 35.51 seconds
Started Mar 31 03:46:05 PM PDT 24
Finished Mar 31 03:46:41 PM PDT 24
Peak memory 480056 kb
Host smart-84f4a4eb-8b2d-401c-abce-87dcb8c592b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021589206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.2021589206
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.668038681
Short name T606
Test name
Test status
Simulation time 1085088768 ps
CPU time 66.98 seconds
Started Mar 31 03:46:08 PM PDT 24
Finished Mar 31 03:47:15 PM PDT 24
Peak memory 407228 kb
Host smart-ed34ca66-acd1-4b77-8e6a-5b9de2204f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668038681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.668038681
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.3311784661
Short name T6
Test name
Test status
Simulation time 139784983 ps
CPU time 0.92 seconds
Started Mar 31 03:46:04 PM PDT 24
Finished Mar 31 03:46:05 PM PDT 24
Peak memory 203724 kb
Host smart-cfeb6b1b-5d1f-4bdb-a1e6-e6f3770990cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311784661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f
mt.3311784661
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.1773187436
Short name T732
Test name
Test status
Simulation time 198309082 ps
CPU time 7.4 seconds
Started Mar 31 03:46:05 PM PDT 24
Finished Mar 31 03:46:12 PM PDT 24
Peak memory 224952 kb
Host smart-4fcc02b9-0277-4f5c-9764-50d304398929
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773187436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.1773187436
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.1664242264
Short name T163
Test name
Test status
Simulation time 3941367955 ps
CPU time 96.43 seconds
Started Mar 31 03:46:08 PM PDT 24
Finished Mar 31 03:47:45 PM PDT 24
Peak memory 1149772 kb
Host smart-2ccf50f2-518a-4900-8637-aff683305887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664242264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.1664242264
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.223315853
Short name T451
Test name
Test status
Simulation time 1939248816 ps
CPU time 4.66 seconds
Started Mar 31 03:46:10 PM PDT 24
Finished Mar 31 03:46:15 PM PDT 24
Peak memory 203792 kb
Host smart-2303642f-3038-49f9-98c0-7411a437cc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223315853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.223315853
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.1482947208
Short name T1057
Test name
Test status
Simulation time 1663199329 ps
CPU time 38.56 seconds
Started Mar 31 03:46:08 PM PDT 24
Finished Mar 31 03:46:47 PM PDT 24
Peak memory 416592 kb
Host smart-32c6d758-9a6c-453e-be37-b0933e5eaa17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482947208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.1482947208
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_override.2033486924
Short name T301
Test name
Test status
Simulation time 78565481 ps
CPU time 0.67 seconds
Started Mar 31 03:46:05 PM PDT 24
Finished Mar 31 03:46:06 PM PDT 24
Peak memory 203604 kb
Host smart-076d46a0-ff13-4db5-ac25-c4215355e55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033486924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.2033486924
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.1822585093
Short name T1184
Test name
Test status
Simulation time 936437914 ps
CPU time 45.06 seconds
Started Mar 31 03:46:05 PM PDT 24
Finished Mar 31 03:46:50 PM PDT 24
Peak memory 296552 kb
Host smart-96112a80-dc5e-476a-aab5-0e35923e0ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822585093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.1822585093
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.1405464368
Short name T480
Test name
Test status
Simulation time 3794056904 ps
CPU time 47.68 seconds
Started Mar 31 03:46:05 PM PDT 24
Finished Mar 31 03:46:53 PM PDT 24
Peak memory 309572 kb
Host smart-d5e3cd65-da90-407d-9f01-d3367f4bc503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405464368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.1405464368
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.4075949503
Short name T866
Test name
Test status
Simulation time 1688400055 ps
CPU time 2.99 seconds
Started Mar 31 03:46:07 PM PDT 24
Finished Mar 31 03:46:10 PM PDT 24
Peak memory 203860 kb
Host smart-b8b254f5-5b13-478b-8be7-fd3d01116bdd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075949503 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.4075949503
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.423152209
Short name T495
Test name
Test status
Simulation time 10038537619 ps
CPU time 75.49 seconds
Started Mar 31 03:46:08 PM PDT 24
Finished Mar 31 03:47:23 PM PDT 24
Peak memory 553664 kb
Host smart-1ecb0a44-3278-4306-bfcb-a7f19c26a3e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423152209 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_acq.423152209
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.3669107080
Short name T66
Test name
Test status
Simulation time 10236311074 ps
CPU time 42.64 seconds
Started Mar 31 03:46:09 PM PDT 24
Finished Mar 31 03:46:52 PM PDT 24
Peak memory 476528 kb
Host smart-1b0e2818-45c0-4ca5-8468-1e4a3b6658ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669107080 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_tx.3669107080
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.2960933587
Short name T1188
Test name
Test status
Simulation time 1744557992 ps
CPU time 2.86 seconds
Started Mar 31 03:46:08 PM PDT 24
Finished Mar 31 03:46:11 PM PDT 24
Peak memory 203820 kb
Host smart-62b904da-187b-495d-9fe3-a46e0d5ea2b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960933587 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_hrst.2960933587
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.3260913390
Short name T398
Test name
Test status
Simulation time 1296372850 ps
CPU time 6.73 seconds
Started Mar 31 03:46:19 PM PDT 24
Finished Mar 31 03:46:26 PM PDT 24
Peak memory 220024 kb
Host smart-26eee310-9fef-4c7f-a8b3-80fb71a4ade6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260913390 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.3260913390
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.1725497095
Short name T611
Test name
Test status
Simulation time 5121038913 ps
CPU time 11.85 seconds
Started Mar 31 03:46:10 PM PDT 24
Finished Mar 31 03:46:22 PM PDT 24
Peak memory 203848 kb
Host smart-55e17ebd-52a5-43e2-8a25-fc8cf04af2d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725497095 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.1725497095
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.2268036331
Short name T881
Test name
Test status
Simulation time 1258472491 ps
CPU time 8.02 seconds
Started Mar 31 03:46:05 PM PDT 24
Finished Mar 31 03:46:13 PM PDT 24
Peak memory 203792 kb
Host smart-0493e688-6d5a-4e8b-ad2c-548fcb1e432d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268036331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_smoke.2268036331
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.2539109672
Short name T1021
Test name
Test status
Simulation time 1256766628 ps
CPU time 23.82 seconds
Started Mar 31 03:46:11 PM PDT 24
Finished Mar 31 03:46:35 PM PDT 24
Peak memory 218204 kb
Host smart-bb682bf4-bab7-4960-b639-52bde5467bde
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539109672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.2539109672
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.1597070810
Short name T572
Test name
Test status
Simulation time 44633843077 ps
CPU time 3399.76 seconds
Started Mar 31 03:46:10 PM PDT 24
Finished Mar 31 04:42:51 PM PDT 24
Peak memory 4873876 kb
Host smart-2408f743-631b-4b4f-a61d-2c45ec8949f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597070810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stretch.1597070810
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.1920544571
Short name T638
Test name
Test status
Simulation time 9146540770 ps
CPU time 6.45 seconds
Started Mar 31 03:46:10 PM PDT 24
Finished Mar 31 03:46:17 PM PDT 24
Peak memory 203912 kb
Host smart-6da030e6-49c2-40b6-88f7-a0db88640840
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920544571 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.1920544571
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_alert_test.3996002264
Short name T1054
Test name
Test status
Simulation time 16656460 ps
CPU time 0.62 seconds
Started Mar 31 03:46:17 PM PDT 24
Finished Mar 31 03:46:18 PM PDT 24
Peak memory 203536 kb
Host smart-9f7faff0-9385-41d9-8e26-16a53bc74c70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996002264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.3996002264
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.1066760941
Short name T473
Test name
Test status
Simulation time 92686956 ps
CPU time 1.41 seconds
Started Mar 31 03:46:11 PM PDT 24
Finished Mar 31 03:46:12 PM PDT 24
Peak memory 211788 kb
Host smart-dcf7a878-211f-41e6-93b0-9d23b9be8c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066760941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.1066760941
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.2799994352
Short name T1023
Test name
Test status
Simulation time 3066517627 ps
CPU time 9.46 seconds
Started Mar 31 03:46:08 PM PDT 24
Finished Mar 31 03:46:18 PM PDT 24
Peak memory 238972 kb
Host smart-3e650ef2-d884-47dd-9dcb-4eda39d112a1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799994352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.2799994352
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.3666774324
Short name T913
Test name
Test status
Simulation time 1473720340 ps
CPU time 99.45 seconds
Started Mar 31 03:46:08 PM PDT 24
Finished Mar 31 03:47:48 PM PDT 24
Peak memory 536784 kb
Host smart-61088a91-7c81-46b3-8a1b-9943fcfb70e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666774324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.3666774324
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.3486554768
Short name T290
Test name
Test status
Simulation time 2007729155 ps
CPU time 64.12 seconds
Started Mar 31 03:46:09 PM PDT 24
Finished Mar 31 03:47:13 PM PDT 24
Peak memory 680700 kb
Host smart-55ef7c1f-8fda-4f53-9855-3e46f83391f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486554768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.3486554768
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.1674660369
Short name T387
Test name
Test status
Simulation time 150900519 ps
CPU time 0.82 seconds
Started Mar 31 03:46:10 PM PDT 24
Finished Mar 31 03:46:11 PM PDT 24
Peak memory 203680 kb
Host smart-39f7e502-f966-413e-8093-033692319437
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674660369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_f
mt.1674660369
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.2889389305
Short name T91
Test name
Test status
Simulation time 184080973 ps
CPU time 4.48 seconds
Started Mar 31 03:46:11 PM PDT 24
Finished Mar 31 03:46:15 PM PDT 24
Peak memory 236408 kb
Host smart-92c1a562-c585-4a4f-a438-902e034591f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889389305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.2889389305
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.3684454735
Short name T832
Test name
Test status
Simulation time 4345548078 ps
CPU time 120.77 seconds
Started Mar 31 03:46:10 PM PDT 24
Finished Mar 31 03:48:11 PM PDT 24
Peak memory 1274496 kb
Host smart-8a03ea0c-b149-487b-9eba-19fe6b8f955c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684454735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.3684454735
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.4291668046
Short name T17
Test name
Test status
Simulation time 273242438 ps
CPU time 10.87 seconds
Started Mar 31 03:46:14 PM PDT 24
Finished Mar 31 03:46:25 PM PDT 24
Peak memory 203848 kb
Host smart-ce1fae77-49a7-433e-b373-b652c845b11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291668046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.4291668046
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.714239362
Short name T834
Test name
Test status
Simulation time 3748408065 ps
CPU time 45.52 seconds
Started Mar 31 03:46:17 PM PDT 24
Finished Mar 31 03:47:03 PM PDT 24
Peak memory 342012 kb
Host smart-64d74088-85e1-4fbb-a6dc-ef80b76db193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714239362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.714239362
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.1979595409
Short name T207
Test name
Test status
Simulation time 58613781 ps
CPU time 0.65 seconds
Started Mar 31 03:46:19 PM PDT 24
Finished Mar 31 03:46:21 PM PDT 24
Peak memory 203608 kb
Host smart-c2e679a3-4314-469e-8c90-4032b5279a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979595409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.1979595409
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.2400541054
Short name T1138
Test name
Test status
Simulation time 13545579180 ps
CPU time 36.12 seconds
Started Mar 31 03:46:10 PM PDT 24
Finished Mar 31 03:46:47 PM PDT 24
Peak memory 236300 kb
Host smart-8c03f812-b13f-4c34-b729-578827466c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400541054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.2400541054
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.2598581597
Short name T587
Test name
Test status
Simulation time 9504605140 ps
CPU time 61.97 seconds
Started Mar 31 03:46:19 PM PDT 24
Finished Mar 31 03:47:22 PM PDT 24
Peak memory 373068 kb
Host smart-9c443c23-51b9-42be-a589-70b0cff77f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598581597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.2598581597
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.969664675
Short name T317
Test name
Test status
Simulation time 681234760 ps
CPU time 3.57 seconds
Started Mar 31 03:46:16 PM PDT 24
Finished Mar 31 03:46:20 PM PDT 24
Peak memory 211968 kb
Host smart-8449227b-79ff-4cf5-9874-229b0ec75592
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969664675 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.969664675
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.2346883402
Short name T433
Test name
Test status
Simulation time 10030075340 ps
CPU time 67.6 seconds
Started Mar 31 03:46:08 PM PDT 24
Finished Mar 31 03:47:16 PM PDT 24
Peak memory 527216 kb
Host smart-5ae473e7-d3c1-4077-982c-1935ccfb4694
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346883402 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_fifo_reset_acq.2346883402
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.3822198247
Short name T1212
Test name
Test status
Simulation time 10089013970 ps
CPU time 94.97 seconds
Started Mar 31 03:46:17 PM PDT 24
Finished Mar 31 03:47:52 PM PDT 24
Peak memory 713124 kb
Host smart-3af4552f-5957-4c7a-913c-22d6ef3f28de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822198247 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.3822198247
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.745471458
Short name T485
Test name
Test status
Simulation time 1709220054 ps
CPU time 2.43 seconds
Started Mar 31 03:46:21 PM PDT 24
Finished Mar 31 03:46:24 PM PDT 24
Peak memory 203712 kb
Host smart-758254d2-31c5-4f7d-9205-c3b92b8ebe4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745471458 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 27.i2c_target_hrst.745471458
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.1339942298
Short name T1032
Test name
Test status
Simulation time 925680337 ps
CPU time 5.24 seconds
Started Mar 31 03:46:12 PM PDT 24
Finished Mar 31 03:46:18 PM PDT 24
Peak memory 203228 kb
Host smart-5d2b79e7-2c13-4aaf-8309-39f0283b166b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339942298 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.1339942298
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.137796423
Short name T568
Test name
Test status
Simulation time 3050416936 ps
CPU time 23.43 seconds
Started Mar 31 03:46:19 PM PDT 24
Finished Mar 31 03:46:43 PM PDT 24
Peak memory 203824 kb
Host smart-6054fc1a-b503-42d3-872b-b449df644fff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137796423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_tar
get_smoke.137796423
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.3009835022
Short name T604
Test name
Test status
Simulation time 702497495 ps
CPU time 11.54 seconds
Started Mar 31 03:46:16 PM PDT 24
Finished Mar 31 03:46:27 PM PDT 24
Peak memory 207436 kb
Host smart-3552e1ab-662d-45b1-931c-5fc549051963
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009835022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_rd.3009835022
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.2981792286
Short name T395
Test name
Test status
Simulation time 14603453999 ps
CPU time 226.47 seconds
Started Mar 31 03:46:16 PM PDT 24
Finished Mar 31 03:50:02 PM PDT 24
Peak memory 1874244 kb
Host smart-cba5e02e-c54d-4571-b48a-9698a59835c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981792286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stretch.2981792286
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.3569293014
Short name T337
Test name
Test status
Simulation time 7217500912 ps
CPU time 7.95 seconds
Started Mar 31 03:46:19 PM PDT 24
Finished Mar 31 03:46:28 PM PDT 24
Peak memory 211108 kb
Host smart-1de5d438-e20c-4289-ac81-cd3c356007ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569293014 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.3569293014
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_alert_test.3805352512
Short name T632
Test name
Test status
Simulation time 18381926 ps
CPU time 0.61 seconds
Started Mar 31 03:46:22 PM PDT 24
Finished Mar 31 03:46:23 PM PDT 24
Peak memory 203676 kb
Host smart-ef9a8060-427f-4418-a07b-88aa99baea0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805352512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.3805352512
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.1344008576
Short name T594
Test name
Test status
Simulation time 198425638 ps
CPU time 1.77 seconds
Started Mar 31 03:46:16 PM PDT 24
Finished Mar 31 03:46:18 PM PDT 24
Peak memory 212012 kb
Host smart-912523b0-4284-4dbe-9840-028f35c400d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344008576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.1344008576
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.2849098618
Short name T721
Test name
Test status
Simulation time 725553119 ps
CPU time 8.47 seconds
Started Mar 31 03:46:20 PM PDT 24
Finished Mar 31 03:46:29 PM PDT 24
Peak memory 279820 kb
Host smart-a1d581f1-bb94-408d-878a-24a47f00abd2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849098618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_emp
ty.2849098618
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.2302374750
Short name T334
Test name
Test status
Simulation time 5506199464 ps
CPU time 39.36 seconds
Started Mar 31 03:46:14 PM PDT 24
Finished Mar 31 03:46:54 PM PDT 24
Peak memory 444452 kb
Host smart-2c2dc0fa-ce71-4e3a-9794-13c4688550f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302374750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.2302374750
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.1614208081
Short name T796
Test name
Test status
Simulation time 5166738767 ps
CPU time 84.17 seconds
Started Mar 31 03:46:17 PM PDT 24
Finished Mar 31 03:47:43 PM PDT 24
Peak memory 484436 kb
Host smart-c14a72bb-ae4a-48ea-8b6d-a9a86c456bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614208081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.1614208081
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.4202152359
Short name T824
Test name
Test status
Simulation time 247699127 ps
CPU time 3.12 seconds
Started Mar 31 03:46:14 PM PDT 24
Finished Mar 31 03:46:18 PM PDT 24
Peak memory 224100 kb
Host smart-b1df3a9e-bb61-42bc-9a49-c4f864da501e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202152359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.4202152359
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.4172878366
Short name T612
Test name
Test status
Simulation time 14162239731 ps
CPU time 267.94 seconds
Started Mar 31 03:46:17 PM PDT 24
Finished Mar 31 03:50:45 PM PDT 24
Peak memory 1051160 kb
Host smart-f441354f-4d1e-437b-9316-b57d54990cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172878366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.4172878366
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.121598489
Short name T803
Test name
Test status
Simulation time 1766562477 ps
CPU time 9.71 seconds
Started Mar 31 03:46:20 PM PDT 24
Finished Mar 31 03:46:30 PM PDT 24
Peak memory 203752 kb
Host smart-4d39bd9c-8b6c-4cf7-a8cb-b096c28655ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121598489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.121598489
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.1655335226
Short name T894
Test name
Test status
Simulation time 6119248244 ps
CPU time 17.77 seconds
Started Mar 31 03:46:22 PM PDT 24
Finished Mar 31 03:46:40 PM PDT 24
Peak memory 308180 kb
Host smart-11a7b94d-893b-4121-8180-743d0f063479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655335226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.1655335226
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.2505308012
Short name T794
Test name
Test status
Simulation time 48172643 ps
CPU time 0.64 seconds
Started Mar 31 03:46:18 PM PDT 24
Finished Mar 31 03:46:19 PM PDT 24
Peak memory 203588 kb
Host smart-cc97cfc6-94e1-4222-a208-22ed59a38ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505308012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.2505308012
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.813411611
Short name T626
Test name
Test status
Simulation time 2511807489 ps
CPU time 66.26 seconds
Started Mar 31 03:46:19 PM PDT 24
Finished Mar 31 03:47:26 PM PDT 24
Peak memory 383144 kb
Host smart-84e943aa-7202-4d54-a3e1-4f37be8f58fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813411611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.813411611
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.1909391464
Short name T654
Test name
Test status
Simulation time 3426317333 ps
CPU time 3.99 seconds
Started Mar 31 03:46:21 PM PDT 24
Finished Mar 31 03:46:26 PM PDT 24
Peak memory 203668 kb
Host smart-88f15162-a233-414c-b3b7-66ffe4d178e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909391464 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.1909391464
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.17069639
Short name T406
Test name
Test status
Simulation time 10185966042 ps
CPU time 31.86 seconds
Started Mar 31 03:46:16 PM PDT 24
Finished Mar 31 03:46:48 PM PDT 24
Peak memory 411360 kb
Host smart-4f0bd920-9e77-4a71-9011-8bc8b849b247
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17069639 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.i2c_target_fifo_reset_acq.17069639
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.70872177
Short name T747
Test name
Test status
Simulation time 10123536899 ps
CPU time 66.4 seconds
Started Mar 31 03:46:16 PM PDT 24
Finished Mar 31 03:47:23 PM PDT 24
Peak memory 597168 kb
Host smart-dde774d4-9995-48bd-a27e-3d59fa3e3057
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70872177 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.i2c_target_fifo_reset_tx.70872177
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.1298881712
Short name T84
Test name
Test status
Simulation time 777040287 ps
CPU time 2.4 seconds
Started Mar 31 03:46:15 PM PDT 24
Finished Mar 31 03:46:18 PM PDT 24
Peak memory 203764 kb
Host smart-0f2bab30-9d96-48da-98d6-5a249072cd80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298881712 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.1298881712
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.484864348
Short name T339
Test name
Test status
Simulation time 1470496272 ps
CPU time 3.98 seconds
Started Mar 31 03:46:20 PM PDT 24
Finished Mar 31 03:46:25 PM PDT 24
Peak memory 203772 kb
Host smart-ed19a327-0315-470b-9bbb-0a63ef68a168
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484864348 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_intr_smoke.484864348
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.1963489518
Short name T285
Test name
Test status
Simulation time 5532906236 ps
CPU time 13.17 seconds
Started Mar 31 03:46:15 PM PDT 24
Finished Mar 31 03:46:28 PM PDT 24
Peak memory 203820 kb
Host smart-aa5dad6a-d135-4698-8368-dde3f4956f69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963489518 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.1963489518
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.4163320977
Short name T1137
Test name
Test status
Simulation time 1102555988 ps
CPU time 17.77 seconds
Started Mar 31 03:46:15 PM PDT 24
Finished Mar 31 03:46:33 PM PDT 24
Peak memory 203816 kb
Host smart-b2d7321b-4099-40e5-863a-f5d3d96ca0ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163320977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.4163320977
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.2381475749
Short name T815
Test name
Test status
Simulation time 770742671 ps
CPU time 32.15 seconds
Started Mar 31 03:46:16 PM PDT 24
Finished Mar 31 03:46:49 PM PDT 24
Peak memory 203736 kb
Host smart-be060a11-ede1-490a-b0e9-ff04f635b358
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381475749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.2381475749
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.521876246
Short name T1029
Test name
Test status
Simulation time 10183396942 ps
CPU time 10.55 seconds
Started Mar 31 03:46:20 PM PDT 24
Finished Mar 31 03:46:31 PM PDT 24
Peak memory 203900 kb
Host smart-199456b4-d8b8-4ea0-91bc-76469d048633
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521876246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c
_target_stress_wr.521876246
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.1331783691
Short name T1065
Test name
Test status
Simulation time 11444072646 ps
CPU time 1116.09 seconds
Started Mar 31 03:46:19 PM PDT 24
Finished Mar 31 04:04:56 PM PDT 24
Peak memory 2490784 kb
Host smart-04851519-3f87-433e-a93e-3625954c0d16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331783691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stretch.1331783691
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.3057035158
Short name T843
Test name
Test status
Simulation time 6167292837 ps
CPU time 7.25 seconds
Started Mar 31 03:46:16 PM PDT 24
Finished Mar 31 03:46:23 PM PDT 24
Peak memory 210540 kb
Host smart-998b5563-b541-4b18-8c7d-31ba2f98376e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057035158 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.3057035158
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_alert_test.882829824
Short name T648
Test name
Test status
Simulation time 21614331 ps
CPU time 0.58 seconds
Started Mar 31 03:46:29 PM PDT 24
Finished Mar 31 03:46:30 PM PDT 24
Peak memory 203624 kb
Host smart-779f94ea-7bb8-412c-913d-3dd57a79eaf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882829824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.882829824
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.3236646692
Short name T1162
Test name
Test status
Simulation time 323471530 ps
CPU time 1.61 seconds
Started Mar 31 03:46:22 PM PDT 24
Finished Mar 31 03:46:24 PM PDT 24
Peak memory 220264 kb
Host smart-a68de81e-4b2f-4650-98b2-21142e2dc753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236646692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.3236646692
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.2718651551
Short name T255
Test name
Test status
Simulation time 1316708359 ps
CPU time 16.07 seconds
Started Mar 31 03:46:22 PM PDT 24
Finished Mar 31 03:46:38 PM PDT 24
Peak memory 244200 kb
Host smart-ba1ce26b-b9b6-42d9-a5a2-43a0162da4ef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718651551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.2718651551
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.1576478372
Short name T54
Test name
Test status
Simulation time 4157494607 ps
CPU time 149.68 seconds
Started Mar 31 03:46:21 PM PDT 24
Finished Mar 31 03:48:52 PM PDT 24
Peak memory 699048 kb
Host smart-7890f0d1-b071-4357-93e4-125279d4df3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576478372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.1576478372
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.2225020275
Short name T541
Test name
Test status
Simulation time 2021948139 ps
CPU time 78.61 seconds
Started Mar 31 03:46:22 PM PDT 24
Finished Mar 31 03:47:41 PM PDT 24
Peak memory 706784 kb
Host smart-c1f47f8b-c815-479a-86f7-e292e91d9302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225020275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.2225020275
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.499177913
Short name T996
Test name
Test status
Simulation time 310578787 ps
CPU time 0.85 seconds
Started Mar 31 03:46:19 PM PDT 24
Finished Mar 31 03:46:21 PM PDT 24
Peak memory 203700 kb
Host smart-3decf556-edd0-4ac0-8630-267e1c96748b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499177913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_fm
t.499177913
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.1909120494
Short name T197
Test name
Test status
Simulation time 107614492 ps
CPU time 3.07 seconds
Started Mar 31 03:46:21 PM PDT 24
Finished Mar 31 03:46:24 PM PDT 24
Peak memory 216576 kb
Host smart-3a8d5993-9469-440f-8f2c-7b35af170cfb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909120494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx
.1909120494
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.196176574
Short name T98
Test name
Test status
Simulation time 6696572295 ps
CPU time 101.44 seconds
Started Mar 31 03:46:20 PM PDT 24
Finished Mar 31 03:48:02 PM PDT 24
Peak memory 1021044 kb
Host smart-8dc1cb63-ab7f-4cff-938b-dcd998271224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196176574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.196176574
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.1485727270
Short name T647
Test name
Test status
Simulation time 10912231414 ps
CPU time 23.1 seconds
Started Mar 31 03:46:22 PM PDT 24
Finished Mar 31 03:46:45 PM PDT 24
Peak memory 203856 kb
Host smart-9fbe96cb-e9ec-4c1a-a51e-5ecb398ed1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485727270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.1485727270
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.851927456
Short name T439
Test name
Test status
Simulation time 1763455827 ps
CPU time 95.13 seconds
Started Mar 31 03:46:21 PM PDT 24
Finished Mar 31 03:47:56 PM PDT 24
Peak memory 459936 kb
Host smart-a6011a99-2879-47d6-80bd-39bc3761c2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851927456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.851927456
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_host_override.605976701
Short name T425
Test name
Test status
Simulation time 15229315 ps
CPU time 0.67 seconds
Started Mar 31 03:46:20 PM PDT 24
Finished Mar 31 03:46:21 PM PDT 24
Peak memory 203544 kb
Host smart-ee73603c-8a8d-46c4-bb44-599a0c68d5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605976701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.605976701
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.413899317
Short name T193
Test name
Test status
Simulation time 5566114489 ps
CPU time 16.81 seconds
Started Mar 31 03:46:24 PM PDT 24
Finished Mar 31 03:46:41 PM PDT 24
Peak memory 212084 kb
Host smart-91276fb5-2e6b-46cb-adfb-4c0c41dc8f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413899317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.413899317
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.2406351322
Short name T253
Test name
Test status
Simulation time 5331562526 ps
CPU time 67.78 seconds
Started Mar 31 03:46:21 PM PDT 24
Finished Mar 31 03:47:29 PM PDT 24
Peak memory 349284 kb
Host smart-96db8630-a419-45d8-b3c1-64382579a3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406351322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.2406351322
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.1873590001
Short name T763
Test name
Test status
Simulation time 759367937 ps
CPU time 3.43 seconds
Started Mar 31 03:46:23 PM PDT 24
Finished Mar 31 03:46:26 PM PDT 24
Peak memory 203780 kb
Host smart-aa7711a9-8291-4e0b-9338-46adb84c3ff9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873590001 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.1873590001
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.353446200
Short name T608
Test name
Test status
Simulation time 10341755644 ps
CPU time 4.43 seconds
Started Mar 31 03:46:22 PM PDT 24
Finished Mar 31 03:46:26 PM PDT 24
Peak memory 222684 kb
Host smart-a2aec516-b95c-43ee-b61a-dbc6d977a96d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353446200 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_acq.353446200
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.3218292667
Short name T175
Test name
Test status
Simulation time 10133513015 ps
CPU time 43.18 seconds
Started Mar 31 03:46:23 PM PDT 24
Finished Mar 31 03:47:07 PM PDT 24
Peak memory 443268 kb
Host smart-50fee6e7-2b14-4bed-bf57-4bd6626042b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218292667 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.3218292667
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.3289939828
Short name T787
Test name
Test status
Simulation time 291395924 ps
CPU time 2.1 seconds
Started Mar 31 03:46:21 PM PDT 24
Finished Mar 31 03:46:23 PM PDT 24
Peak memory 203772 kb
Host smart-f698e4df-50e1-48a7-a37e-6c617ac823bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289939828 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_hrst.3289939828
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.2034949860
Short name T347
Test name
Test status
Simulation time 2082421701 ps
CPU time 5.74 seconds
Started Mar 31 03:46:25 PM PDT 24
Finished Mar 31 03:46:31 PM PDT 24
Peak memory 203844 kb
Host smart-bc560edb-27f8-4907-9583-171199ac1210
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034949860 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_intr_smoke.2034949860
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.2327504207
Short name T1091
Test name
Test status
Simulation time 1069283596 ps
CPU time 9.77 seconds
Started Mar 31 03:46:23 PM PDT 24
Finished Mar 31 03:46:33 PM PDT 24
Peak memory 203832 kb
Host smart-96b919b3-7597-4471-9a49-c9c516f4badf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327504207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_smoke.2327504207
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.2442793390
Short name T448
Test name
Test status
Simulation time 2337564486 ps
CPU time 18.43 seconds
Started Mar 31 03:46:19 PM PDT 24
Finished Mar 31 03:46:38 PM PDT 24
Peak memory 217740 kb
Host smart-7389dcca-9515-4e3d-ba13-c14d53b4f0e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442793390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_rd.2442793390
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.2698541979
Short name T828
Test name
Test status
Simulation time 17657876994 ps
CPU time 146.43 seconds
Started Mar 31 03:46:24 PM PDT 24
Finished Mar 31 03:48:50 PM PDT 24
Peak memory 1118416 kb
Host smart-bd988a54-98bc-4fbc-bbf9-c12a607250da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698541979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_
target_stretch.2698541979
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.3249065935
Short name T444
Test name
Test status
Simulation time 21224856011 ps
CPU time 7.69 seconds
Started Mar 31 03:46:24 PM PDT 24
Finished Mar 31 03:46:32 PM PDT 24
Peak memory 219048 kb
Host smart-9e4501b4-9a5e-4f8a-ba54-1adc6cbd6d9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249065935 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_timeout.3249065935
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_alert_test.3417311420
Short name T1106
Test name
Test status
Simulation time 23264061 ps
CPU time 0.63 seconds
Started Mar 31 03:43:57 PM PDT 24
Finished Mar 31 03:43:58 PM PDT 24
Peak memory 203680 kb
Host smart-6a7bc8da-7e62-4078-bc32-c9edc0f2deb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417311420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.3417311420
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.1677096320
Short name T516
Test name
Test status
Simulation time 98449739 ps
CPU time 1.48 seconds
Started Mar 31 03:43:57 PM PDT 24
Finished Mar 31 03:43:58 PM PDT 24
Peak memory 211968 kb
Host smart-62eca809-e06d-4b15-b385-bd3c2c7214b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677096320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.1677096320
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.2480448873
Short name T173
Test name
Test status
Simulation time 275514108 ps
CPU time 5.15 seconds
Started Mar 31 03:43:56 PM PDT 24
Finished Mar 31 03:44:01 PM PDT 24
Peak memory 259464 kb
Host smart-0975bf4c-ff56-4cb3-91b1-ce281df10a7d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480448873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.2480448873
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.2931497423
Short name T895
Test name
Test status
Simulation time 11034656645 ps
CPU time 75.81 seconds
Started Mar 31 03:44:03 PM PDT 24
Finished Mar 31 03:45:18 PM PDT 24
Peak memory 753292 kb
Host smart-f36d9a56-a23d-49ef-97d1-b94ec30e24b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931497423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.2931497423
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.1034739782
Short name T1093
Test name
Test status
Simulation time 1331929849 ps
CPU time 40.38 seconds
Started Mar 31 03:44:02 PM PDT 24
Finished Mar 31 03:44:42 PM PDT 24
Peak memory 500012 kb
Host smart-0d392460-9a33-4dcc-9be5-9036cf29a00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034739782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.1034739782
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.3964421452
Short name T1094
Test name
Test status
Simulation time 93352654 ps
CPU time 0.93 seconds
Started Mar 31 03:43:58 PM PDT 24
Finished Mar 31 03:43:59 PM PDT 24
Peak memory 203736 kb
Host smart-8bc7bffb-e6cb-43e5-b5b3-1460531562c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964421452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.3964421452
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.3306280325
Short name T462
Test name
Test status
Simulation time 197975677 ps
CPU time 10.52 seconds
Started Mar 31 03:43:55 PM PDT 24
Finished Mar 31 03:44:06 PM PDT 24
Peak memory 237796 kb
Host smart-e2bc5c05-e689-4f89-8ea1-8004a2aa85e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306280325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
3306280325
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.1756157338
Short name T886
Test name
Test status
Simulation time 2189373518 ps
CPU time 138.09 seconds
Started Mar 31 03:43:56 PM PDT 24
Finished Mar 31 03:46:14 PM PDT 24
Peak memory 730940 kb
Host smart-901e267c-b81d-4ac0-8845-86d450283235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756157338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.1756157338
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.1622755327
Short name T343
Test name
Test status
Simulation time 238404281 ps
CPU time 2.12 seconds
Started Mar 31 03:43:57 PM PDT 24
Finished Mar 31 03:43:59 PM PDT 24
Peak memory 203820 kb
Host smart-38baf230-6d89-4cb3-a03d-df92c313c3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622755327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.1622755327
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.3899771857
Short name T379
Test name
Test status
Simulation time 4309544760 ps
CPU time 20.55 seconds
Started Mar 31 03:43:55 PM PDT 24
Finished Mar 31 03:44:16 PM PDT 24
Peak memory 369620 kb
Host smart-366802a9-049f-48fd-9879-13f5e886e8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899771857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.3899771857
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.2335696104
Short name T802
Test name
Test status
Simulation time 47975413 ps
CPU time 0.67 seconds
Started Mar 31 03:43:57 PM PDT 24
Finished Mar 31 03:43:58 PM PDT 24
Peak memory 203588 kb
Host smart-c93dbf10-b47d-4334-a859-da937333330d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335696104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.2335696104
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.565785167
Short name T39
Test name
Test status
Simulation time 26634673940 ps
CPU time 1173.58 seconds
Started Mar 31 03:43:56 PM PDT 24
Finished Mar 31 04:03:30 PM PDT 24
Peak memory 3289900 kb
Host smart-935f3217-7f9c-48ac-89b8-881fcf392e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565785167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.565785167
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.2397323051
Short name T1107
Test name
Test status
Simulation time 1739492090 ps
CPU time 82.85 seconds
Started Mar 31 03:44:02 PM PDT 24
Finished Mar 31 03:45:25 PM PDT 24
Peak memory 361296 kb
Host smart-c8bb0878-9f2e-4330-b9ba-aadd5b7efaf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397323051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.2397323051
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.33279819
Short name T705
Test name
Test status
Simulation time 2033784530 ps
CPU time 2.72 seconds
Started Mar 31 03:43:59 PM PDT 24
Finished Mar 31 03:44:02 PM PDT 24
Peak memory 203776 kb
Host smart-89fd5dbc-2e26-4794-abd7-9762610c85a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33279819 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_bad_addr.33279819
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.3623877680
Short name T490
Test name
Test status
Simulation time 10164721998 ps
CPU time 57.26 seconds
Started Mar 31 03:43:57 PM PDT 24
Finished Mar 31 03:44:55 PM PDT 24
Peak memory 508752 kb
Host smart-45d6b811-1096-448c-ace0-8983a0ecebed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623877680 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.3623877680
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.508047145
Short name T1087
Test name
Test status
Simulation time 10421102545 ps
CPU time 15.04 seconds
Started Mar 31 03:43:59 PM PDT 24
Finished Mar 31 03:44:14 PM PDT 24
Peak memory 327092 kb
Host smart-d2d5458c-9ea0-4148-982a-f2b4193e222d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508047145 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.i2c_target_fifo_reset_tx.508047145
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.2028615511
Short name T640
Test name
Test status
Simulation time 9599640316 ps
CPU time 2.91 seconds
Started Mar 31 03:43:56 PM PDT 24
Finished Mar 31 03:43:59 PM PDT 24
Peak memory 203904 kb
Host smart-061c0dd3-88a7-46c2-b052-c7a96224a5b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028615511 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_hrst.2028615511
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.4196947096
Short name T1099
Test name
Test status
Simulation time 1332127143 ps
CPU time 6.77 seconds
Started Mar 31 03:43:59 PM PDT 24
Finished Mar 31 03:44:06 PM PDT 24
Peak memory 212000 kb
Host smart-fb3378a3-9d4f-4f72-a494-ef70dfa0c31e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196947096 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.4196947096
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.2730704708
Short name T412
Test name
Test status
Simulation time 5903011294 ps
CPU time 55.01 seconds
Started Mar 31 03:44:00 PM PDT 24
Finished Mar 31 03:44:55 PM PDT 24
Peak memory 203880 kb
Host smart-0f921e9b-29ae-4e97-909a-c1fc29ebe823
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730704708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_smoke.2730704708
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.1316305093
Short name T315
Test name
Test status
Simulation time 1638271271 ps
CPU time 32.68 seconds
Started Mar 31 03:43:57 PM PDT 24
Finished Mar 31 03:44:30 PM PDT 24
Peak memory 203832 kb
Host smart-a156b8c7-22e1-4511-b8e6-39f16e0d8600
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316305093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_rd.1316305093
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.456822724
Short name T733
Test name
Test status
Simulation time 1446948615 ps
CPU time 7.59 seconds
Started Mar 31 03:44:00 PM PDT 24
Finished Mar 31 03:44:08 PM PDT 24
Peak memory 220052 kb
Host smart-f48c1236-8380-4900-bb6c-f02c94bc43d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456822724 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_timeout.456822724
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_alert_test.306289972
Short name T613
Test name
Test status
Simulation time 35638444 ps
CPU time 0.59 seconds
Started Mar 31 03:46:32 PM PDT 24
Finished Mar 31 03:46:32 PM PDT 24
Peak memory 203692 kb
Host smart-f3cfc8a2-a91c-4757-a7ca-75094487a7ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306289972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.306289972
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.3224649520
Short name T1104
Test name
Test status
Simulation time 347084037 ps
CPU time 1.78 seconds
Started Mar 31 03:46:29 PM PDT 24
Finished Mar 31 03:46:31 PM PDT 24
Peak memory 212084 kb
Host smart-345546dc-36a4-446e-a63f-da82987a531a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224649520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.3224649520
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.1595451088
Short name T174
Test name
Test status
Simulation time 2304853879 ps
CPU time 4.73 seconds
Started Mar 31 03:46:29 PM PDT 24
Finished Mar 31 03:46:34 PM PDT 24
Peak memory 255688 kb
Host smart-e71beb63-4be4-4b35-adee-c72bb17895ca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595451088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.1595451088
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.987635936
Short name T862
Test name
Test status
Simulation time 12754734663 ps
CPU time 94.7 seconds
Started Mar 31 03:46:32 PM PDT 24
Finished Mar 31 03:48:06 PM PDT 24
Peak memory 712376 kb
Host smart-bd307b36-a338-4115-bd9f-f2827e79798b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987635936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.987635936
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.4264414690
Short name T816
Test name
Test status
Simulation time 11882537314 ps
CPU time 62.28 seconds
Started Mar 31 03:46:31 PM PDT 24
Finished Mar 31 03:47:33 PM PDT 24
Peak memory 585336 kb
Host smart-74461d17-071b-451f-8c22-258702ab8a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264414690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.4264414690
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.404671187
Short name T200
Test name
Test status
Simulation time 114741624 ps
CPU time 0.99 seconds
Started Mar 31 03:46:39 PM PDT 24
Finished Mar 31 03:46:40 PM PDT 24
Peak memory 203664 kb
Host smart-ca790e61-f105-4380-8409-d7816fc8ddfe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404671187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_fm
t.404671187
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.1560438156
Short name T196
Test name
Test status
Simulation time 457924278 ps
CPU time 2.64 seconds
Started Mar 31 03:46:30 PM PDT 24
Finished Mar 31 03:46:33 PM PDT 24
Peak memory 203868 kb
Host smart-971d3e6d-b36f-4a6f-a659-833e1386dcfc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560438156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.1560438156
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.2970281658
Short name T1083
Test name
Test status
Simulation time 7626346168 ps
CPU time 76.29 seconds
Started Mar 31 03:46:26 PM PDT 24
Finished Mar 31 03:47:43 PM PDT 24
Peak memory 884140 kb
Host smart-caec8d08-6e5c-4431-85b0-b98bffd06a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970281658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.2970281658
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.2116750979
Short name T1187
Test name
Test status
Simulation time 1219482568 ps
CPU time 2.74 seconds
Started Mar 31 03:46:30 PM PDT 24
Finished Mar 31 03:46:33 PM PDT 24
Peak memory 203844 kb
Host smart-718704e3-58e1-4d6e-902a-b95107220a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116750979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.2116750979
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.63366116
Short name T1178
Test name
Test status
Simulation time 4705457607 ps
CPU time 21.15 seconds
Started Mar 31 03:46:28 PM PDT 24
Finished Mar 31 03:46:49 PM PDT 24
Peak memory 279940 kb
Host smart-868211f5-3e61-42da-9760-68badcc2d748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63366116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.63366116
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_override.3560386274
Short name T627
Test name
Test status
Simulation time 55269461 ps
CPU time 0.65 seconds
Started Mar 31 03:46:31 PM PDT 24
Finished Mar 31 03:46:32 PM PDT 24
Peak memory 203576 kb
Host smart-07ccc919-957e-45b8-a6b5-cf26b6d6adad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560386274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.3560386274
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.3567287985
Short name T919
Test name
Test status
Simulation time 73325888740 ps
CPU time 3536.73 seconds
Started Mar 31 03:46:29 PM PDT 24
Finished Mar 31 04:45:27 PM PDT 24
Peak memory 3111132 kb
Host smart-129a3412-86cb-4792-936d-22455ce2b9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567287985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.3567287985
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.20799346
Short name T319
Test name
Test status
Simulation time 6313705567 ps
CPU time 30.37 seconds
Started Mar 31 03:46:22 PM PDT 24
Finished Mar 31 03:46:52 PM PDT 24
Peak memory 402800 kb
Host smart-874b2aaf-2e08-4c8c-909a-e8f5fb34fc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20799346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.20799346
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.176527885
Short name T344
Test name
Test status
Simulation time 479909773 ps
CPU time 2.72 seconds
Started Mar 31 03:46:28 PM PDT 24
Finished Mar 31 03:46:31 PM PDT 24
Peak memory 203788 kb
Host smart-c0897a43-8e17-40a9-88b8-aa01fb2bf581
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176527885 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.176527885
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.2155876092
Short name T359
Test name
Test status
Simulation time 10158788617 ps
CPU time 65.07 seconds
Started Mar 31 03:46:29 PM PDT 24
Finished Mar 31 03:47:35 PM PDT 24
Peak memory 508268 kb
Host smart-dda6f310-83f6-423a-971f-d1bf50c1d2cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155876092 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_reset_acq.2155876092
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.3134000687
Short name T684
Test name
Test status
Simulation time 10063779067 ps
CPU time 86.19 seconds
Started Mar 31 03:46:38 PM PDT 24
Finished Mar 31 03:48:05 PM PDT 24
Peak memory 695664 kb
Host smart-490bce4c-d4e3-4a5a-82d6-d0a67100c29c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134000687 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_tx.3134000687
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.2757855634
Short name T797
Test name
Test status
Simulation time 3547812557 ps
CPU time 2.41 seconds
Started Mar 31 03:46:26 PM PDT 24
Finished Mar 31 03:46:28 PM PDT 24
Peak memory 203888 kb
Host smart-b5b84ff9-d802-4274-82d0-b279ec08acfd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757855634 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_hrst.2757855634
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.1395101936
Short name T323
Test name
Test status
Simulation time 17528365650 ps
CPU time 5.32 seconds
Started Mar 31 03:46:29 PM PDT 24
Finished Mar 31 03:46:35 PM PDT 24
Peak memory 214788 kb
Host smart-703e203f-0b92-4662-aa72-ce9411858acf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395101936 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_intr_smoke.1395101936
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.3765100834
Short name T619
Test name
Test status
Simulation time 7792346578 ps
CPU time 16.2 seconds
Started Mar 31 03:46:27 PM PDT 24
Finished Mar 31 03:46:43 PM PDT 24
Peak memory 203884 kb
Host smart-b459ea1d-130f-48b3-8911-b64b4ca05371
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765100834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_smoke.3765100834
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.3041605767
Short name T463
Test name
Test status
Simulation time 408211648 ps
CPU time 6.35 seconds
Started Mar 31 03:46:29 PM PDT 24
Finished Mar 31 03:46:36 PM PDT 24
Peak memory 204300 kb
Host smart-178947d4-9393-42b8-9846-f375fc298c98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041605767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.3041605767
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.3638870097
Short name T74
Test name
Test status
Simulation time 5504021976 ps
CPU time 155.62 seconds
Started Mar 31 03:46:32 PM PDT 24
Finished Mar 31 03:49:08 PM PDT 24
Peak memory 1440284 kb
Host smart-ccedfbc6-3be9-40ae-83ab-5d8790b7c37e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638870097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_
target_stretch.3638870097
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.607533586
Short name T609
Test name
Test status
Simulation time 1242021035 ps
CPU time 6.51 seconds
Started Mar 31 03:46:29 PM PDT 24
Finished Mar 31 03:46:35 PM PDT 24
Peak memory 203892 kb
Host smart-85317e81-a231-4e03-8511-2cd836e0e2fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607533586 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_timeout.607533586
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_alert_test.2356262732
Short name T292
Test name
Test status
Simulation time 16077213 ps
CPU time 0.59 seconds
Started Mar 31 03:46:38 PM PDT 24
Finished Mar 31 03:46:39 PM PDT 24
Peak memory 203544 kb
Host smart-dbf0d331-ee9c-498d-bcac-7ff7e0c11878
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356262732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.2356262732
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.565467712
Short name T453
Test name
Test status
Simulation time 756511207 ps
CPU time 1.48 seconds
Started Mar 31 03:46:28 PM PDT 24
Finished Mar 31 03:46:30 PM PDT 24
Peak memory 212040 kb
Host smart-acc3a612-a88f-43ee-95e4-145507eb564d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565467712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.565467712
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.4244793380
Short name T579
Test name
Test status
Simulation time 258989026 ps
CPU time 5.96 seconds
Started Mar 31 03:46:38 PM PDT 24
Finished Mar 31 03:46:44 PM PDT 24
Peak memory 257528 kb
Host smart-034b3d23-e0c9-4ec9-b839-83f8067100fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244793380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp
ty.4244793380
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.1479817072
Short name T841
Test name
Test status
Simulation time 1927976883 ps
CPU time 58.53 seconds
Started Mar 31 03:46:29 PM PDT 24
Finished Mar 31 03:47:27 PM PDT 24
Peak memory 661792 kb
Host smart-0279cbff-2946-4510-8434-a7c28ab14b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479817072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.1479817072
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.2339661000
Short name T542
Test name
Test status
Simulation time 11824915556 ps
CPU time 45.13 seconds
Started Mar 31 03:46:29 PM PDT 24
Finished Mar 31 03:47:14 PM PDT 24
Peak memory 504296 kb
Host smart-0949498a-232e-4d24-8b9d-4ca9767e0355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339661000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.2339661000
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.867260536
Short name T329
Test name
Test status
Simulation time 610909012 ps
CPU time 0.95 seconds
Started Mar 31 03:46:29 PM PDT 24
Finished Mar 31 03:46:30 PM PDT 24
Peak memory 203644 kb
Host smart-d0e7136b-e607-46b7-9573-f2282ed80d9a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867260536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_fm
t.867260536
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.3537501437
Short name T585
Test name
Test status
Simulation time 229066597 ps
CPU time 4.02 seconds
Started Mar 31 03:46:32 PM PDT 24
Finished Mar 31 03:46:36 PM PDT 24
Peak memory 226956 kb
Host smart-68eee2e0-cd5c-4561-b54b-ca27d198b88d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537501437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx
.3537501437
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.2463586400
Short name T998
Test name
Test status
Simulation time 385325129 ps
CPU time 15.14 seconds
Started Mar 31 03:46:35 PM PDT 24
Finished Mar 31 03:46:50 PM PDT 24
Peak memory 203892 kb
Host smart-656f41d1-c907-417c-85fc-f73526e417f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463586400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.2463586400
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.4199639731
Short name T421
Test name
Test status
Simulation time 5779611336 ps
CPU time 27.94 seconds
Started Mar 31 03:46:33 PM PDT 24
Finished Mar 31 03:47:01 PM PDT 24
Peak memory 414300 kb
Host smart-638db815-faca-4201-a9cc-24ee963c9032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199639731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.4199639731
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_override.4155824341
Short name T371
Test name
Test status
Simulation time 26785958 ps
CPU time 0.65 seconds
Started Mar 31 03:46:28 PM PDT 24
Finished Mar 31 03:46:29 PM PDT 24
Peak memory 203612 kb
Host smart-9463378a-da46-4b85-a4c8-7abb6cfb3a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155824341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.4155824341
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.3916322733
Short name T774
Test name
Test status
Simulation time 6480690687 ps
CPU time 100.43 seconds
Started Mar 31 03:46:27 PM PDT 24
Finished Mar 31 03:48:08 PM PDT 24
Peak memory 604340 kb
Host smart-d2ce93e2-6466-446e-b84f-686b7182855b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916322733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.3916322733
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.3717474104
Short name T891
Test name
Test status
Simulation time 28803859055 ps
CPU time 31.4 seconds
Started Mar 31 03:46:29 PM PDT 24
Finished Mar 31 03:47:00 PM PDT 24
Peak memory 399884 kb
Host smart-28913fad-2d46-478a-b7f3-9270dd3db884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717474104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.3717474104
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.2989496151
Short name T997
Test name
Test status
Simulation time 2071751564 ps
CPU time 3.03 seconds
Started Mar 31 03:46:35 PM PDT 24
Finished Mar 31 03:46:38 PM PDT 24
Peak memory 203800 kb
Host smart-99c4709f-dcc7-417d-acd9-c9149ed27465
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989496151 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.2989496151
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.3436621111
Short name T1008
Test name
Test status
Simulation time 10035738165 ps
CPU time 72.68 seconds
Started Mar 31 03:46:32 PM PDT 24
Finished Mar 31 03:47:44 PM PDT 24
Peak memory 578372 kb
Host smart-857627b6-017a-44b0-b5ea-3fad518eced5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436621111 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.3436621111
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.133588245
Short name T350
Test name
Test status
Simulation time 10290712841 ps
CPU time 46.45 seconds
Started Mar 31 03:46:36 PM PDT 24
Finished Mar 31 03:47:22 PM PDT 24
Peak memory 495484 kb
Host smart-81fae02f-4199-4c32-bf98-15f93d33269b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133588245 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.i2c_target_fifo_reset_tx.133588245
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.957100132
Short name T1192
Test name
Test status
Simulation time 3484111270 ps
CPU time 2.34 seconds
Started Mar 31 03:46:35 PM PDT 24
Finished Mar 31 03:46:37 PM PDT 24
Peak memory 203836 kb
Host smart-6a2e708e-63c7-4251-b2ba-1f80a12de5f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957100132 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 31.i2c_target_hrst.957100132
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.1268383541
Short name T471
Test name
Test status
Simulation time 1036489106 ps
CPU time 5.17 seconds
Started Mar 31 03:46:34 PM PDT 24
Finished Mar 31 03:46:39 PM PDT 24
Peak memory 214260 kb
Host smart-77840bdf-5830-4b68-8e68-bb181a2ab4c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268383541 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.1268383541
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.3076720172
Short name T295
Test name
Test status
Simulation time 6222584844 ps
CPU time 17.23 seconds
Started Mar 31 03:46:33 PM PDT 24
Finished Mar 31 03:46:56 PM PDT 24
Peak memory 203796 kb
Host smart-d3bdfacf-5f22-48a4-838c-edbbaf232f8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076720172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_smoke.3076720172
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.1960370058
Short name T576
Test name
Test status
Simulation time 1398533795 ps
CPU time 61.49 seconds
Started Mar 31 03:46:33 PM PDT 24
Finished Mar 31 03:47:35 PM PDT 24
Peak memory 206116 kb
Host smart-1546963d-12fd-4f87-a510-5dd07c3e6ea2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960370058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_rd.1960370058
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.2730131651
Short name T695
Test name
Test status
Simulation time 14257584322 ps
CPU time 8.83 seconds
Started Mar 31 03:46:33 PM PDT 24
Finished Mar 31 03:46:42 PM PDT 24
Peak memory 203864 kb
Host smart-69a08ac8-2442-4a2e-be4b-544853101422
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730131651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.2730131651
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.2173415387
Short name T1005
Test name
Test status
Simulation time 24761493822 ps
CPU time 1679.68 seconds
Started Mar 31 03:46:33 PM PDT 24
Finished Mar 31 04:14:33 PM PDT 24
Peak memory 6131212 kb
Host smart-2bf1ec1b-fd55-45c5-900f-3187a5860c12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173415387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_
target_stretch.2173415387
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.4258561391
Short name T250
Test name
Test status
Simulation time 1454672021 ps
CPU time 7.05 seconds
Started Mar 31 03:46:34 PM PDT 24
Finished Mar 31 03:46:41 PM PDT 24
Peak memory 217016 kb
Host smart-f40c3c0d-ce7b-4967-ac36-be61da65ac94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258561391 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_timeout.4258561391
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_alert_test.3432443639
Short name T720
Test name
Test status
Simulation time 23666608 ps
CPU time 0.61 seconds
Started Mar 31 03:46:46 PM PDT 24
Finished Mar 31 03:46:47 PM PDT 24
Peak memory 203696 kb
Host smart-26338c72-2589-40b7-80e9-90efd1cf6d44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432443639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.3432443639
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.1035690125
Short name T666
Test name
Test status
Simulation time 61503117 ps
CPU time 1.07 seconds
Started Mar 31 03:46:43 PM PDT 24
Finished Mar 31 03:46:45 PM PDT 24
Peak memory 211944 kb
Host smart-1b07a0e2-b235-4d42-9883-9b8f4c876a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035690125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.1035690125
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.686513116
Short name T859
Test name
Test status
Simulation time 387570897 ps
CPU time 3.74 seconds
Started Mar 31 03:46:33 PM PDT 24
Finished Mar 31 03:46:37 PM PDT 24
Peak memory 235084 kb
Host smart-1a789f67-541b-4095-98e7-a89d9d401c86
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686513116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_empt
y.686513116
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.2843682650
Short name T938
Test name
Test status
Simulation time 5988505372 ps
CPU time 36 seconds
Started Mar 31 03:46:34 PM PDT 24
Finished Mar 31 03:47:11 PM PDT 24
Peak memory 398236 kb
Host smart-9ac1d456-94d9-4461-b38a-b0dde009c24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843682650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.2843682650
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.2680043083
Short name T778
Test name
Test status
Simulation time 12843505937 ps
CPU time 38.12 seconds
Started Mar 31 03:46:37 PM PDT 24
Finished Mar 31 03:47:15 PM PDT 24
Peak memory 524928 kb
Host smart-4161a701-ec0f-47a6-a4ea-fde0f1c66f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680043083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.2680043083
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.10417792
Short name T1163
Test name
Test status
Simulation time 555826007 ps
CPU time 1.07 seconds
Started Mar 31 03:46:33 PM PDT 24
Finished Mar 31 03:46:35 PM PDT 24
Peak memory 203704 kb
Host smart-539a9623-78c4-4277-ba25-f32d8b37bce1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10417792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_fmt
.10417792
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.3003986426
Short name T702
Test name
Test status
Simulation time 569931044 ps
CPU time 2.74 seconds
Started Mar 31 03:46:36 PM PDT 24
Finished Mar 31 03:46:40 PM PDT 24
Peak memory 203812 kb
Host smart-5883939c-23da-4556-aae0-1bd31d8da0f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003986426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx
.3003986426
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.2310631803
Short name T519
Test name
Test status
Simulation time 17127386850 ps
CPU time 133.82 seconds
Started Mar 31 03:46:33 PM PDT 24
Finished Mar 31 03:48:47 PM PDT 24
Peak memory 1228600 kb
Host smart-ebb95b36-7f7a-4386-b10b-7c58f6cffc5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310631803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.2310631803
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.450878038
Short name T352
Test name
Test status
Simulation time 1318361490 ps
CPU time 5.45 seconds
Started Mar 31 03:46:40 PM PDT 24
Finished Mar 31 03:46:45 PM PDT 24
Peak memory 203800 kb
Host smart-b07ad987-bbe6-4a7e-b6cb-3b8b88b0b230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450878038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.450878038
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.1275177819
Short name T333
Test name
Test status
Simulation time 2920541370 ps
CPU time 72.43 seconds
Started Mar 31 03:46:40 PM PDT 24
Finished Mar 31 03:47:52 PM PDT 24
Peak memory 365696 kb
Host smart-58859fd5-c254-4200-bf38-5b1c14698f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275177819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.1275177819
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/32.i2c_host_override.4153482098
Short name T848
Test name
Test status
Simulation time 53129764 ps
CPU time 0.67 seconds
Started Mar 31 03:46:45 PM PDT 24
Finished Mar 31 03:46:46 PM PDT 24
Peak memory 203340 kb
Host smart-cc014918-d2f9-4177-a891-d0494674f761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153482098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.4153482098
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.3273488328
Short name T483
Test name
Test status
Simulation time 1064056368 ps
CPU time 14.83 seconds
Started Mar 31 03:46:35 PM PDT 24
Finished Mar 31 03:46:50 PM PDT 24
Peak memory 284052 kb
Host smart-5539ed30-5067-4b34-b8e8-22e68100bc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273488328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.3273488328
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.2182898895
Short name T955
Test name
Test status
Simulation time 1460634676 ps
CPU time 30.95 seconds
Started Mar 31 03:46:33 PM PDT 24
Finished Mar 31 03:47:04 PM PDT 24
Peak memory 381880 kb
Host smart-ebf99c6b-59a4-4447-891a-35acc16ed36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182898895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.2182898895
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stress_all.1708879105
Short name T710
Test name
Test status
Simulation time 7729202035 ps
CPU time 484.21 seconds
Started Mar 31 03:46:33 PM PDT 24
Finished Mar 31 03:54:38 PM PDT 24
Peak memory 1100596 kb
Host smart-f805b98f-91c9-4cbb-9168-67c6288900eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708879105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stress_all.1708879105
Directory /workspace/32.i2c_host_stress_all/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.1293989600
Short name T1211
Test name
Test status
Simulation time 629029916 ps
CPU time 2.81 seconds
Started Mar 31 03:46:38 PM PDT 24
Finished Mar 31 03:46:41 PM PDT 24
Peak memory 203852 kb
Host smart-b44a7e8c-8cb4-4265-be9f-14b4160900bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293989600 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.1293989600
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.1069531153
Short name T711
Test name
Test status
Simulation time 10193946163 ps
CPU time 5.18 seconds
Started Mar 31 03:46:39 PM PDT 24
Finished Mar 31 03:46:44 PM PDT 24
Peak memory 221788 kb
Host smart-7aea45cf-3495-4472-81e2-60300e3fc1ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069531153 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_fifo_reset_acq.1069531153
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.2067540235
Short name T1006
Test name
Test status
Simulation time 10070935111 ps
CPU time 79.95 seconds
Started Mar 31 03:46:39 PM PDT 24
Finished Mar 31 03:47:59 PM PDT 24
Peak memory 658652 kb
Host smart-5591ba47-c1ac-40b3-af9a-6cf2f6a30a06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067540235 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.2067540235
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.3173157238
Short name T440
Test name
Test status
Simulation time 1403491616 ps
CPU time 2.25 seconds
Started Mar 31 03:46:39 PM PDT 24
Finished Mar 31 03:46:41 PM PDT 24
Peak memory 203804 kb
Host smart-8e5b234e-ab0b-4986-9092-dc66904e0a3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173157238 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_hrst.3173157238
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.1022971659
Short name T389
Test name
Test status
Simulation time 1186580191 ps
CPU time 6.02 seconds
Started Mar 31 03:46:43 PM PDT 24
Finished Mar 31 03:46:49 PM PDT 24
Peak memory 203820 kb
Host smart-ffd3bbc4-73fd-4dd9-a65f-52bcc69cda75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022971659 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_intr_smoke.1022971659
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.1203171115
Short name T701
Test name
Test status
Simulation time 4145775596 ps
CPU time 31.26 seconds
Started Mar 31 03:46:36 PM PDT 24
Finished Mar 31 03:47:07 PM PDT 24
Peak memory 203904 kb
Host smart-b7f73254-30a0-4283-9dc6-a0b4a9c762e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203171115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_smoke.1203171115
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.2361405506
Short name T719
Test name
Test status
Simulation time 2493468855 ps
CPU time 12.27 seconds
Started Mar 31 03:46:46 PM PDT 24
Finished Mar 31 03:46:59 PM PDT 24
Peak memory 206132 kb
Host smart-46438cb8-00cf-403c-8213-fb5c5591b003
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361405506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.2361405506
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.1371097389
Short name T119
Test name
Test status
Simulation time 17415125566 ps
CPU time 10.61 seconds
Started Mar 31 03:46:33 PM PDT 24
Finished Mar 31 03:46:44 PM PDT 24
Peak memory 203804 kb
Host smart-3f152f95-77a7-410e-b9de-ad4cfeb3d65a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371097389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_wr.1371097389
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.3583445751
Short name T818
Test name
Test status
Simulation time 36879100205 ps
CPU time 370.15 seconds
Started Mar 31 03:46:37 PM PDT 24
Finished Mar 31 03:52:47 PM PDT 24
Peak memory 1233316 kb
Host smart-1b999ada-54c6-4380-ba5e-8dea8f495e4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583445751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_
target_stretch.3583445751
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.2073307265
Short name T524
Test name
Test status
Simulation time 1484964132 ps
CPU time 7.77 seconds
Started Mar 31 03:46:40 PM PDT 24
Finished Mar 31 03:46:48 PM PDT 24
Peak memory 219072 kb
Host smart-afbf5e18-1703-4096-8f0e-3a39a990b10c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073307265 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.2073307265
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_alert_test.1654352728
Short name T1177
Test name
Test status
Simulation time 15080630 ps
CPU time 0.61 seconds
Started Mar 31 03:46:42 PM PDT 24
Finished Mar 31 03:46:43 PM PDT 24
Peak memory 203696 kb
Host smart-017ab12c-ffa0-49c9-9c31-e0127a022cb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654352728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.1654352728
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.630293730
Short name T43
Test name
Test status
Simulation time 169799098 ps
CPU time 1.25 seconds
Started Mar 31 03:46:39 PM PDT 24
Finished Mar 31 03:46:40 PM PDT 24
Peak memory 212016 kb
Host smart-6013dc2f-5724-4ad7-bb34-2818c88d8e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630293730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.630293730
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.3500570204
Short name T304
Test name
Test status
Simulation time 387581396 ps
CPU time 8.85 seconds
Started Mar 31 03:46:36 PM PDT 24
Finished Mar 31 03:46:46 PM PDT 24
Peak memory 287316 kb
Host smart-8e50d783-4b19-4f53-888f-431c7964d2ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500570204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.3500570204
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.3472287361
Short name T537
Test name
Test status
Simulation time 7652133876 ps
CPU time 48.92 seconds
Started Mar 31 03:46:39 PM PDT 24
Finished Mar 31 03:47:28 PM PDT 24
Peak memory 505668 kb
Host smart-6c8a582e-ab98-48cd-9ee3-4445c6ce7cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472287361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.3472287361
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.2287557328
Short name T1026
Test name
Test status
Simulation time 1153557231 ps
CPU time 33.06 seconds
Started Mar 31 03:46:39 PM PDT 24
Finished Mar 31 03:47:12 PM PDT 24
Peak memory 448492 kb
Host smart-e4c03a91-6b39-4a39-90bc-2901057d29c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287557328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.2287557328
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.1116647323
Short name T686
Test name
Test status
Simulation time 287318821 ps
CPU time 1.17 seconds
Started Mar 31 03:46:37 PM PDT 24
Finished Mar 31 03:46:39 PM PDT 24
Peak memory 203780 kb
Host smart-faf1ac62-af5b-4e52-98fc-a6dc27cba155
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116647323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_f
mt.1116647323
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.4224945629
Short name T198
Test name
Test status
Simulation time 112853408 ps
CPU time 5.77 seconds
Started Mar 31 03:46:41 PM PDT 24
Finished Mar 31 03:46:47 PM PDT 24
Peak memory 218140 kb
Host smart-087f402f-b179-44cb-8fff-6ffe285b0957
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224945629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.4224945629
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.3864358863
Short name T1045
Test name
Test status
Simulation time 12860014242 ps
CPU time 76.82 seconds
Started Mar 31 03:46:37 PM PDT 24
Finished Mar 31 03:47:54 PM PDT 24
Peak memory 940164 kb
Host smart-58a1a468-4ed5-4850-b172-f099997b8569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864358863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.3864358863
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.1031824515
Short name T218
Test name
Test status
Simulation time 1609254597 ps
CPU time 4.33 seconds
Started Mar 31 03:46:45 PM PDT 24
Finished Mar 31 03:46:50 PM PDT 24
Peak memory 203836 kb
Host smart-563f18dd-8eae-47d5-a200-3e1dd103a24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031824515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.1031824515
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.1872276256
Short name T990
Test name
Test status
Simulation time 5185285861 ps
CPU time 21.55 seconds
Started Mar 31 03:46:55 PM PDT 24
Finished Mar 31 03:47:16 PM PDT 24
Peak memory 328548 kb
Host smart-cde32f8d-a81a-4957-be97-a810f2c615b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872276256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.1872276256
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_perf.875653428
Short name T744
Test name
Test status
Simulation time 4891719243 ps
CPU time 174.17 seconds
Started Mar 31 03:46:38 PM PDT 24
Finished Mar 31 03:49:32 PM PDT 24
Peak memory 801560 kb
Host smart-c05315ce-7759-4586-9b93-11d3a5e64c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875653428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.875653428
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.4055052003
Short name T847
Test name
Test status
Simulation time 723246183 ps
CPU time 11.44 seconds
Started Mar 31 03:46:37 PM PDT 24
Finished Mar 31 03:46:49 PM PDT 24
Peak memory 252588 kb
Host smart-45d6e65d-e85d-4497-8be6-a3abb476a29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055052003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.4055052003
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.1610567173
Short name T549
Test name
Test status
Simulation time 1220463656 ps
CPU time 5.23 seconds
Started Mar 31 03:46:45 PM PDT 24
Finished Mar 31 03:46:50 PM PDT 24
Peak memory 204248 kb
Host smart-9d7748be-3d1b-45de-b52b-0f6c7e0d5ed5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610567173 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.1610567173
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.2491163815
Short name T945
Test name
Test status
Simulation time 10120748894 ps
CPU time 86.21 seconds
Started Mar 31 03:46:48 PM PDT 24
Finished Mar 31 03:48:15 PM PDT 24
Peak memory 615396 kb
Host smart-7a7fb121-2f2e-4df8-b014-6d9fe2f4b610
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491163815 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_reset_acq.2491163815
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.3219260829
Short name T897
Test name
Test status
Simulation time 10235696153 ps
CPU time 16.85 seconds
Started Mar 31 03:46:54 PM PDT 24
Finished Mar 31 03:47:10 PM PDT 24
Peak memory 330648 kb
Host smart-5d4dcce6-9ff0-4fee-a3df-9c508e01e2a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219260829 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.3219260829
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.3702777211
Short name T667
Test name
Test status
Simulation time 1939862018 ps
CPU time 2.35 seconds
Started Mar 31 03:46:42 PM PDT 24
Finished Mar 31 03:46:45 PM PDT 24
Peak memory 203824 kb
Host smart-0b3e35d8-c544-42c7-ba3b-88c729cffebd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702777211 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_hrst.3702777211
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.3203008104
Short name T399
Test name
Test status
Simulation time 3789649277 ps
CPU time 5.49 seconds
Started Mar 31 03:46:46 PM PDT 24
Finished Mar 31 03:46:52 PM PDT 24
Peak memory 203900 kb
Host smart-0d7f98ce-dae9-4418-8928-4101541e82ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203008104 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.3203008104
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.1066403646
Short name T851
Test name
Test status
Simulation time 793207863 ps
CPU time 28.32 seconds
Started Mar 31 03:46:38 PM PDT 24
Finished Mar 31 03:47:06 PM PDT 24
Peak memory 203836 kb
Host smart-44c587f4-8943-4ae7-aed2-362e7203af58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066403646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta
rget_smoke.1066403646
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.3094845864
Short name T683
Test name
Test status
Simulation time 16610792406 ps
CPU time 26.8 seconds
Started Mar 31 03:46:39 PM PDT 24
Finished Mar 31 03:47:06 PM PDT 24
Peak memory 226492 kb
Host smart-895e405a-fec5-403a-a62f-5f2f1de625c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094845864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_rd.3094845864
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.2779634423
Short name T651
Test name
Test status
Simulation time 18053192248 ps
CPU time 99.62 seconds
Started Mar 31 03:46:43 PM PDT 24
Finished Mar 31 03:48:23 PM PDT 24
Peak memory 1189896 kb
Host smart-730c2f4b-5fe8-4dad-b26f-83739e297519
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779634423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stretch.2779634423
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.2493689490
Short name T662
Test name
Test status
Simulation time 4249554277 ps
CPU time 6.49 seconds
Started Mar 31 03:46:43 PM PDT 24
Finished Mar 31 03:46:49 PM PDT 24
Peak memory 203928 kb
Host smart-c3266b53-24f8-4420-bb74-0911eb73e5c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493689490 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.2493689490
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_alert_test.1737904098
Short name T811
Test name
Test status
Simulation time 21192129 ps
CPU time 0.6 seconds
Started Mar 31 03:46:48 PM PDT 24
Finished Mar 31 03:46:49 PM PDT 24
Peak memory 203560 kb
Host smart-a10bb14c-b9c5-4cca-879f-f70c92700094
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737904098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.1737904098
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.1765383868
Short name T45
Test name
Test status
Simulation time 88191332 ps
CPU time 1.72 seconds
Started Mar 31 03:46:51 PM PDT 24
Finished Mar 31 03:46:53 PM PDT 24
Peak memory 212092 kb
Host smart-cc84141c-0f61-43e2-8392-8c5601d7a141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765383868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.1765383868
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.2369854151
Short name T1123
Test name
Test status
Simulation time 1067674805 ps
CPU time 6.4 seconds
Started Mar 31 03:46:46 PM PDT 24
Finished Mar 31 03:46:53 PM PDT 24
Peak memory 259376 kb
Host smart-996c251b-fcb3-4497-8758-2822ba2e97d8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369854151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_emp
ty.2369854151
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.12422931
Short name T547
Test name
Test status
Simulation time 6007805784 ps
CPU time 99.4 seconds
Started Mar 31 03:46:44 PM PDT 24
Finished Mar 31 03:48:23 PM PDT 24
Peak memory 561988 kb
Host smart-131a2bc8-72c1-4434-9af8-4cadf757868f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12422931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.12422931
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.200210261
Short name T482
Test name
Test status
Simulation time 5631470562 ps
CPU time 47.61 seconds
Started Mar 31 03:46:52 PM PDT 24
Finished Mar 31 03:47:39 PM PDT 24
Peak memory 552360 kb
Host smart-6d424c9d-1318-4fff-86b4-b7af98b83914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200210261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.200210261
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.2156184651
Short name T817
Test name
Test status
Simulation time 185067591 ps
CPU time 0.93 seconds
Started Mar 31 03:46:51 PM PDT 24
Finished Mar 31 03:46:52 PM PDT 24
Peak memory 203436 kb
Host smart-c7317a97-b02d-45a6-a3c5-9ba5ea175e04
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156184651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.2156184651
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.3634766945
Short name T934
Test name
Test status
Simulation time 296563736 ps
CPU time 3.29 seconds
Started Mar 31 03:46:48 PM PDT 24
Finished Mar 31 03:46:52 PM PDT 24
Peak memory 203828 kb
Host smart-85c7db91-95e6-4006-a19a-bb02d2566b34
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634766945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx
.3634766945
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.2761028763
Short name T772
Test name
Test status
Simulation time 6185211528 ps
CPU time 135.17 seconds
Started Mar 31 03:46:43 PM PDT 24
Finished Mar 31 03:48:58 PM PDT 24
Peak memory 1178100 kb
Host smart-b5792e70-06a3-44f4-9121-d04de0945a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761028763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.2761028763
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.1929590760
Short name T512
Test name
Test status
Simulation time 882994405 ps
CPU time 4.19 seconds
Started Mar 31 03:46:49 PM PDT 24
Finished Mar 31 03:46:54 PM PDT 24
Peak memory 203836 kb
Host smart-3034c891-65ae-48e0-a293-a00a84c4db2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929590760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.1929590760
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.4113812055
Short name T13
Test name
Test status
Simulation time 23811179571 ps
CPU time 22.09 seconds
Started Mar 31 03:46:50 PM PDT 24
Finished Mar 31 03:47:12 PM PDT 24
Peak memory 360428 kb
Host smart-40437a92-5b60-425d-aecb-abb10e42e1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113812055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.4113812055
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.1301317013
Short name T617
Test name
Test status
Simulation time 27913738 ps
CPU time 0.64 seconds
Started Mar 31 03:46:46 PM PDT 24
Finished Mar 31 03:46:47 PM PDT 24
Peak memory 203592 kb
Host smart-35457352-a2ff-4ed1-8c53-5546bb4be75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301317013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.1301317013
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.3928197511
Short name T1148
Test name
Test status
Simulation time 6326883159 ps
CPU time 90.05 seconds
Started Mar 31 03:46:51 PM PDT 24
Finished Mar 31 03:48:21 PM PDT 24
Peak memory 218232 kb
Host smart-d0add6f9-55e1-4b4d-9483-029c5f0073ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928197511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.3928197511
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.2614825638
Short name T809
Test name
Test status
Simulation time 12366728947 ps
CPU time 83.82 seconds
Started Mar 31 03:46:55 PM PDT 24
Finished Mar 31 03:48:19 PM PDT 24
Peak memory 454672 kb
Host smart-18e402bd-dc25-4322-949c-f71230b69d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614825638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.2614825638
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.2342849569
Short name T800
Test name
Test status
Simulation time 1038403276 ps
CPU time 4.31 seconds
Started Mar 31 03:46:48 PM PDT 24
Finished Mar 31 03:46:53 PM PDT 24
Peak memory 212024 kb
Host smart-9461a2dc-5bb6-4257-989c-600225c2984d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342849569 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.2342849569
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.4086126229
Short name T199
Test name
Test status
Simulation time 10598139439 ps
CPU time 12.42 seconds
Started Mar 31 03:46:54 PM PDT 24
Finished Mar 31 03:47:06 PM PDT 24
Peak memory 285960 kb
Host smart-4782671a-a2e0-4c5e-8c40-8d1518850834
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086126229 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.4086126229
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.2236359230
Short name T67
Test name
Test status
Simulation time 10077346273 ps
CPU time 87.41 seconds
Started Mar 31 03:46:54 PM PDT 24
Finished Mar 31 03:48:21 PM PDT 24
Peak memory 692560 kb
Host smart-40cc55df-5478-46b9-a3c3-ad41aed17655
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236359230 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.2236359230
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.24251600
Short name T553
Test name
Test status
Simulation time 419936889 ps
CPU time 2.51 seconds
Started Mar 31 03:46:50 PM PDT 24
Finished Mar 31 03:46:53 PM PDT 24
Peak memory 203800 kb
Host smart-18b2ca94-16cc-407b-9bc2-0a93b97360d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24251600 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 34.i2c_target_hrst.24251600
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.1757941445
Short name T889
Test name
Test status
Simulation time 733791616 ps
CPU time 4.14 seconds
Started Mar 31 03:46:55 PM PDT 24
Finished Mar 31 03:46:59 PM PDT 24
Peak memory 204972 kb
Host smart-f873b9da-c73b-463c-b839-fb3d33731d4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757941445 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.1757941445
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.2762101127
Short name T663
Test name
Test status
Simulation time 6185051600 ps
CPU time 7.87 seconds
Started Mar 31 03:46:55 PM PDT 24
Finished Mar 31 03:47:03 PM PDT 24
Peak memory 203928 kb
Host smart-55b75f10-99e1-460b-88e8-2c88c973486a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762101127 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.2762101127
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.3584828317
Short name T1017
Test name
Test status
Simulation time 1389549323 ps
CPU time 19.92 seconds
Started Mar 31 03:46:51 PM PDT 24
Finished Mar 31 03:47:11 PM PDT 24
Peak memory 203876 kb
Host smart-9f9f7f14-5912-48ae-812f-36abd25e9260
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584828317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta
rget_smoke.3584828317
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.1618961576
Short name T370
Test name
Test status
Simulation time 413178947 ps
CPU time 11.79 seconds
Started Mar 31 03:46:45 PM PDT 24
Finished Mar 31 03:46:57 PM PDT 24
Peak memory 203868 kb
Host smart-c57f449c-4036-44d2-9409-7dc5156baaae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618961576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_rd.1618961576
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.402940677
Short name T960
Test name
Test status
Simulation time 8397805983 ps
CPU time 36.06 seconds
Started Mar 31 03:46:42 PM PDT 24
Finished Mar 31 03:47:18 PM PDT 24
Peak memory 341212 kb
Host smart-f1630962-5395-442e-87d8-1a11e2e6c981
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402940677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_t
arget_stretch.402940677
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.7651257
Short name T1010
Test name
Test status
Simulation time 2227884404 ps
CPU time 6.06 seconds
Started Mar 31 03:46:55 PM PDT 24
Finished Mar 31 03:47:01 PM PDT 24
Peak memory 208600 kb
Host smart-c17d6266-f191-488b-8eab-2fe520ef055a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7651257 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_timeout.7651257
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_unexp_stop.4038627896
Short name T33
Test name
Test status
Simulation time 3904043850 ps
CPU time 6.92 seconds
Started Mar 31 03:46:50 PM PDT 24
Finished Mar 31 03:46:57 PM PDT 24
Peak memory 212044 kb
Host smart-3365827f-2582-4ab7-a227-a0ffa3a22ec0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038627896 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 34.i2c_target_unexp_stop.4038627896
Directory /workspace/34.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/35.i2c_alert_test.466106619
Short name T102
Test name
Test status
Simulation time 16343352 ps
CPU time 0.62 seconds
Started Mar 31 03:47:04 PM PDT 24
Finished Mar 31 03:47:05 PM PDT 24
Peak memory 203716 kb
Host smart-389cd338-2d48-4e01-bfee-c25664437e5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466106619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.466106619
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.3523434072
Short name T431
Test name
Test status
Simulation time 297866181 ps
CPU time 1.58 seconds
Started Mar 31 03:46:51 PM PDT 24
Finished Mar 31 03:46:53 PM PDT 24
Peak memory 212048 kb
Host smart-03daf10f-c225-4a0c-b3a9-25374858f3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523434072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.3523434072
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.1020912605
Short name T404
Test name
Test status
Simulation time 323155451 ps
CPU time 16.84 seconds
Started Mar 31 03:46:49 PM PDT 24
Finished Mar 31 03:47:06 PM PDT 24
Peak memory 270860 kb
Host smart-cb450ec3-bb7a-4729-a6eb-915d6f80ac8c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020912605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.1020912605
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.2394750391
Short name T852
Test name
Test status
Simulation time 2066908622 ps
CPU time 70.52 seconds
Started Mar 31 03:46:51 PM PDT 24
Finished Mar 31 03:48:02 PM PDT 24
Peak memory 718332 kb
Host smart-664e47b7-6295-4fc0-b2b2-6f9dae2b3294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394750391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.2394750391
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.2237642149
Short name T424
Test name
Test status
Simulation time 4395192854 ps
CPU time 30.23 seconds
Started Mar 31 03:46:52 PM PDT 24
Finished Mar 31 03:47:22 PM PDT 24
Peak memory 475416 kb
Host smart-be936444-5410-44a8-9d42-d20efb807801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237642149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.2237642149
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.3941446151
Short name T203
Test name
Test status
Simulation time 357756306 ps
CPU time 1.21 seconds
Started Mar 31 03:46:52 PM PDT 24
Finished Mar 31 03:46:54 PM PDT 24
Peak memory 203788 kb
Host smart-f6106075-cee7-4617-851c-fb1a84b1d982
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941446151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.3941446151
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.2889785391
Short name T967
Test name
Test status
Simulation time 533668044 ps
CPU time 3.22 seconds
Started Mar 31 03:46:49 PM PDT 24
Finished Mar 31 03:46:53 PM PDT 24
Peak memory 203840 kb
Host smart-65450b8e-8a52-4139-821b-fdc7c0d21f97
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889785391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.2889785391
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.4112909555
Short name T114
Test name
Test status
Simulation time 3509840608 ps
CPU time 104.69 seconds
Started Mar 31 03:46:50 PM PDT 24
Finished Mar 31 03:48:35 PM PDT 24
Peak memory 1042392 kb
Host smart-6970dd42-c9ac-45d0-b1a7-9c60f088efdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112909555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.4112909555
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.3547634828
Short name T501
Test name
Test status
Simulation time 3049990561 ps
CPU time 15.2 seconds
Started Mar 31 03:47:06 PM PDT 24
Finished Mar 31 03:47:22 PM PDT 24
Peak memory 203684 kb
Host smart-dcf86734-2b5c-4fcf-9e94-10a1e48776e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547634828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.3547634828
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.2253986768
Short name T928
Test name
Test status
Simulation time 16699826436 ps
CPU time 22.21 seconds
Started Mar 31 03:47:01 PM PDT 24
Finished Mar 31 03:47:23 PM PDT 24
Peak memory 327584 kb
Host smart-e2b0c9f2-645c-4780-9b2d-67d4e1ab2156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253986768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.2253986768
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/35.i2c_host_override.3751503076
Short name T185
Test name
Test status
Simulation time 62048209 ps
CPU time 0.65 seconds
Started Mar 31 03:46:49 PM PDT 24
Finished Mar 31 03:46:50 PM PDT 24
Peak memory 203628 kb
Host smart-fd039416-56fb-444b-97df-8968d1d27d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751503076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.3751503076
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.1663296348
Short name T674
Test name
Test status
Simulation time 6490721706 ps
CPU time 78.32 seconds
Started Mar 31 03:46:52 PM PDT 24
Finished Mar 31 03:48:11 PM PDT 24
Peak memory 523892 kb
Host smart-87a24996-8b5d-4079-949e-1f489184c503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663296348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.1663296348
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.2942976116
Short name T1124
Test name
Test status
Simulation time 737720895 ps
CPU time 12.84 seconds
Started Mar 31 03:46:50 PM PDT 24
Finished Mar 31 03:47:03 PM PDT 24
Peak memory 293468 kb
Host smart-3b90a54c-1d55-4d22-8157-c73cceb492df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942976116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.2942976116
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stress_all.2088392658
Short name T99
Test name
Test status
Simulation time 17470447002 ps
CPU time 317.7 seconds
Started Mar 31 03:46:48 PM PDT 24
Finished Mar 31 03:52:07 PM PDT 24
Peak memory 1556816 kb
Host smart-10fc72ec-f686-4abf-9bc2-39b5aa7633a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088392658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.2088392658
Directory /workspace/35.i2c_host_stress_all/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.2903694554
Short name T1160
Test name
Test status
Simulation time 2041943367 ps
CPU time 5.23 seconds
Started Mar 31 03:46:58 PM PDT 24
Finished Mar 31 03:47:04 PM PDT 24
Peak memory 204324 kb
Host smart-13e368b0-8596-4170-9746-dcc6d07a89e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903694554 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.2903694554
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.846207709
Short name T61
Test name
Test status
Simulation time 10124229679 ps
CPU time 80.03 seconds
Started Mar 31 03:47:00 PM PDT 24
Finished Mar 31 03:48:20 PM PDT 24
Peak memory 599232 kb
Host smart-feeb346d-c556-464e-bab2-53f774e0fcc4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846207709 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_acq.846207709
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.2153373743
Short name T458
Test name
Test status
Simulation time 10139590113 ps
CPU time 85.19 seconds
Started Mar 31 03:47:06 PM PDT 24
Finished Mar 31 03:48:31 PM PDT 24
Peak memory 683152 kb
Host smart-52d72743-1e40-4376-ab90-59c1129933b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153373743 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_tx.2153373743
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.220307820
Short name T1046
Test name
Test status
Simulation time 975473258 ps
CPU time 2.85 seconds
Started Mar 31 03:46:57 PM PDT 24
Finished Mar 31 03:46:59 PM PDT 24
Peak memory 203772 kb
Host smart-b31b1a7c-4eac-476b-8838-029a54f05ba4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220307820 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 35.i2c_target_hrst.220307820
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.2109903891
Short name T408
Test name
Test status
Simulation time 1485100616 ps
CPU time 4.82 seconds
Started Mar 31 03:46:49 PM PDT 24
Finished Mar 31 03:46:54 PM PDT 24
Peak memory 209064 kb
Host smart-174a9663-f504-4c36-b8bf-f382feccfe35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109903891 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.2109903891
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.3385993432
Short name T1059
Test name
Test status
Simulation time 4581279612 ps
CPU time 5.87 seconds
Started Mar 31 03:47:06 PM PDT 24
Finished Mar 31 03:47:12 PM PDT 24
Peak memory 203800 kb
Host smart-5a7dab66-42e2-492b-8b72-4caea6e12d1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385993432 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.3385993432
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.3444167955
Short name T988
Test name
Test status
Simulation time 2604887146 ps
CPU time 22.89 seconds
Started Mar 31 03:46:49 PM PDT 24
Finished Mar 31 03:47:12 PM PDT 24
Peak memory 203792 kb
Host smart-b393a019-9611-4dc5-8e1a-7dbb973092b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444167955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.3444167955
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.1993726108
Short name T394
Test name
Test status
Simulation time 2666259662 ps
CPU time 28.3 seconds
Started Mar 31 03:46:52 PM PDT 24
Finished Mar 31 03:47:20 PM PDT 24
Peak memory 203964 kb
Host smart-4a382db4-9983-47d8-8df3-d8d959cf1dab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993726108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.1993726108
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.1932613093
Short name T1175
Test name
Test status
Simulation time 1243791178 ps
CPU time 7.08 seconds
Started Mar 31 03:47:05 PM PDT 24
Finished Mar 31 03:47:13 PM PDT 24
Peak memory 219996 kb
Host smart-79eccd6b-cfc3-478f-80ba-a1a2669420bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932613093 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_timeout.1932613093
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_alert_test.2415549012
Short name T1024
Test name
Test status
Simulation time 15296748 ps
CPU time 0.6 seconds
Started Mar 31 03:47:09 PM PDT 24
Finished Mar 31 03:47:09 PM PDT 24
Peak memory 203644 kb
Host smart-30f2a43f-3f56-47b3-8f47-42eb28a981f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415549012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.2415549012
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.334532839
Short name T741
Test name
Test status
Simulation time 67694559 ps
CPU time 1.42 seconds
Started Mar 31 03:47:00 PM PDT 24
Finished Mar 31 03:47:01 PM PDT 24
Peak memory 211848 kb
Host smart-9163c0b4-d528-47bb-8712-9060446ea57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334532839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.334532839
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.591999050
Short name T393
Test name
Test status
Simulation time 380746921 ps
CPU time 9.46 seconds
Started Mar 31 03:46:56 PM PDT 24
Finished Mar 31 03:47:06 PM PDT 24
Peak memory 285008 kb
Host smart-243b0efe-54ab-424e-af68-a63d93048370
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591999050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_empt
y.591999050
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.3330669478
Short name T496
Test name
Test status
Simulation time 10988198093 ps
CPU time 38.22 seconds
Started Mar 31 03:46:55 PM PDT 24
Finished Mar 31 03:47:33 PM PDT 24
Peak memory 386696 kb
Host smart-7c91e14e-1110-421a-bfce-b43b127275ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330669478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.3330669478
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.2877042022
Short name T716
Test name
Test status
Simulation time 1743561539 ps
CPU time 127.4 seconds
Started Mar 31 03:46:56 PM PDT 24
Finished Mar 31 03:49:03 PM PDT 24
Peak memory 631996 kb
Host smart-69414568-8336-46d3-9bf1-47e3beaf56b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877042022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.2877042022
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.3208904303
Short name T1031
Test name
Test status
Simulation time 336813729 ps
CPU time 1.17 seconds
Started Mar 31 03:46:59 PM PDT 24
Finished Mar 31 03:47:00 PM PDT 24
Peak memory 203768 kb
Host smart-efaee237-d5ce-4c10-94b5-61f1b613f3c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208904303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.3208904303
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.3670374461
Short name T328
Test name
Test status
Simulation time 426828876 ps
CPU time 2.52 seconds
Started Mar 31 03:47:04 PM PDT 24
Finished Mar 31 03:47:07 PM PDT 24
Peak memory 203812 kb
Host smart-3e701cbd-c683-4ac6-9673-ad32406715d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670374461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.3670374461
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.3811405902
Short name T300
Test name
Test status
Simulation time 31383499911 ps
CPU time 101.94 seconds
Started Mar 31 03:47:06 PM PDT 24
Finished Mar 31 03:48:48 PM PDT 24
Peak memory 1005804 kb
Host smart-21745244-bb36-4c5e-bd18-523a36c1823f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811405902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.3811405902
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.252100173
Short name T761
Test name
Test status
Simulation time 1894835248 ps
CPU time 19.24 seconds
Started Mar 31 03:47:00 PM PDT 24
Finished Mar 31 03:47:20 PM PDT 24
Peak memory 203824 kb
Host smart-8e2d9c1a-7436-4d3a-85fa-2faf0e73b0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252100173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.252100173
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.427244894
Short name T779
Test name
Test status
Simulation time 3708888562 ps
CPU time 38.12 seconds
Started Mar 31 03:47:00 PM PDT 24
Finished Mar 31 03:47:38 PM PDT 24
Peak memory 456200 kb
Host smart-d4d9d77b-752f-480f-855d-4224edcca621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427244894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.427244894
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_override.4059461937
Short name T268
Test name
Test status
Simulation time 30783229 ps
CPU time 0.68 seconds
Started Mar 31 03:47:10 PM PDT 24
Finished Mar 31 03:47:12 PM PDT 24
Peak memory 203560 kb
Host smart-b181b984-b11f-4900-812b-ad922e0ef430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059461937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.4059461937
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.3103569454
Short name T943
Test name
Test status
Simulation time 2601115304 ps
CPU time 181.36 seconds
Started Mar 31 03:47:07 PM PDT 24
Finished Mar 31 03:50:09 PM PDT 24
Peak memory 814028 kb
Host smart-4ee3558e-ea6c-48e9-9d29-ee47c517d7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103569454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.3103569454
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.1034132801
Short name T1001
Test name
Test status
Simulation time 4198201316 ps
CPU time 51.93 seconds
Started Mar 31 03:47:04 PM PDT 24
Finished Mar 31 03:47:56 PM PDT 24
Peak memory 314464 kb
Host smart-b095d67d-5a53-4545-8ec7-827eaf8a4060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034132801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.1034132801
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.2957533406
Short name T5
Test name
Test status
Simulation time 527901719 ps
CPU time 2.94 seconds
Started Mar 31 03:47:02 PM PDT 24
Finished Mar 31 03:47:05 PM PDT 24
Peak memory 203788 kb
Host smart-69e7a656-84b2-40d6-821d-71708d67893b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957533406 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.2957533406
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.219004159
Short name T842
Test name
Test status
Simulation time 10054633911 ps
CPU time 93.3 seconds
Started Mar 31 03:46:56 PM PDT 24
Finished Mar 31 03:48:29 PM PDT 24
Peak memory 602152 kb
Host smart-704584f6-76ac-434a-b1e0-13c06db7e29e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219004159 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_acq.219004159
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.1420533188
Short name T1007
Test name
Test status
Simulation time 10496374170 ps
CPU time 15.81 seconds
Started Mar 31 03:47:04 PM PDT 24
Finished Mar 31 03:47:20 PM PDT 24
Peak memory 351852 kb
Host smart-458f8717-d6d5-409c-b2a8-77ca7d267966
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420533188 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_tx.1420533188
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.315557954
Short name T335
Test name
Test status
Simulation time 2486714391 ps
CPU time 3.34 seconds
Started Mar 31 03:47:05 PM PDT 24
Finished Mar 31 03:47:08 PM PDT 24
Peak memory 203824 kb
Host smart-aac22e34-167e-4cc2-9f06-e80c41e620b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315557954 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 36.i2c_target_hrst.315557954
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.776993687
Short name T718
Test name
Test status
Simulation time 2679797290 ps
CPU time 3.9 seconds
Started Mar 31 03:46:56 PM PDT 24
Finished Mar 31 03:47:00 PM PDT 24
Peak memory 203900 kb
Host smart-b1f283e5-f555-4335-9156-2f7a328425b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776993687 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_intr_smoke.776993687
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.2333885263
Short name T312
Test name
Test status
Simulation time 2347944129 ps
CPU time 38.87 seconds
Started Mar 31 03:46:57 PM PDT 24
Finished Mar 31 03:47:36 PM PDT 24
Peak memory 203892 kb
Host smart-06b6a0a1-f31c-452e-920c-21d939faf2ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333885263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.2333885263
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.2825683673
Short name T693
Test name
Test status
Simulation time 5832270089 ps
CPU time 62.45 seconds
Started Mar 31 03:47:00 PM PDT 24
Finished Mar 31 03:48:02 PM PDT 24
Peak memory 205492 kb
Host smart-6d1cc879-fda1-4a12-8bb9-6bba88863b33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825683673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_rd.2825683673
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.1502911525
Short name T979
Test name
Test status
Simulation time 11396193616 ps
CPU time 112.24 seconds
Started Mar 31 03:46:55 PM PDT 24
Finished Mar 31 03:48:47 PM PDT 24
Peak memory 1125336 kb
Host smart-90a352df-52a6-4a3d-9ef8-33f02f6a6443
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502911525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stretch.1502911525
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.1926551790
Short name T247
Test name
Test status
Simulation time 1322420469 ps
CPU time 6.94 seconds
Started Mar 31 03:46:57 PM PDT 24
Finished Mar 31 03:47:04 PM PDT 24
Peak memory 211368 kb
Host smart-0c466cd0-9f9b-469c-85c2-c81d06549f42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926551790 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.1926551790
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_alert_test.3664185383
Short name T479
Test name
Test status
Simulation time 47714683 ps
CPU time 0.59 seconds
Started Mar 31 03:47:11 PM PDT 24
Finished Mar 31 03:47:12 PM PDT 24
Peak memory 203592 kb
Host smart-9201b8e6-24be-4301-863c-12c7f8eb2aa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664185383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.3664185383
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.3648337449
Short name T957
Test name
Test status
Simulation time 318894503 ps
CPU time 1.3 seconds
Started Mar 31 03:47:04 PM PDT 24
Finished Mar 31 03:47:05 PM PDT 24
Peak memory 212116 kb
Host smart-92c6a068-65df-4597-8555-f2ab24dece75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648337449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.3648337449
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.871583913
Short name T1193
Test name
Test status
Simulation time 1640827198 ps
CPU time 8.83 seconds
Started Mar 31 03:47:05 PM PDT 24
Finished Mar 31 03:47:14 PM PDT 24
Peak memory 301600 kb
Host smart-a07e4ad2-7ed3-473c-85b6-7e733505ad86
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871583913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_empt
y.871583913
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.2204830094
Short name T784
Test name
Test status
Simulation time 1717879758 ps
CPU time 46.2 seconds
Started Mar 31 03:47:01 PM PDT 24
Finished Mar 31 03:47:48 PM PDT 24
Peak memory 537700 kb
Host smart-1593b1a4-cbce-46bc-b6f1-13f1c5998d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204830094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.2204830094
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.1282233319
Short name T89
Test name
Test status
Simulation time 24227212185 ps
CPU time 41.68 seconds
Started Mar 31 03:47:05 PM PDT 24
Finished Mar 31 03:47:47 PM PDT 24
Peak memory 564988 kb
Host smart-ee3940ef-05d1-4122-824f-aa2d222d1edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282233319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.1282233319
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.1184726049
Short name T665
Test name
Test status
Simulation time 141410335 ps
CPU time 1.08 seconds
Started Mar 31 03:47:08 PM PDT 24
Finished Mar 31 03:47:09 PM PDT 24
Peak memory 203620 kb
Host smart-0817532b-9859-48c7-b483-2bad9cf87b54
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184726049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_f
mt.1184726049
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.2873419928
Short name T694
Test name
Test status
Simulation time 363642268 ps
CPU time 5.49 seconds
Started Mar 31 03:47:06 PM PDT 24
Finished Mar 31 03:47:11 PM PDT 24
Peak memory 237192 kb
Host smart-935da404-25ee-4443-863d-be567adeb4cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873419928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.2873419928
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.2867654757
Short name T8
Test name
Test status
Simulation time 3810881067 ps
CPU time 277.43 seconds
Started Mar 31 03:47:04 PM PDT 24
Finished Mar 31 03:51:41 PM PDT 24
Peak memory 1090560 kb
Host smart-0d2d3aa8-7034-4155-b0a6-d190b4efde3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867654757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.2867654757
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.1309187846
Short name T325
Test name
Test status
Simulation time 1181745747 ps
CPU time 3.5 seconds
Started Mar 31 03:47:04 PM PDT 24
Finished Mar 31 03:47:07 PM PDT 24
Peak memory 203816 kb
Host smart-d232ed7c-a27e-4380-b650-41bd70567da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309187846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.1309187846
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.4208354998
Short name T918
Test name
Test status
Simulation time 3822453903 ps
CPU time 50.3 seconds
Started Mar 31 03:47:02 PM PDT 24
Finished Mar 31 03:47:52 PM PDT 24
Peak memory 363516 kb
Host smart-6155a34d-7a67-4dab-9221-814567618e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208354998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.4208354998
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.1538165098
Short name T751
Test name
Test status
Simulation time 23160032 ps
CPU time 0.63 seconds
Started Mar 31 03:47:02 PM PDT 24
Finished Mar 31 03:47:02 PM PDT 24
Peak memory 203620 kb
Host smart-2523b221-f9e6-457f-b113-11f6d5fb7704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538165098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.1538165098
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.3607604565
Short name T961
Test name
Test status
Simulation time 286519258 ps
CPU time 3.62 seconds
Started Mar 31 03:47:10 PM PDT 24
Finished Mar 31 03:47:15 PM PDT 24
Peak memory 220012 kb
Host smart-63d231b1-142e-4a4a-9cf7-31aec9552223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607604565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.3607604565
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.791529859
Short name T605
Test name
Test status
Simulation time 4189532675 ps
CPU time 57.42 seconds
Started Mar 31 03:47:07 PM PDT 24
Finished Mar 31 03:48:04 PM PDT 24
Peak memory 364648 kb
Host smart-380249da-d8f4-4102-ae25-2a5106a94df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791529859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.791529859
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.3929157340
Short name T177
Test name
Test status
Simulation time 6121610681 ps
CPU time 4.55 seconds
Started Mar 31 03:47:07 PM PDT 24
Finished Mar 31 03:47:12 PM PDT 24
Peak memory 203940 kb
Host smart-92b2431d-7f56-4dbc-b594-2d8b3a1cf88f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929157340 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.3929157340
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.3818731993
Short name T87
Test name
Test status
Simulation time 10251225579 ps
CPU time 26.86 seconds
Started Mar 31 03:47:08 PM PDT 24
Finished Mar 31 03:47:34 PM PDT 24
Peak memory 367160 kb
Host smart-5bfad9ec-ca4c-4d56-a75a-05e42021ab57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818731993 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_fifo_reset_acq.3818731993
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.3126999933
Short name T1189
Test name
Test status
Simulation time 10187016860 ps
CPU time 51 seconds
Started Mar 31 03:47:02 PM PDT 24
Finished Mar 31 03:47:53 PM PDT 24
Peak memory 544292 kb
Host smart-a881b46e-01e2-4085-a5e5-6d65467a311b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126999933 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.3126999933
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.1908885527
Short name T478
Test name
Test status
Simulation time 1483103842 ps
CPU time 2.38 seconds
Started Mar 31 03:47:04 PM PDT 24
Finished Mar 31 03:47:07 PM PDT 24
Peak memory 203856 kb
Host smart-34622277-5b54-4369-b8f6-f3faad31e529
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908885527 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_hrst.1908885527
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.2977504184
Short name T1121
Test name
Test status
Simulation time 1660996310 ps
CPU time 4.12 seconds
Started Mar 31 03:47:09 PM PDT 24
Finished Mar 31 03:47:13 PM PDT 24
Peak memory 204068 kb
Host smart-f5b2588e-bcff-4818-bb02-a4258f5d7abf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977504184 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.2977504184
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.1134832274
Short name T436
Test name
Test status
Simulation time 3998376776 ps
CPU time 40.77 seconds
Started Mar 31 03:47:04 PM PDT 24
Finished Mar 31 03:47:45 PM PDT 24
Peak memory 203868 kb
Host smart-e0b9b69a-5c6e-4fc6-86ee-5aaa60d3d149
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134832274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.1134832274
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.283362719
Short name T1068
Test name
Test status
Simulation time 16351014161 ps
CPU time 13.01 seconds
Started Mar 31 03:47:03 PM PDT 24
Finished Mar 31 03:47:16 PM PDT 24
Peak memory 213604 kb
Host smart-7eb7da89-4cc8-4ce1-b0be-154841fa73e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283362719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c
_target_stress_rd.283362719
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.1517033302
Short name T1027
Test name
Test status
Simulation time 34667892226 ps
CPU time 3317.23 seconds
Started Mar 31 03:47:00 PM PDT 24
Finished Mar 31 04:42:18 PM PDT 24
Peak memory 8191248 kb
Host smart-8501a396-a3a3-4fd5-9969-f2192e42cb33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517033302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stretch.1517033302
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.3571528452
Short name T838
Test name
Test status
Simulation time 7033557658 ps
CPU time 7.97 seconds
Started Mar 31 03:47:05 PM PDT 24
Finished Mar 31 03:47:13 PM PDT 24
Peak memory 220104 kb
Host smart-b7de2907-0bc5-4900-920b-364ca16ef742
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571528452 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_timeout.3571528452
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_alert_test.2569495542
Short name T1132
Test name
Test status
Simulation time 37084948 ps
CPU time 0.64 seconds
Started Mar 31 03:47:07 PM PDT 24
Finished Mar 31 03:47:08 PM PDT 24
Peak memory 203704 kb
Host smart-3a03210c-d42b-429d-bcc8-e59bf64b1418
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569495542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.2569495542
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.2722918859
Short name T390
Test name
Test status
Simulation time 138959908 ps
CPU time 1.69 seconds
Started Mar 31 03:47:08 PM PDT 24
Finished Mar 31 03:47:10 PM PDT 24
Peak memory 212100 kb
Host smart-35c11639-5c7c-4e1b-9a19-071d43183f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722918859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.2722918859
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.3902833312
Short name T550
Test name
Test status
Simulation time 289315161 ps
CPU time 6.6 seconds
Started Mar 31 03:47:07 PM PDT 24
Finished Mar 31 03:47:14 PM PDT 24
Peak memory 263048 kb
Host smart-30116317-90a9-4b51-9df5-d4f95a4ad6ff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902833312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.3902833312
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.1004054247
Short name T517
Test name
Test status
Simulation time 1826326085 ps
CPU time 98.39 seconds
Started Mar 31 03:47:10 PM PDT 24
Finished Mar 31 03:48:48 PM PDT 24
Peak memory 348136 kb
Host smart-1aa47421-2404-4026-b2e5-68340f67dfb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004054247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.1004054247
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.2956308810
Short name T503
Test name
Test status
Simulation time 6191175015 ps
CPU time 51.61 seconds
Started Mar 31 03:47:11 PM PDT 24
Finished Mar 31 03:48:03 PM PDT 24
Peak memory 574812 kb
Host smart-00297bc2-7535-4996-a03f-9590f753176d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956308810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.2956308810
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.1787213111
Short name T812
Test name
Test status
Simulation time 219648376 ps
CPU time 0.95 seconds
Started Mar 31 03:47:05 PM PDT 24
Finished Mar 31 03:47:06 PM PDT 24
Peak memory 203728 kb
Host smart-3505089b-ff08-4644-99e3-66b9218d04d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787213111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.1787213111
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.177853172
Short name T840
Test name
Test status
Simulation time 783262562 ps
CPU time 4.07 seconds
Started Mar 31 03:47:09 PM PDT 24
Finished Mar 31 03:47:13 PM PDT 24
Peak memory 203736 kb
Host smart-66c876c6-540b-42e3-96cc-8473ea7b7b6c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177853172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx.
177853172
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.913295486
Short name T467
Test name
Test status
Simulation time 4244057732 ps
CPU time 135.26 seconds
Started Mar 31 03:47:08 PM PDT 24
Finished Mar 31 03:49:23 PM PDT 24
Peak memory 1228476 kb
Host smart-1902a195-7e91-4a04-a43e-045a907a2970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913295486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.913295486
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.3369467162
Short name T737
Test name
Test status
Simulation time 650826867 ps
CPU time 2.79 seconds
Started Mar 31 03:47:07 PM PDT 24
Finished Mar 31 03:47:09 PM PDT 24
Peak memory 203792 kb
Host smart-d8338e83-960f-4240-a142-c4dc18300ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369467162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.3369467162
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.777713892
Short name T708
Test name
Test status
Simulation time 1368929758 ps
CPU time 23.22 seconds
Started Mar 31 03:47:11 PM PDT 24
Finished Mar 31 03:47:34 PM PDT 24
Peak memory 365856 kb
Host smart-5fd05c18-4ee3-4d58-9203-deffa9f19276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777713892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.777713892
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.3472792320
Short name T527
Test name
Test status
Simulation time 48229996 ps
CPU time 0.62 seconds
Started Mar 31 03:47:08 PM PDT 24
Finished Mar 31 03:47:09 PM PDT 24
Peak memory 203600 kb
Host smart-01819382-5e71-478e-8108-dcd0ef8e3ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472792320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.3472792320
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.3347864394
Short name T1174
Test name
Test status
Simulation time 12536946780 ps
CPU time 1015.05 seconds
Started Mar 31 03:47:08 PM PDT 24
Finished Mar 31 04:04:03 PM PDT 24
Peak memory 3058720 kb
Host smart-6b14292d-bfda-4927-a549-f8849c1d2541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347864394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.3347864394
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.3747677778
Short name T515
Test name
Test status
Simulation time 1462362395 ps
CPU time 85.6 seconds
Started Mar 31 03:47:09 PM PDT 24
Finished Mar 31 03:48:35 PM PDT 24
Peak memory 464016 kb
Host smart-48421b02-4e94-4dc2-8ff5-f5a19c4fc6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747677778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.3747677778
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.2410183024
Short name T454
Test name
Test status
Simulation time 1874950377 ps
CPU time 2.76 seconds
Started Mar 31 03:47:09 PM PDT 24
Finished Mar 31 03:47:12 PM PDT 24
Peak memory 203856 kb
Host smart-54f9e1f0-ee32-4e83-ba85-7a5310d86cc1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410183024 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.2410183024
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.3948130668
Short name T422
Test name
Test status
Simulation time 11206987069 ps
CPU time 6.01 seconds
Started Mar 31 03:47:11 PM PDT 24
Finished Mar 31 03:47:17 PM PDT 24
Peak memory 221560 kb
Host smart-95bedb10-e9aa-4882-8ff6-0711802c05a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948130668 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_fifo_reset_acq.3948130668
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.2938531830
Short name T643
Test name
Test status
Simulation time 10346435127 ps
CPU time 10.5 seconds
Started Mar 31 03:47:08 PM PDT 24
Finished Mar 31 03:47:18 PM PDT 24
Peak memory 286376 kb
Host smart-3d6dbec0-8e3f-4d97-a3aa-802998c03c08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938531830 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.2938531830
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.4048006933
Short name T1210
Test name
Test status
Simulation time 2274046014 ps
CPU time 6.57 seconds
Started Mar 31 03:47:10 PM PDT 24
Finished Mar 31 03:47:16 PM PDT 24
Peak memory 208552 kb
Host smart-efc0d9c8-42cc-4159-b7aa-9fd1ae08f3ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048006933 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_intr_smoke.4048006933
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.2287047978
Short name T1134
Test name
Test status
Simulation time 735737102 ps
CPU time 14.45 seconds
Started Mar 31 03:47:09 PM PDT 24
Finished Mar 31 03:47:24 PM PDT 24
Peak memory 203780 kb
Host smart-fc984efe-e728-4e4c-96ab-8655cafcb996
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287047978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.2287047978
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.1480838587
Short name T316
Test name
Test status
Simulation time 967153966 ps
CPU time 18.73 seconds
Started Mar 31 03:47:07 PM PDT 24
Finished Mar 31 03:47:25 PM PDT 24
Peak memory 203584 kb
Host smart-9047aeb4-21b5-44aa-9935-40c7c77c0d5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480838587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_rd.1480838587
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.98146539
Short name T771
Test name
Test status
Simulation time 16483697988 ps
CPU time 814.64 seconds
Started Mar 31 03:47:06 PM PDT 24
Finished Mar 31 04:00:42 PM PDT 24
Peak memory 4042436 kb
Host smart-dd51abad-50bf-4132-b1c7-f02e83606a44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98146539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_stretch.98146539
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.811211228
Short name T85
Test name
Test status
Simulation time 1538406919 ps
CPU time 7.75 seconds
Started Mar 31 03:47:08 PM PDT 24
Finished Mar 31 03:47:16 PM PDT 24
Peak memory 219972 kb
Host smart-abc528c7-f973-4c2c-8463-7b332fbf0fef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811211228 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_timeout.811211228
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_unexp_stop.3067320113
Short name T1018
Test name
Test status
Simulation time 2002342659 ps
CPU time 5.53 seconds
Started Mar 31 03:47:07 PM PDT 24
Finished Mar 31 03:47:12 PM PDT 24
Peak memory 206184 kb
Host smart-57832b13-8fe3-4580-9ebd-84d992adda9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067320113 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 38.i2c_target_unexp_stop.3067320113
Directory /workspace/38.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/39.i2c_alert_test.1865925752
Short name T103
Test name
Test status
Simulation time 40454556 ps
CPU time 0.58 seconds
Started Mar 31 03:47:12 PM PDT 24
Finished Mar 31 03:47:12 PM PDT 24
Peak memory 203692 kb
Host smart-3ec3b384-edf3-4cf1-b259-4a90adfd3156
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865925752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.1865925752
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.3463583566
Short name T1153
Test name
Test status
Simulation time 285562889 ps
CPU time 1.51 seconds
Started Mar 31 03:47:17 PM PDT 24
Finished Mar 31 03:47:18 PM PDT 24
Peak memory 212008 kb
Host smart-0e721f3d-df4e-4aca-823c-768f0c7a4fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463583566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.3463583566
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.1572165798
Short name T522
Test name
Test status
Simulation time 331922861 ps
CPU time 6.1 seconds
Started Mar 31 03:47:15 PM PDT 24
Finished Mar 31 03:47:22 PM PDT 24
Peak memory 272460 kb
Host smart-e597914e-a9be-4c69-9c9e-8684b0832341
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572165798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_emp
ty.1572165798
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.481317472
Short name T589
Test name
Test status
Simulation time 6802657893 ps
CPU time 49.83 seconds
Started Mar 31 03:47:08 PM PDT 24
Finished Mar 31 03:47:58 PM PDT 24
Peak memory 629132 kb
Host smart-fd54fe86-4248-488c-a918-fcdc458f5485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481317472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.481317472
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.848730214
Short name T993
Test name
Test status
Simulation time 329514680 ps
CPU time 1.13 seconds
Started Mar 31 03:47:10 PM PDT 24
Finished Mar 31 03:47:11 PM PDT 24
Peak memory 203724 kb
Host smart-8d34f259-c721-4b03-8e95-ead5a04b9543
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848730214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_fm
t.848730214
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.2530798488
Short name T92
Test name
Test status
Simulation time 729479672 ps
CPU time 9.35 seconds
Started Mar 31 03:47:20 PM PDT 24
Finished Mar 31 03:47:29 PM PDT 24
Peak memory 203752 kb
Host smart-9610abc2-63bd-48d3-bcc7-8a30e84abf79
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530798488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx
.2530798488
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.3519676286
Short name T742
Test name
Test status
Simulation time 18514079576 ps
CPU time 117.65 seconds
Started Mar 31 03:47:10 PM PDT 24
Finished Mar 31 03:49:07 PM PDT 24
Peak memory 1311268 kb
Host smart-8d5dbd42-851b-415a-a837-c88f5a162361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519676286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.3519676286
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.435079514
Short name T1179
Test name
Test status
Simulation time 1563008744 ps
CPU time 2.94 seconds
Started Mar 31 03:47:19 PM PDT 24
Finished Mar 31 03:47:22 PM PDT 24
Peak memory 203772 kb
Host smart-56740dee-b2cd-4f28-9382-3e41d5da7c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435079514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.435079514
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.2743588368
Short name T437
Test name
Test status
Simulation time 4038225081 ps
CPU time 54.85 seconds
Started Mar 31 03:47:15 PM PDT 24
Finished Mar 31 03:48:11 PM PDT 24
Peak memory 365348 kb
Host smart-c99fa6bf-9795-43ed-8b4c-61241a7c2221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743588368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.2743588368
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.832815603
Short name T182
Test name
Test status
Simulation time 30869414 ps
CPU time 0.72 seconds
Started Mar 31 03:47:07 PM PDT 24
Finished Mar 31 03:47:08 PM PDT 24
Peak memory 203580 kb
Host smart-00bba56f-1a7b-4616-b52b-58e5779496b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832815603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.832815603
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.2420477032
Short name T871
Test name
Test status
Simulation time 8696625182 ps
CPU time 49.23 seconds
Started Mar 31 03:47:17 PM PDT 24
Finished Mar 31 03:48:07 PM PDT 24
Peak memory 560436 kb
Host smart-72165825-e2d5-423e-aff2-bfc64b9245e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420477032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.2420477032
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.2263562792
Short name T1149
Test name
Test status
Simulation time 1945337672 ps
CPU time 24.75 seconds
Started Mar 31 03:47:08 PM PDT 24
Finished Mar 31 03:47:32 PM PDT 24
Peak memory 340812 kb
Host smart-bd204698-068e-423b-be47-8cbbc7f3cb07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263562792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.2263562792
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stress_all.134942444
Short name T631
Test name
Test status
Simulation time 32438495625 ps
CPU time 321.33 seconds
Started Mar 31 03:47:15 PM PDT 24
Finished Mar 31 03:52:37 PM PDT 24
Peak memory 1543764 kb
Host smart-688dd36d-6c69-4626-a547-9ddfb6a5a19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134942444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stress_all.134942444
Directory /workspace/39.i2c_host_stress_all/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.4027809616
Short name T978
Test name
Test status
Simulation time 1715985938 ps
CPU time 4.16 seconds
Started Mar 31 03:47:17 PM PDT 24
Finished Mar 31 03:47:22 PM PDT 24
Peak memory 212008 kb
Host smart-a0e694aa-f016-4a01-8a98-65117b34bfe0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027809616 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.4027809616
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.2828733975
Short name T618
Test name
Test status
Simulation time 10053039369 ps
CPU time 30.25 seconds
Started Mar 31 03:47:12 PM PDT 24
Finished Mar 31 03:47:42 PM PDT 24
Peak memory 408476 kb
Host smart-b7f53119-fcd6-4a93-90c5-03ab532e4316
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828733975 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.2828733975
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.1577351164
Short name T768
Test name
Test status
Simulation time 10121230805 ps
CPU time 14.35 seconds
Started Mar 31 03:47:16 PM PDT 24
Finished Mar 31 03:47:30 PM PDT 24
Peak memory 305964 kb
Host smart-456cbb45-0394-4636-b441-fd5cd9012037
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577351164 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_tx.1577351164
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.3974896810
Short name T40
Test name
Test status
Simulation time 792026750 ps
CPU time 2.33 seconds
Started Mar 31 03:47:15 PM PDT 24
Finished Mar 31 03:47:18 PM PDT 24
Peak memory 203784 kb
Host smart-a03dfd86-49f7-4bb1-88e1-cc0faeebb4fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974896810 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_hrst.3974896810
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.2498812512
Short name T863
Test name
Test status
Simulation time 1500488655 ps
CPU time 7.75 seconds
Started Mar 31 03:47:13 PM PDT 24
Finished Mar 31 03:47:21 PM PDT 24
Peak memory 212060 kb
Host smart-06a1c3cb-5e27-400b-8293-deba850d7813
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498812512 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.2498812512
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.266090132
Short name T318
Test name
Test status
Simulation time 7584780278 ps
CPU time 5.46 seconds
Started Mar 31 03:47:16 PM PDT 24
Finished Mar 31 03:47:22 PM PDT 24
Peak memory 203840 kb
Host smart-fd3a7f69-e2dd-4646-a016-90d26d519c37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266090132 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.266090132
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.2513738714
Short name T320
Test name
Test status
Simulation time 7476044340 ps
CPU time 13.9 seconds
Started Mar 31 03:47:15 PM PDT 24
Finished Mar 31 03:47:29 PM PDT 24
Peak memory 203900 kb
Host smart-d44d7092-663d-4420-8c77-7f4fd5237c60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513738714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.2513738714
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.2841702340
Short name T669
Test name
Test status
Simulation time 1377532737 ps
CPU time 57.32 seconds
Started Mar 31 03:47:13 PM PDT 24
Finished Mar 31 03:48:10 PM PDT 24
Peak memory 205312 kb
Host smart-1b217a5f-51c4-4309-89db-e70d9b51c737
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841702340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_rd.2841702340
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.970156882
Short name T1019
Test name
Test status
Simulation time 11756000706 ps
CPU time 6.67 seconds
Started Mar 31 03:47:17 PM PDT 24
Finished Mar 31 03:47:25 PM PDT 24
Peak memory 203792 kb
Host smart-6adce747-676b-4f97-aab6-cc567a5ba105
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970156882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c
_target_stress_wr.970156882
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.3008607005
Short name T692
Test name
Test status
Simulation time 12219400209 ps
CPU time 1036.63 seconds
Started Mar 31 03:47:18 PM PDT 24
Finished Mar 31 04:04:36 PM PDT 24
Peak memory 2430212 kb
Host smart-6371d2db-dcc5-4714-b8f0-b017c6f80345
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008607005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_
target_stretch.3008607005
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.1249881210
Short name T1126
Test name
Test status
Simulation time 1907521006 ps
CPU time 7.8 seconds
Started Mar 31 03:47:12 PM PDT 24
Finished Mar 31 03:47:20 PM PDT 24
Peak memory 219804 kb
Host smart-4785381e-fdca-49d1-a953-affda6f56065
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249881210 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_timeout.1249881210
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_alert_test.471758867
Short name T1127
Test name
Test status
Simulation time 17700367 ps
CPU time 0.68 seconds
Started Mar 31 03:44:06 PM PDT 24
Finished Mar 31 03:44:07 PM PDT 24
Peak memory 203676 kb
Host smart-7c80d289-13ea-49b9-89bf-336427341a48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471758867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.471758867
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.4082094023
Short name T999
Test name
Test status
Simulation time 80083216 ps
CPU time 1.31 seconds
Started Mar 31 03:44:02 PM PDT 24
Finished Mar 31 03:44:03 PM PDT 24
Peak memory 212128 kb
Host smart-cf2992bd-0ca7-4ad1-bd96-8fdd359a6d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082094023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.4082094023
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.3441693039
Short name T533
Test name
Test status
Simulation time 752485867 ps
CPU time 4.57 seconds
Started Mar 31 03:44:06 PM PDT 24
Finished Mar 31 03:44:10 PM PDT 24
Peak memory 241156 kb
Host smart-d9ef37e3-118a-4709-9e5f-21c2c6ccadf4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441693039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empt
y.3441693039
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.564209135
Short name T893
Test name
Test status
Simulation time 23554216088 ps
CPU time 177.53 seconds
Started Mar 31 03:44:06 PM PDT 24
Finished Mar 31 03:47:04 PM PDT 24
Peak memory 789876 kb
Host smart-e1c296c6-6db6-4d5c-82a2-ccbceb509832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564209135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.564209135
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.1083118266
Short name T251
Test name
Test status
Simulation time 6052933126 ps
CPU time 35.74 seconds
Started Mar 31 03:43:59 PM PDT 24
Finished Mar 31 03:44:35 PM PDT 24
Peak memory 533688 kb
Host smart-321b7ac6-5741-43b8-8bc5-dfe8760b833b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083118266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.1083118266
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.2377435270
Short name T264
Test name
Test status
Simulation time 366077351 ps
CPU time 1.02 seconds
Started Mar 31 03:44:12 PM PDT 24
Finished Mar 31 03:44:14 PM PDT 24
Peak memory 203776 kb
Host smart-97048e05-9228-4c32-acfe-2e99d5c40c8c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377435270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fm
t.2377435270
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.2514498786
Short name T1078
Test name
Test status
Simulation time 137327909 ps
CPU time 3.68 seconds
Started Mar 31 03:44:06 PM PDT 24
Finished Mar 31 03:44:10 PM PDT 24
Peak memory 223596 kb
Host smart-ce9d52e1-b2cc-4615-93aa-8a2686bc832a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514498786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
2514498786
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.3440441789
Short name T373
Test name
Test status
Simulation time 4364017678 ps
CPU time 318.42 seconds
Started Mar 31 03:43:59 PM PDT 24
Finished Mar 31 03:49:17 PM PDT 24
Peak memory 1219044 kb
Host smart-6292a511-49fe-4ebd-aafa-e4327ebf0453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440441789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.3440441789
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.2500328782
Short name T825
Test name
Test status
Simulation time 482478263 ps
CPU time 7.63 seconds
Started Mar 31 03:44:05 PM PDT 24
Finished Mar 31 03:44:12 PM PDT 24
Peak memory 203700 kb
Host smart-77ae57da-b6e0-4e3e-8b92-f97fc4a829a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500328782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.2500328782
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.3978697627
Short name T1052
Test name
Test status
Simulation time 7829753224 ps
CPU time 31.45 seconds
Started Mar 31 03:44:13 PM PDT 24
Finished Mar 31 03:44:44 PM PDT 24
Peak memory 330672 kb
Host smart-07e2fdfd-2be4-4c99-8ba4-4a5a9dd02aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978697627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.3978697627
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.2506746971
Short name T892
Test name
Test status
Simulation time 135119233 ps
CPU time 0.68 seconds
Started Mar 31 03:43:57 PM PDT 24
Finished Mar 31 03:43:57 PM PDT 24
Peak memory 203616 kb
Host smart-97381421-8b62-4aaa-a26a-9c50c1f568d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506746971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.2506746971
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.1179014878
Short name T625
Test name
Test status
Simulation time 754843133 ps
CPU time 7.37 seconds
Started Mar 31 03:44:03 PM PDT 24
Finished Mar 31 03:44:11 PM PDT 24
Peak memory 249340 kb
Host smart-01d87df6-0efd-4a14-b7c2-e93d6ce424f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179014878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.1179014878
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.3689521618
Short name T633
Test name
Test status
Simulation time 2329725761 ps
CPU time 21.84 seconds
Started Mar 31 03:44:03 PM PDT 24
Finished Mar 31 03:44:25 PM PDT 24
Peak memory 343668 kb
Host smart-ebad1bbb-d643-4850-bd18-c148a5216cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689521618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.3689521618
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.661339045
Short name T108
Test name
Test status
Simulation time 67889510 ps
CPU time 0.97 seconds
Started Mar 31 03:44:06 PM PDT 24
Finished Mar 31 03:44:08 PM PDT 24
Peak memory 222356 kb
Host smart-249117a9-cabd-4691-9d92-a521ab03f738
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661339045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.661339045
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.1962013174
Short name T30
Test name
Test status
Simulation time 1140271495 ps
CPU time 3.35 seconds
Started Mar 31 03:44:13 PM PDT 24
Finished Mar 31 03:44:17 PM PDT 24
Peak memory 203936 kb
Host smart-541f39a8-c02b-4577-b131-0bd24884fa47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962013174 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.1962013174
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.2393413129
Short name T901
Test name
Test status
Simulation time 10200495925 ps
CPU time 13.06 seconds
Started Mar 31 03:44:04 PM PDT 24
Finished Mar 31 03:44:18 PM PDT 24
Peak memory 287664 kb
Host smart-b2045706-11af-405c-a687-09b7f250ab35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393413129 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_fifo_reset_acq.2393413129
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.1769355470
Short name T635
Test name
Test status
Simulation time 10130421033 ps
CPU time 102.8 seconds
Started Mar 31 03:44:07 PM PDT 24
Finished Mar 31 03:45:50 PM PDT 24
Peak memory 675400 kb
Host smart-82ec3c28-bd9c-47f5-b8ca-15da9def0e0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769355470 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.1769355470
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.2310857965
Short name T879
Test name
Test status
Simulation time 690671919 ps
CPU time 2.1 seconds
Started Mar 31 03:44:09 PM PDT 24
Finished Mar 31 03:44:12 PM PDT 24
Peak memory 203864 kb
Host smart-9a7e7dfd-4e24-4113-9688-4910a87dd515
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310857965 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_hrst.2310857965
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.4124419484
Short name T385
Test name
Test status
Simulation time 1007661169 ps
CPU time 5.65 seconds
Started Mar 31 03:44:08 PM PDT 24
Finished Mar 31 03:44:13 PM PDT 24
Peak memory 218324 kb
Host smart-dd4046a5-0146-44e2-89de-b06e48208542
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124419484 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_intr_smoke.4124419484
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.3510273917
Short name T1030
Test name
Test status
Simulation time 3382497838 ps
CPU time 10.92 seconds
Started Mar 31 03:44:02 PM PDT 24
Finished Mar 31 03:44:13 PM PDT 24
Peak memory 203820 kb
Host smart-f6ece345-b4f1-4325-9a96-8e77ae7be27b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510273917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.3510273917
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.3658272456
Short name T402
Test name
Test status
Simulation time 4049584423 ps
CPU time 17.54 seconds
Started Mar 31 03:44:03 PM PDT 24
Finished Mar 31 03:44:20 PM PDT 24
Peak memory 203868 kb
Host smart-33613611-89a9-4554-af62-746abac0fa76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658272456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.3658272456
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.346000164
Short name T878
Test name
Test status
Simulation time 8314670024 ps
CPU time 142.89 seconds
Started Mar 31 03:44:05 PM PDT 24
Finished Mar 31 03:46:28 PM PDT 24
Peak memory 1291392 kb
Host smart-c24c9f24-510d-4d2b-8129-778983d8c0d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346000164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_ta
rget_stretch.346000164
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.1262793387
Short name T489
Test name
Test status
Simulation time 3233890925 ps
CPU time 7.92 seconds
Started Mar 31 03:44:08 PM PDT 24
Finished Mar 31 03:44:16 PM PDT 24
Peak memory 212092 kb
Host smart-16e6c053-0f0f-411e-bff6-ed7f252f8682
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262793387 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.1262793387
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_alert_test.1504327402
Short name T504
Test name
Test status
Simulation time 18280865 ps
CPU time 0.64 seconds
Started Mar 31 03:47:22 PM PDT 24
Finished Mar 31 03:47:23 PM PDT 24
Peak memory 203692 kb
Host smart-11748b6b-50d5-4df0-8e83-3b45243d94e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504327402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.1504327402
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.3021110620
Short name T912
Test name
Test status
Simulation time 129394416 ps
CPU time 1.24 seconds
Started Mar 31 03:47:28 PM PDT 24
Finished Mar 31 03:47:30 PM PDT 24
Peak memory 212008 kb
Host smart-40182247-ee02-4268-b048-041fd86b0b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021110620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.3021110620
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.4289844935
Short name T358
Test name
Test status
Simulation time 1151636864 ps
CPU time 15 seconds
Started Mar 31 03:47:17 PM PDT 24
Finished Mar 31 03:47:33 PM PDT 24
Peak memory 263740 kb
Host smart-0fccb890-59c9-419c-a316-598096a72324
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289844935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.4289844935
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.1354531149
Short name T727
Test name
Test status
Simulation time 1721636062 ps
CPU time 34.11 seconds
Started Mar 31 03:47:11 PM PDT 24
Finished Mar 31 03:47:46 PM PDT 24
Peak memory 285320 kb
Host smart-a7898072-5862-4212-8d53-6fd2b8eec23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354531149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.1354531149
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.3108757478
Short name T690
Test name
Test status
Simulation time 2147128289 ps
CPU time 79.54 seconds
Started Mar 31 03:47:13 PM PDT 24
Finished Mar 31 03:48:33 PM PDT 24
Peak memory 735280 kb
Host smart-e6f78c09-043f-4cd8-a9bb-719b5b23bef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108757478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.3108757478
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.3246661707
Short name T1200
Test name
Test status
Simulation time 585687074 ps
CPU time 1.1 seconds
Started Mar 31 03:47:13 PM PDT 24
Finished Mar 31 03:47:14 PM PDT 24
Peak memory 203732 kb
Host smart-e61d08fe-50b2-474b-8293-c2fd2622aefc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246661707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_f
mt.3246661707
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.58993622
Short name T992
Test name
Test status
Simulation time 656477358 ps
CPU time 4.8 seconds
Started Mar 31 03:47:18 PM PDT 24
Finished Mar 31 03:47:23 PM PDT 24
Peak memory 230828 kb
Host smart-1709e241-c633-49bd-9d7b-08882d43b213
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58993622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx.58993622
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.3273484460
Short name T450
Test name
Test status
Simulation time 5308650888 ps
CPU time 182.74 seconds
Started Mar 31 03:47:13 PM PDT 24
Finished Mar 31 03:50:16 PM PDT 24
Peak memory 864768 kb
Host smart-babf88e6-13db-4e7c-9e09-9d20bc26f744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273484460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.3273484460
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.149082866
Short name T745
Test name
Test status
Simulation time 261720390 ps
CPU time 10.84 seconds
Started Mar 31 03:47:24 PM PDT 24
Finished Mar 31 03:47:35 PM PDT 24
Peak memory 203788 kb
Host smart-ab60425d-f390-4343-b8e3-7a32205ac74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149082866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.149082866
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.3998295755
Short name T659
Test name
Test status
Simulation time 1410510269 ps
CPU time 28.43 seconds
Started Mar 31 03:47:20 PM PDT 24
Finished Mar 31 03:47:49 PM PDT 24
Peak memory 415292 kb
Host smart-a6d35473-ff52-420f-87fe-e048e3db9c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998295755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.3998295755
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.1121646543
Short name T183
Test name
Test status
Simulation time 16170828 ps
CPU time 0.63 seconds
Started Mar 31 03:47:15 PM PDT 24
Finished Mar 31 03:47:16 PM PDT 24
Peak memory 203608 kb
Host smart-4907306e-c008-4e11-b893-83e1a974ed6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121646543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.1121646543
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.3626511374
Short name T1044
Test name
Test status
Simulation time 28110318172 ps
CPU time 1068.71 seconds
Started Mar 31 03:47:17 PM PDT 24
Finished Mar 31 04:05:06 PM PDT 24
Peak memory 3080840 kb
Host smart-0e837659-63ed-45b9-84d4-fb8953687db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626511374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.3626511374
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.1740488876
Short name T530
Test name
Test status
Simulation time 1640560472 ps
CPU time 35.67 seconds
Started Mar 31 03:47:17 PM PDT 24
Finished Mar 31 03:47:53 PM PDT 24
Peak memory 356292 kb
Host smart-f6d40d37-8762-4825-8dbe-2f375bb1cc90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740488876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.1740488876
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.309985134
Short name T1069
Test name
Test status
Simulation time 871429345 ps
CPU time 4.13 seconds
Started Mar 31 03:47:20 PM PDT 24
Finished Mar 31 03:47:24 PM PDT 24
Peak memory 203820 kb
Host smart-dc83ad2b-2f28-4cbd-b84b-f7d5d4597676
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309985134 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.309985134
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.3020940865
Short name T937
Test name
Test status
Simulation time 10226924207 ps
CPU time 13.19 seconds
Started Mar 31 03:47:25 PM PDT 24
Finished Mar 31 03:47:38 PM PDT 24
Peak memory 271888 kb
Host smart-e20106d2-ac63-4e53-a670-436d38a48857
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020940865 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.3020940865
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.990667276
Short name T492
Test name
Test status
Simulation time 10222563604 ps
CPU time 16.23 seconds
Started Mar 31 03:47:23 PM PDT 24
Finished Mar 31 03:47:40 PM PDT 24
Peak memory 343616 kb
Host smart-0dc27c43-948b-466f-b441-63843fd2da9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990667276 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.i2c_target_fifo_reset_tx.990667276
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.982368130
Short name T555
Test name
Test status
Simulation time 872908240 ps
CPU time 2.82 seconds
Started Mar 31 03:47:20 PM PDT 24
Finished Mar 31 03:47:23 PM PDT 24
Peak memory 203808 kb
Host smart-cb77d390-c1a4-4c5c-9384-99bb8bf4843d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982368130 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 40.i2c_target_hrst.982368130
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.3475027736
Short name T50
Test name
Test status
Simulation time 7996821190 ps
CPU time 3.91 seconds
Started Mar 31 03:47:22 PM PDT 24
Finished Mar 31 03:47:26 PM PDT 24
Peak memory 203860 kb
Host smart-373666bc-e6e7-4b86-ac62-2df9bc175166
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475027736 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.3475027736
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.943034846
Short name T657
Test name
Test status
Simulation time 6484053112 ps
CPU time 2.8 seconds
Started Mar 31 03:47:28 PM PDT 24
Finished Mar 31 03:47:32 PM PDT 24
Peak memory 203832 kb
Host smart-9161b43c-9f77-4289-b475-dd2b03857780
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943034846 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.943034846
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.2247338447
Short name T10
Test name
Test status
Simulation time 1356997337 ps
CPU time 19.2 seconds
Started Mar 31 03:47:32 PM PDT 24
Finished Mar 31 03:47:52 PM PDT 24
Peak memory 203808 kb
Host smart-015bed09-7a8f-447c-a2eb-a4930176768f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247338447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_ta
rget_smoke.2247338447
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.4246768409
Short name T908
Test name
Test status
Simulation time 934638690 ps
CPU time 4.88 seconds
Started Mar 31 03:47:21 PM PDT 24
Finished Mar 31 03:47:26 PM PDT 24
Peak memory 203852 kb
Host smart-7b507d24-2c46-4a29-b6c0-07af830b8944
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246768409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.4246768409
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.3193098903
Short name T578
Test name
Test status
Simulation time 20895335049 ps
CPU time 4.83 seconds
Started Mar 31 03:47:23 PM PDT 24
Finished Mar 31 03:47:28 PM PDT 24
Peak memory 203892 kb
Host smart-3a7ae517-b646-419e-8bb4-f6f469cf4694
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193098903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_wr.3193098903
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.3253152249
Short name T1159
Test name
Test status
Simulation time 41230349724 ps
CPU time 956.78 seconds
Started Mar 31 03:47:22 PM PDT 24
Finished Mar 31 04:03:19 PM PDT 24
Peak memory 2441380 kb
Host smart-267b9b5e-1493-4794-9fbb-112a1078e312
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253152249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stretch.3253152249
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.3557435179
Short name T513
Test name
Test status
Simulation time 1219197087 ps
CPU time 6.9 seconds
Started Mar 31 03:47:22 PM PDT 24
Finished Mar 31 03:47:29 PM PDT 24
Peak memory 219216 kb
Host smart-16c9c285-2676-4d2d-ba75-fb5ba66c6127
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557435179 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_timeout.3557435179
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_alert_test.2036815038
Short name T566
Test name
Test status
Simulation time 56443999 ps
CPU time 0.65 seconds
Started Mar 31 03:47:23 PM PDT 24
Finished Mar 31 03:47:24 PM PDT 24
Peak memory 203596 kb
Host smart-9cd7eef0-8a4c-4c36-bcf7-2c2c3f5045af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036815038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.2036815038
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.2479663160
Short name T956
Test name
Test status
Simulation time 91782610 ps
CPU time 1.5 seconds
Started Mar 31 03:47:19 PM PDT 24
Finished Mar 31 03:47:21 PM PDT 24
Peak memory 212124 kb
Host smart-06a60b36-11fb-4988-92d3-c4275c8cac26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479663160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.2479663160
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.2812188765
Short name T1185
Test name
Test status
Simulation time 226001839 ps
CPU time 4.16 seconds
Started Mar 31 03:47:21 PM PDT 24
Finished Mar 31 03:47:25 PM PDT 24
Peak memory 249736 kb
Host smart-f3384288-d4a6-4022-b6bf-6c8182e249dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812188765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp
ty.2812188765
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.2665665091
Short name T82
Test name
Test status
Simulation time 2083557527 ps
CPU time 79.65 seconds
Started Mar 31 03:47:25 PM PDT 24
Finished Mar 31 03:48:45 PM PDT 24
Peak memory 721924 kb
Host smart-656c5f74-88d8-4430-b8fd-68246fe1636a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665665091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.2665665091
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.56941645
Short name T914
Test name
Test status
Simulation time 5755129810 ps
CPU time 47.71 seconds
Started Mar 31 03:47:21 PM PDT 24
Finished Mar 31 03:48:08 PM PDT 24
Peak memory 585692 kb
Host smart-3ce28119-0787-4ef8-82f0-bc8fb8afb144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56941645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.56941645
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.3243692215
Short name T486
Test name
Test status
Simulation time 118138681 ps
CPU time 1.15 seconds
Started Mar 31 03:47:23 PM PDT 24
Finished Mar 31 03:47:24 PM PDT 24
Peak memory 203796 kb
Host smart-472cc7c6-0a5f-4e66-91c0-ad6b4cfa9358
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243692215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_f
mt.3243692215
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.2672479713
Short name T1000
Test name
Test status
Simulation time 135423397 ps
CPU time 4.1 seconds
Started Mar 31 03:47:21 PM PDT 24
Finished Mar 31 03:47:25 PM PDT 24
Peak memory 226420 kb
Host smart-cacccb95-0dd9-48c2-9b0c-e247dd5f6e83
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672479713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx
.2672479713
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.140152234
Short name T162
Test name
Test status
Simulation time 3618985798 ps
CPU time 83.22 seconds
Started Mar 31 03:47:29 PM PDT 24
Finished Mar 31 03:48:52 PM PDT 24
Peak memory 1037940 kb
Host smart-acf905d4-f6a3-4d5b-86d0-f59264cd34ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140152234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.140152234
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.1438176020
Short name T921
Test name
Test status
Simulation time 1046866698 ps
CPU time 15.01 seconds
Started Mar 31 03:47:24 PM PDT 24
Finished Mar 31 03:47:40 PM PDT 24
Peak memory 203808 kb
Host smart-91ea0754-a854-4add-b636-368a63ce328a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438176020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.1438176020
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/41.i2c_host_mode_toggle.1041436274
Short name T601
Test name
Test status
Simulation time 3798793844 ps
CPU time 16.14 seconds
Started Mar 31 03:47:23 PM PDT 24
Finished Mar 31 03:47:40 PM PDT 24
Peak memory 319056 kb
Host smart-bd5a3da4-beb5-454f-ac24-3b3f0d5aee44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041436274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.1041436274
Directory /workspace/41.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/41.i2c_host_override.1334872878
Short name T759
Test name
Test status
Simulation time 51108390 ps
CPU time 0.66 seconds
Started Mar 31 03:47:22 PM PDT 24
Finished Mar 31 03:47:23 PM PDT 24
Peak memory 203588 kb
Host smart-3a9a69c0-839a-4aee-ba84-ed89e1ff983f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334872878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.1334872878
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.1529163779
Short name T190
Test name
Test status
Simulation time 6247456777 ps
CPU time 63.65 seconds
Started Mar 31 03:47:19 PM PDT 24
Finished Mar 31 03:48:23 PM PDT 24
Peak memory 213064 kb
Host smart-24a0d1db-b013-48f6-ac9e-91d5a6730409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529163779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.1529163779
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.466433185
Short name T729
Test name
Test status
Simulation time 7601665872 ps
CPU time 45.77 seconds
Started Mar 31 03:47:20 PM PDT 24
Finished Mar 31 03:48:06 PM PDT 24
Peak memory 300864 kb
Host smart-c4ca8c4a-0a28-4f11-8a2c-b1897df9cbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466433185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.466433185
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.851808236
Short name T294
Test name
Test status
Simulation time 1066046505 ps
CPU time 4.53 seconds
Started Mar 31 03:47:28 PM PDT 24
Finished Mar 31 03:47:32 PM PDT 24
Peak memory 212048 kb
Host smart-b655e6b2-532c-4e5f-b089-405afd2be25a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851808236 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.851808236
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.1200208764
Short name T958
Test name
Test status
Simulation time 10092190272 ps
CPU time 68.04 seconds
Started Mar 31 03:47:25 PM PDT 24
Finished Mar 31 03:48:34 PM PDT 24
Peak memory 561724 kb
Host smart-6388c8f7-b5b4-4df2-985c-cb6aa39ed97f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200208764 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_fifo_reset_acq.1200208764
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.2582627538
Short name T1180
Test name
Test status
Simulation time 10390505828 ps
CPU time 17.92 seconds
Started Mar 31 03:47:29 PM PDT 24
Finished Mar 31 03:47:47 PM PDT 24
Peak memory 348536 kb
Host smart-2ba75e9e-9874-4fdb-9424-3369ff2ce674
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582627538 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_tx.2582627538
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.2928507927
Short name T208
Test name
Test status
Simulation time 645482745 ps
CPU time 3.26 seconds
Started Mar 31 03:47:25 PM PDT 24
Finished Mar 31 03:47:28 PM PDT 24
Peak memory 203752 kb
Host smart-fbe63cbd-7733-4cca-8042-d557222468fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928507927 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.2928507927
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.1168075871
Short name T599
Test name
Test status
Simulation time 16902641981 ps
CPU time 4.69 seconds
Started Mar 31 03:47:30 PM PDT 24
Finished Mar 31 03:47:35 PM PDT 24
Peak memory 204520 kb
Host smart-0a20c990-a581-4e9b-b328-72198f96ddfc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168075871 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.1168075871
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.3253010886
Short name T740
Test name
Test status
Simulation time 2057339911 ps
CPU time 14.56 seconds
Started Mar 31 03:47:21 PM PDT 24
Finished Mar 31 03:47:35 PM PDT 24
Peak memory 203744 kb
Host smart-de37c5e2-7ff0-4486-8f94-553802ee2e94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253010886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_smoke.3253010886
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.3518770077
Short name T411
Test name
Test status
Simulation time 791701051 ps
CPU time 16.02 seconds
Started Mar 31 03:47:25 PM PDT 24
Finished Mar 31 03:47:42 PM PDT 24
Peak memory 203868 kb
Host smart-90c1bad6-9be9-4c48-8275-eeefc95a9e46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518770077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_rd.3518770077
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.2652157150
Short name T813
Test name
Test status
Simulation time 20403777642 ps
CPU time 170.47 seconds
Started Mar 31 03:47:27 PM PDT 24
Finished Mar 31 03:50:18 PM PDT 24
Peak memory 1329192 kb
Host smart-fbc3fd7e-2211-4da9-b5c1-7da65d6ec7d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652157150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stretch.2652157150
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.2588496899
Short name T629
Test name
Test status
Simulation time 2816172757 ps
CPU time 6.77 seconds
Started Mar 31 03:47:27 PM PDT 24
Finished Mar 31 03:47:34 PM PDT 24
Peak memory 214260 kb
Host smart-aabee454-01bc-47e0-ad44-2fe8e262f612
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588496899 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.2588496899
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_alert_test.3301096991
Short name T621
Test name
Test status
Simulation time 21838390 ps
CPU time 0.62 seconds
Started Mar 31 03:47:37 PM PDT 24
Finished Mar 31 03:47:38 PM PDT 24
Peak memory 203644 kb
Host smart-c5224517-43c9-48ba-80a2-5a8e27f0417e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301096991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.3301096991
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.764834500
Short name T310
Test name
Test status
Simulation time 355086009 ps
CPU time 1.27 seconds
Started Mar 31 03:47:36 PM PDT 24
Finished Mar 31 03:47:38 PM PDT 24
Peak memory 212044 kb
Host smart-91261be0-7c57-41b6-88cf-da9abdc258e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764834500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.764834500
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.3600858706
Short name T950
Test name
Test status
Simulation time 216115012 ps
CPU time 10.8 seconds
Started Mar 31 03:47:28 PM PDT 24
Finished Mar 31 03:47:39 PM PDT 24
Peak memory 240440 kb
Host smart-b052df83-5197-45b7-9a89-fc79b3e8ae2f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600858706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_emp
ty.3600858706
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.3359447765
Short name T646
Test name
Test status
Simulation time 1902085930 ps
CPU time 134.43 seconds
Started Mar 31 03:47:27 PM PDT 24
Finished Mar 31 03:49:41 PM PDT 24
Peak memory 652656 kb
Host smart-2f86535d-3368-4f0b-9f07-60077ed8475c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359447765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.3359447765
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.24917623
Short name T313
Test name
Test status
Simulation time 1188372682 ps
CPU time 38.02 seconds
Started Mar 31 03:47:28 PM PDT 24
Finished Mar 31 03:48:06 PM PDT 24
Peak memory 485592 kb
Host smart-b949a4eb-5a6a-4b01-9f2a-e35b057727f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24917623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.24917623
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.3190238262
Short name T1055
Test name
Test status
Simulation time 298001326 ps
CPU time 0.91 seconds
Started Mar 31 03:47:27 PM PDT 24
Finished Mar 31 03:47:28 PM PDT 24
Peak memory 203732 kb
Host smart-631e3fd1-e696-4276-98ad-1b5c676bd341
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190238262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.3190238262
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.3216164077
Short name T474
Test name
Test status
Simulation time 455003967 ps
CPU time 3.31 seconds
Started Mar 31 03:47:28 PM PDT 24
Finished Mar 31 03:47:31 PM PDT 24
Peak memory 218960 kb
Host smart-94e34674-becc-4506-8cba-23597f64c83b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216164077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.3216164077
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.2829533678
Short name T808
Test name
Test status
Simulation time 4038400997 ps
CPU time 121.78 seconds
Started Mar 31 03:47:23 PM PDT 24
Finished Mar 31 03:49:25 PM PDT 24
Peak memory 1168716 kb
Host smart-fa476280-09af-48a7-8a5a-806c76114e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829533678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.2829533678
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.208975625
Short name T1125
Test name
Test status
Simulation time 2092459270 ps
CPU time 6.43 seconds
Started Mar 31 03:47:37 PM PDT 24
Finished Mar 31 03:47:44 PM PDT 24
Peak memory 203764 kb
Host smart-a9c8c0bf-5d7a-462d-9538-cbb0600129f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208975625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.208975625
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.3908839626
Short name T799
Test name
Test status
Simulation time 3681990228 ps
CPU time 94.79 seconds
Started Mar 31 03:47:29 PM PDT 24
Finished Mar 31 03:49:04 PM PDT 24
Peak memory 459404 kb
Host smart-4f20ad12-daae-45f5-9914-c46db88e054e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908839626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.3908839626
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_override.2718187058
Short name T279
Test name
Test status
Simulation time 26060404 ps
CPU time 0.7 seconds
Started Mar 31 03:47:42 PM PDT 24
Finished Mar 31 03:47:43 PM PDT 24
Peak memory 203620 kb
Host smart-268254c0-5429-4cfa-bfe3-53f72c4b7ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718187058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.2718187058
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.954367331
Short name T192
Test name
Test status
Simulation time 534798632 ps
CPU time 8.04 seconds
Started Mar 31 03:47:39 PM PDT 24
Finished Mar 31 03:47:47 PM PDT 24
Peak memory 256704 kb
Host smart-013bbdb2-5389-41ba-9c86-e3684180b867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954367331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.954367331
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.478372857
Short name T213
Test name
Test status
Simulation time 1250868206 ps
CPU time 25 seconds
Started Mar 31 03:47:27 PM PDT 24
Finished Mar 31 03:47:53 PM PDT 24
Peak memory 374288 kb
Host smart-343d260f-6c46-43f1-8168-92a6fe1b2247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478372857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.478372857
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.26711590
Short name T1097
Test name
Test status
Simulation time 668738513 ps
CPU time 3.46 seconds
Started Mar 31 03:47:45 PM PDT 24
Finished Mar 31 03:47:49 PM PDT 24
Peak memory 203820 kb
Host smart-8b48e0bc-dda5-425d-954c-bd86b5733bca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26711590 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_bad_addr.26711590
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.213623069
Short name T391
Test name
Test status
Simulation time 10095426056 ps
CPU time 25.22 seconds
Started Mar 31 03:47:32 PM PDT 24
Finished Mar 31 03:47:58 PM PDT 24
Peak memory 353644 kb
Host smart-64ea38aa-8c91-4516-bd04-ac316e85c397
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213623069 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_acq.213623069
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.4026683389
Short name T367
Test name
Test status
Simulation time 10238739037 ps
CPU time 45.67 seconds
Started Mar 31 03:47:42 PM PDT 24
Finished Mar 31 03:48:28 PM PDT 24
Peak memory 468692 kb
Host smart-e091efaa-8de9-4aec-9517-c6b6cff33834
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026683389 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_tx.4026683389
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.2280766829
Short name T386
Test name
Test status
Simulation time 742931453 ps
CPU time 2.71 seconds
Started Mar 31 03:47:25 PM PDT 24
Finished Mar 31 03:47:28 PM PDT 24
Peak memory 203796 kb
Host smart-35960c1b-d4e1-47f9-aa1d-4adafd653396
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280766829 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_hrst.2280766829
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.1761487532
Short name T837
Test name
Test status
Simulation time 1201991156 ps
CPU time 3.9 seconds
Started Mar 31 03:47:27 PM PDT 24
Finished Mar 31 03:47:31 PM PDT 24
Peak memory 207788 kb
Host smart-72a67844-75a2-4e29-aa9b-a80a3cb39312
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761487532 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_intr_smoke.1761487532
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.2558878774
Short name T807
Test name
Test status
Simulation time 2646009395 ps
CPU time 27.23 seconds
Started Mar 31 03:47:25 PM PDT 24
Finished Mar 31 03:47:52 PM PDT 24
Peak memory 203828 kb
Host smart-5aa1755c-5109-4d93-a6bc-41044ad30b5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558878774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ta
rget_smoke.2558878774
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.2204079319
Short name T423
Test name
Test status
Simulation time 4768380617 ps
CPU time 23.19 seconds
Started Mar 31 03:47:38 PM PDT 24
Finished Mar 31 03:48:01 PM PDT 24
Peak memory 220216 kb
Host smart-d86dd9e2-5c35-4236-a987-dd4dba304702
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204079319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_rd.2204079319
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.309131644
Short name T1157
Test name
Test status
Simulation time 42207811886 ps
CPU time 1021.42 seconds
Started Mar 31 03:47:24 PM PDT 24
Finished Mar 31 04:04:26 PM PDT 24
Peak memory 4853176 kb
Host smart-be96de9c-68bd-4be7-be3c-eff21399e6d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309131644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_t
arget_stretch.309131644
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.875887551
Short name T661
Test name
Test status
Simulation time 1396958467 ps
CPU time 6.88 seconds
Started Mar 31 03:47:37 PM PDT 24
Finished Mar 31 03:47:44 PM PDT 24
Peak memory 208056 kb
Host smart-de9e123d-7525-4cf4-9e2b-2f57950345f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875887551 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_timeout.875887551
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_alert_test.2246965667
Short name T1102
Test name
Test status
Simulation time 43966822 ps
CPU time 0.62 seconds
Started Mar 31 03:47:40 PM PDT 24
Finished Mar 31 03:47:41 PM PDT 24
Peak memory 203724 kb
Host smart-7e7dd9f7-c89a-4a13-977d-8902b01548c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246965667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.2246965667
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.2374822156
Short name T685
Test name
Test status
Simulation time 104221403 ps
CPU time 1.37 seconds
Started Mar 31 03:47:30 PM PDT 24
Finished Mar 31 03:47:31 PM PDT 24
Peak memory 211992 kb
Host smart-082b4970-933d-4024-ad22-66370e28fad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374822156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.2374822156
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.2025928395
Short name T602
Test name
Test status
Simulation time 592597956 ps
CPU time 5.55 seconds
Started Mar 31 03:47:31 PM PDT 24
Finished Mar 31 03:47:37 PM PDT 24
Peak memory 263104 kb
Host smart-0816a256-a5b0-4c1b-a462-bd3e206fc9ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025928395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.2025928395
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.2724495721
Short name T1095
Test name
Test status
Simulation time 1384123217 ps
CPU time 33.18 seconds
Started Mar 31 03:47:31 PM PDT 24
Finished Mar 31 03:48:05 PM PDT 24
Peak memory 421980 kb
Host smart-3958bfc2-5450-4975-85d6-07dc74fe8796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724495721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.2724495721
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.985618706
Short name T472
Test name
Test status
Simulation time 7175262919 ps
CPU time 133.06 seconds
Started Mar 31 03:47:33 PM PDT 24
Finished Mar 31 03:49:46 PM PDT 24
Peak memory 633548 kb
Host smart-2c58c79c-533a-417f-ba56-b99547547e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985618706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.985618706
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.4040719808
Short name T201
Test name
Test status
Simulation time 92711019 ps
CPU time 0.8 seconds
Started Mar 31 03:47:28 PM PDT 24
Finished Mar 31 03:47:29 PM PDT 24
Peak memory 203680 kb
Host smart-3936d5df-cae6-43d0-bff1-c041777e14f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040719808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_f
mt.4040719808
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.470952910
Short name T1139
Test name
Test status
Simulation time 899808206 ps
CPU time 8.08 seconds
Started Mar 31 03:47:47 PM PDT 24
Finished Mar 31 03:47:56 PM PDT 24
Peak memory 203808 kb
Host smart-ab024041-56a3-41af-9e1f-aee192fab2d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470952910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx.
470952910
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.3275388481
Short name T229
Test name
Test status
Simulation time 10217640149 ps
CPU time 254.4 seconds
Started Mar 31 03:47:25 PM PDT 24
Finished Mar 31 03:51:39 PM PDT 24
Peak memory 1036144 kb
Host smart-be729150-5dc8-4c1c-96b5-5d199bad8229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275388481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.3275388481
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.2150309640
Short name T374
Test name
Test status
Simulation time 2420606375 ps
CPU time 22.09 seconds
Started Mar 31 03:47:34 PM PDT 24
Finished Mar 31 03:47:57 PM PDT 24
Peak memory 203868 kb
Host smart-e873e32a-21d1-48d6-b673-3bc69f35e8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150309640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.2150309640
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.1321370256
Short name T11
Test name
Test status
Simulation time 3177765239 ps
CPU time 74.32 seconds
Started Mar 31 03:47:33 PM PDT 24
Finished Mar 31 03:48:48 PM PDT 24
Peak memory 364704 kb
Host smart-437a2fe8-c136-48c2-84e2-ac796a2a3b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321370256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.1321370256
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.1312145612
Short name T181
Test name
Test status
Simulation time 32836950 ps
CPU time 0.65 seconds
Started Mar 31 03:47:25 PM PDT 24
Finished Mar 31 03:47:26 PM PDT 24
Peak memory 203600 kb
Host smart-5615417a-28fa-4fdc-b806-461715700bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312145612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.1312145612
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.94412819
Short name T653
Test name
Test status
Simulation time 8091599292 ps
CPU time 21.16 seconds
Started Mar 31 03:47:30 PM PDT 24
Finished Mar 31 03:47:52 PM PDT 24
Peak memory 429700 kb
Host smart-b90e27c2-48d3-4f32-b197-bb808f5cbbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94412819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.94412819
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.24235993
Short name T73
Test name
Test status
Simulation time 2457408827 ps
CPU time 57.05 seconds
Started Mar 31 03:47:26 PM PDT 24
Finished Mar 31 03:48:23 PM PDT 24
Peak memory 324740 kb
Host smart-a030fe4b-3b27-4bbf-a8e3-254f1fe53100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24235993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.24235993
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.4215808088
Short name T552
Test name
Test status
Simulation time 3378368977 ps
CPU time 3.82 seconds
Started Mar 31 03:47:38 PM PDT 24
Finished Mar 31 03:47:42 PM PDT 24
Peak memory 212088 kb
Host smart-994f9baf-1415-4cef-9568-1edd317d4af0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215808088 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.4215808088
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.4116811836
Short name T1117
Test name
Test status
Simulation time 10093263843 ps
CPU time 52.64 seconds
Started Mar 31 03:47:32 PM PDT 24
Finished Mar 31 03:48:25 PM PDT 24
Peak memory 495988 kb
Host smart-90e56b51-3fbe-46d6-a720-7be12f6f72cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116811836 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.4116811836
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.1912536669
Short name T1155
Test name
Test status
Simulation time 10126465440 ps
CPU time 16.1 seconds
Started Mar 31 03:47:34 PM PDT 24
Finished Mar 31 03:47:51 PM PDT 24
Peak memory 315252 kb
Host smart-d6cba034-2a60-4eb3-9f50-76f9d6225a73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912536669 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_tx.1912536669
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.1532039805
Short name T887
Test name
Test status
Simulation time 837335653 ps
CPU time 2.9 seconds
Started Mar 31 03:47:35 PM PDT 24
Finished Mar 31 03:47:38 PM PDT 24
Peak memory 203856 kb
Host smart-c158ee86-5012-4f26-ae0a-16fc5d93d3c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532039805 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_hrst.1532039805
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.3635315622
Short name T296
Test name
Test status
Simulation time 1072340970 ps
CPU time 5.23 seconds
Started Mar 31 03:47:31 PM PDT 24
Finished Mar 31 03:47:36 PM PDT 24
Peak memory 203792 kb
Host smart-d6a3c97b-306a-4370-adc6-be67521d63e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635315622 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.3635315622
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.881969267
Short name T484
Test name
Test status
Simulation time 1350453247 ps
CPU time 22.12 seconds
Started Mar 31 03:47:27 PM PDT 24
Finished Mar 31 03:47:50 PM PDT 24
Peak memory 203632 kb
Host smart-4d1b3d28-0eda-4c90-a00c-2d53275584ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881969267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_tar
get_smoke.881969267
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.2071788919
Short name T209
Test name
Test status
Simulation time 276551844 ps
CPU time 10.15 seconds
Started Mar 31 03:47:29 PM PDT 24
Finished Mar 31 03:47:39 PM PDT 24
Peak memory 203764 kb
Host smart-41eff3ad-b7f7-479b-be0e-6aacdf782a52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071788919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.2071788919
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.4110898364
Short name T276
Test name
Test status
Simulation time 5907534627 ps
CPU time 6.66 seconds
Started Mar 31 03:47:29 PM PDT 24
Finished Mar 31 03:47:37 PM PDT 24
Peak memory 219368 kb
Host smart-3a2749aa-7ac9-490f-83ea-76aa09effaa6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110898364 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_timeout.4110898364
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_alert_test.2111038772
Short name T256
Test name
Test status
Simulation time 25075893 ps
CPU time 0.62 seconds
Started Mar 31 03:47:39 PM PDT 24
Finished Mar 31 03:47:40 PM PDT 24
Peak memory 203648 kb
Host smart-a31cf7a3-1fe9-441f-90c7-1d77335f4813
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111038772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.2111038772
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.3164802459
Short name T1128
Test name
Test status
Simulation time 1444249536 ps
CPU time 1.4 seconds
Started Mar 31 03:47:35 PM PDT 24
Finished Mar 31 03:47:36 PM PDT 24
Peak memory 212036 kb
Host smart-f00a3681-5a00-49ca-9043-a3d4ec8edd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164802459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.3164802459
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.437242515
Short name T603
Test name
Test status
Simulation time 3806210711 ps
CPU time 7.1 seconds
Started Mar 31 03:47:33 PM PDT 24
Finished Mar 31 03:47:41 PM PDT 24
Peak memory 277516 kb
Host smart-d840459c-9c8d-42cc-9bac-12692b803d08
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437242515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_empt
y.437242515
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.3561731192
Short name T1088
Test name
Test status
Simulation time 2204107170 ps
CPU time 76.95 seconds
Started Mar 31 03:47:36 PM PDT 24
Finished Mar 31 03:48:53 PM PDT 24
Peak memory 732988 kb
Host smart-5dc4b38c-8bbd-47af-adb5-788a1f53b62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561731192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.3561731192
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.635310650
Short name T52
Test name
Test status
Simulation time 2310971255 ps
CPU time 69.33 seconds
Started Mar 31 03:47:44 PM PDT 24
Finished Mar 31 03:48:53 PM PDT 24
Peak memory 750696 kb
Host smart-ca0726c7-3b77-4e51-baf3-0e5f7d781309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635310650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.635310650
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.996138190
Short name T706
Test name
Test status
Simulation time 102934146 ps
CPU time 0.95 seconds
Started Mar 31 03:47:34 PM PDT 24
Finished Mar 31 03:47:35 PM PDT 24
Peak memory 203724 kb
Host smart-0f1fff03-41f6-43bd-b482-e0f8c6e5b810
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996138190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_fm
t.996138190
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.1086893342
Short name T559
Test name
Test status
Simulation time 255854659 ps
CPU time 3.35 seconds
Started Mar 31 03:47:38 PM PDT 24
Finished Mar 31 03:47:41 PM PDT 24
Peak memory 223120 kb
Host smart-6e0ce465-4e80-49c7-98ad-f95f46064e12
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086893342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx
.1086893342
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.271987179
Short name T801
Test name
Test status
Simulation time 37366918119 ps
CPU time 213.32 seconds
Started Mar 31 03:47:45 PM PDT 24
Finished Mar 31 03:51:19 PM PDT 24
Peak memory 919592 kb
Host smart-b90d9634-7573-462a-bb0c-d0dbb932f387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271987179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.271987179
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.1527668828
Short name T715
Test name
Test status
Simulation time 1413011290 ps
CPU time 16.18 seconds
Started Mar 31 03:47:43 PM PDT 24
Finished Mar 31 03:48:00 PM PDT 24
Peak memory 203796 kb
Host smart-f8d51192-58e9-4965-a530-058b8862358c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527668828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.1527668828
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.2592973081
Short name T1122
Test name
Test status
Simulation time 3047644483 ps
CPU time 79.37 seconds
Started Mar 31 03:47:45 PM PDT 24
Finished Mar 31 03:49:05 PM PDT 24
Peak memory 463776 kb
Host smart-cbb38db0-1387-41e1-95a4-cf648fef48c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592973081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.2592973081
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.3196833948
Short name T428
Test name
Test status
Simulation time 28141393 ps
CPU time 0.7 seconds
Started Mar 31 03:47:34 PM PDT 24
Finished Mar 31 03:47:36 PM PDT 24
Peak memory 203576 kb
Host smart-57072b9e-b4c3-4665-9d48-879b913757ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196833948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.3196833948
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.2678380745
Short name T38
Test name
Test status
Simulation time 9037896499 ps
CPU time 46.1 seconds
Started Mar 31 03:47:33 PM PDT 24
Finished Mar 31 03:48:19 PM PDT 24
Peak memory 203852 kb
Host smart-04654fb0-4f39-47b8-958f-8e8e34186dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678380745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.2678380745
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.3136802691
Short name T623
Test name
Test status
Simulation time 5212456961 ps
CPU time 66.75 seconds
Started Mar 31 03:47:35 PM PDT 24
Finished Mar 31 03:48:42 PM PDT 24
Peak memory 389900 kb
Host smart-69fd57fd-69be-4572-acae-f199fcaad64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136802691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.3136802691
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.1296609611
Short name T725
Test name
Test status
Simulation time 879127874 ps
CPU time 4.25 seconds
Started Mar 31 03:47:50 PM PDT 24
Finished Mar 31 03:47:54 PM PDT 24
Peak memory 212060 kb
Host smart-fc4f99ec-56ef-4bc3-b2c2-5dbb73aa8290
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296609611 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.1296609611
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.3245246542
Short name T69
Test name
Test status
Simulation time 10083048622 ps
CPU time 33.75 seconds
Started Mar 31 03:47:45 PM PDT 24
Finished Mar 31 03:48:19 PM PDT 24
Peak memory 402448 kb
Host smart-1f073862-eaae-435b-ae24-75a73a562415
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245246542 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_fifo_reset_acq.3245246542
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.2794247155
Short name T877
Test name
Test status
Simulation time 10180239912 ps
CPU time 106.84 seconds
Started Mar 31 03:47:48 PM PDT 24
Finished Mar 31 03:49:35 PM PDT 24
Peak memory 726492 kb
Host smart-353e08e7-606a-4487-8869-98f06b7581c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794247155 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.2794247155
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.1503133213
Short name T658
Test name
Test status
Simulation time 3422264789 ps
CPU time 2.37 seconds
Started Mar 31 03:47:43 PM PDT 24
Finished Mar 31 03:47:46 PM PDT 24
Peak memory 203848 kb
Host smart-08e52ba3-299a-4675-8997-d7db3ce6dae2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503133213 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_hrst.1503133213
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.558564348
Short name T925
Test name
Test status
Simulation time 672566824 ps
CPU time 3.78 seconds
Started Mar 31 03:47:35 PM PDT 24
Finished Mar 31 03:47:39 PM PDT 24
Peak memory 204396 kb
Host smart-64120459-c059-400e-b9ca-554db0cdcaa8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558564348 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_intr_smoke.558564348
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.1229695387
Short name T743
Test name
Test status
Simulation time 733177926 ps
CPU time 10.35 seconds
Started Mar 31 03:47:35 PM PDT 24
Finished Mar 31 03:47:46 PM PDT 24
Peak memory 203924 kb
Host smart-20200b19-4645-47c0-80b4-b719a67f4292
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229695387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.1229695387
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.1410115482
Short name T974
Test name
Test status
Simulation time 5191195019 ps
CPU time 20.75 seconds
Started Mar 31 03:47:35 PM PDT 24
Finished Mar 31 03:47:55 PM PDT 24
Peak memory 232140 kb
Host smart-9bf91bc6-8cae-4fad-9f15-f19128646e24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410115482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_rd.1410115482
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.1723500970
Short name T947
Test name
Test status
Simulation time 4317282642 ps
CPU time 22.07 seconds
Started Mar 31 03:47:35 PM PDT 24
Finished Mar 31 03:47:57 PM PDT 24
Peak memory 414240 kb
Host smart-bb7f1c4e-087c-4338-9253-dc4570ff0a33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723500970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_
target_stretch.1723500970
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.768963266
Short name T278
Test name
Test status
Simulation time 1438432851 ps
CPU time 6.98 seconds
Started Mar 31 03:47:45 PM PDT 24
Finished Mar 31 03:47:52 PM PDT 24
Peak memory 219536 kb
Host smart-88b02a59-ed69-4808-9100-d575425fa6fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768963266 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_timeout.768963266
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_alert_test.179587437
Short name T384
Test name
Test status
Simulation time 28839420 ps
CPU time 0.63 seconds
Started Mar 31 03:47:54 PM PDT 24
Finished Mar 31 03:47:55 PM PDT 24
Peak memory 203668 kb
Host smart-f881cedb-0faf-4ced-bbcb-413b958932b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179587437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.179587437
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.10803202
Short name T782
Test name
Test status
Simulation time 141709047 ps
CPU time 1.64 seconds
Started Mar 31 03:47:46 PM PDT 24
Finished Mar 31 03:47:48 PM PDT 24
Peak memory 212012 kb
Host smart-d681e5d3-da6c-4411-991c-cebfdd347e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10803202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.10803202
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.2617825648
Short name T726
Test name
Test status
Simulation time 264163163 ps
CPU time 5.9 seconds
Started Mar 31 03:47:47 PM PDT 24
Finished Mar 31 03:47:53 PM PDT 24
Peak memory 255108 kb
Host smart-529a0af0-3a04-4bea-ab60-8629f908a88d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617825648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_emp
ty.2617825648
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.591275812
Short name T81
Test name
Test status
Simulation time 1462979190 ps
CPU time 42.6 seconds
Started Mar 31 03:47:43 PM PDT 24
Finished Mar 31 03:48:26 PM PDT 24
Peak memory 472196 kb
Host smart-a235dc82-dcae-47d0-943c-718347fef309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591275812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.591275812
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.3137915015
Short name T446
Test name
Test status
Simulation time 1204293327 ps
CPU time 38.32 seconds
Started Mar 31 03:47:45 PM PDT 24
Finished Mar 31 03:48:23 PM PDT 24
Peak memory 475068 kb
Host smart-6f126579-9fb3-4738-9b32-2c3caea1a1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137915015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.3137915015
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.243505814
Short name T1066
Test name
Test status
Simulation time 332363278 ps
CPU time 0.9 seconds
Started Mar 31 03:47:45 PM PDT 24
Finished Mar 31 03:47:46 PM PDT 24
Peak memory 203672 kb
Host smart-8c398a17-257c-4f02-a6bd-34ad1beb1dc7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243505814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_fm
t.243505814
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.25782083
Short name T1168
Test name
Test status
Simulation time 341868839 ps
CPU time 3.73 seconds
Started Mar 31 03:47:42 PM PDT 24
Finished Mar 31 03:47:46 PM PDT 24
Peak memory 203856 kb
Host smart-14dee07f-62d5-47a5-a225-ea985ee38fc0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25782083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx.25782083
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.2445431938
Short name T331
Test name
Test status
Simulation time 5717022047 ps
CPU time 83.74 seconds
Started Mar 31 03:47:44 PM PDT 24
Finished Mar 31 03:49:08 PM PDT 24
Peak memory 915816 kb
Host smart-4aab3428-b7e3-4f88-9c87-58812b6abb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445431938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.2445431938
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.398279896
Short name T216
Test name
Test status
Simulation time 802566075 ps
CPU time 6.69 seconds
Started Mar 31 03:47:54 PM PDT 24
Finished Mar 31 03:48:01 PM PDT 24
Peak memory 203756 kb
Host smart-db43cea8-42f2-419c-b756-979155865209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398279896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.398279896
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.2350178334
Short name T931
Test name
Test status
Simulation time 3248085329 ps
CPU time 14.96 seconds
Started Mar 31 03:47:47 PM PDT 24
Finished Mar 31 03:48:02 PM PDT 24
Peak memory 270756 kb
Host smart-1f62ede6-61a1-4ee7-943b-ff08dc622fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350178334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.2350178334
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.1244597509
Short name T187
Test name
Test status
Simulation time 30259006 ps
CPU time 0.67 seconds
Started Mar 31 03:47:44 PM PDT 24
Finished Mar 31 03:47:45 PM PDT 24
Peak memory 203612 kb
Host smart-d4810c78-0c54-482c-beb8-9caa4806ed33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244597509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.1244597509
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.2756746024
Short name T366
Test name
Test status
Simulation time 6514801037 ps
CPU time 16.1 seconds
Started Mar 31 03:47:49 PM PDT 24
Finished Mar 31 03:48:05 PM PDT 24
Peak memory 317408 kb
Host smart-55c0a7da-e12f-48a0-9f7f-5a9e6111ccc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756746024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.2756746024
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.4086421772
Short name T954
Test name
Test status
Simulation time 3660084205 ps
CPU time 2.6 seconds
Started Mar 31 03:47:44 PM PDT 24
Finished Mar 31 03:47:47 PM PDT 24
Peak memory 203860 kb
Host smart-dfa02d74-fc02-4015-8e65-de2fe891fbb4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086421772 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.4086421772
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.4176308193
Short name T972
Test name
Test status
Simulation time 10054099684 ps
CPU time 107 seconds
Started Mar 31 03:47:42 PM PDT 24
Finished Mar 31 03:49:30 PM PDT 24
Peak memory 692572 kb
Host smart-d5c65568-f372-4dda-bbd2-c7c4122a3355
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176308193 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.4176308193
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.1627499742
Short name T362
Test name
Test status
Simulation time 1892072367 ps
CPU time 2.66 seconds
Started Mar 31 03:47:48 PM PDT 24
Finished Mar 31 03:47:51 PM PDT 24
Peak memory 203796 kb
Host smart-4a04beb8-8024-45b9-8286-2ad764643dc7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627499742 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_hrst.1627499742
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.1714678764
Short name T1129
Test name
Test status
Simulation time 6173793835 ps
CPU time 8.46 seconds
Started Mar 31 03:47:45 PM PDT 24
Finished Mar 31 03:47:54 PM PDT 24
Peak memory 225544 kb
Host smart-1bff268f-4acf-43a4-956d-a3cabbc66c83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714678764 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.1714678764
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.2191971622
Short name T176
Test name
Test status
Simulation time 1012761785 ps
CPU time 39.94 seconds
Started Mar 31 03:47:50 PM PDT 24
Finished Mar 31 03:48:30 PM PDT 24
Peak memory 203820 kb
Host smart-1bad7bb6-64ae-4257-b2dd-7d45d8b2bc14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191971622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_smoke.2191971622
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.922348341
Short name T357
Test name
Test status
Simulation time 2066627225 ps
CPU time 22.61 seconds
Started Mar 31 03:47:51 PM PDT 24
Finished Mar 31 03:48:14 PM PDT 24
Peak memory 203816 kb
Host smart-bb004f3d-0c30-4b96-a8d2-1c1ee76e4598
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922348341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c
_target_stress_rd.922348341
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.2458289723
Short name T570
Test name
Test status
Simulation time 18621219403 ps
CPU time 36.69 seconds
Started Mar 31 03:47:46 PM PDT 24
Finished Mar 31 03:48:23 PM PDT 24
Peak memory 203724 kb
Host smart-590cd7b5-8b55-449b-ae4c-f6c88ab39183
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458289723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_wr.2458289723
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.2104511191
Short name T920
Test name
Test status
Simulation time 39835946114 ps
CPU time 432.62 seconds
Started Mar 31 03:47:45 PM PDT 24
Finished Mar 31 03:54:58 PM PDT 24
Peak memory 2542696 kb
Host smart-56f9354f-41dd-4170-a206-cbcf03068e20
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104511191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stretch.2104511191
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.2552039708
Short name T71
Test name
Test status
Simulation time 11131710099 ps
CPU time 8.24 seconds
Started Mar 31 03:47:43 PM PDT 24
Finished Mar 31 03:47:52 PM PDT 24
Peak memory 220128 kb
Host smart-94d12b4f-c16b-4667-87fc-4b58da852dd2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552039708 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.2552039708
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_alert_test.399149584
Short name T557
Test name
Test status
Simulation time 53030694 ps
CPU time 0.63 seconds
Started Mar 31 03:47:53 PM PDT 24
Finished Mar 31 03:47:54 PM PDT 24
Peak memory 203788 kb
Host smart-01b63a89-da78-44df-bd09-ce23d9c8ca12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399149584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.399149584
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.161852237
Short name T1089
Test name
Test status
Simulation time 107853079 ps
CPU time 1.66 seconds
Started Mar 31 03:47:55 PM PDT 24
Finished Mar 31 03:47:57 PM PDT 24
Peak memory 212056 kb
Host smart-a97534bc-6b18-4536-8bba-555a0a86b623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161852237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.161852237
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.2331907508
Short name T487
Test name
Test status
Simulation time 378553727 ps
CPU time 10.11 seconds
Started Mar 31 03:47:45 PM PDT 24
Finished Mar 31 03:47:56 PM PDT 24
Peak memory 241256 kb
Host smart-6555e54c-d4f6-4aa3-a521-eee2347327d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331907508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_emp
ty.2331907508
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.1002244112
Short name T83
Test name
Test status
Simulation time 3763889232 ps
CPU time 102.14 seconds
Started Mar 31 03:47:47 PM PDT 24
Finished Mar 31 03:49:29 PM PDT 24
Peak memory 383920 kb
Host smart-cde1e5e6-b872-4b65-9541-4073f9da52ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002244112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.1002244112
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.3142513036
Short name T991
Test name
Test status
Simulation time 2955034434 ps
CPU time 33.76 seconds
Started Mar 31 03:47:53 PM PDT 24
Finished Mar 31 03:48:27 PM PDT 24
Peak memory 414108 kb
Host smart-bb44f495-13eb-4880-85cb-184214064f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142513036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.3142513036
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.2181541258
Short name T639
Test name
Test status
Simulation time 749830780 ps
CPU time 0.99 seconds
Started Mar 31 03:47:52 PM PDT 24
Finished Mar 31 03:47:53 PM PDT 24
Peak memory 203676 kb
Host smart-e9653b47-93cd-41fe-8b70-d66d91934284
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181541258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.2181541258
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.646168706
Short name T854
Test name
Test status
Simulation time 144624650 ps
CPU time 7.55 seconds
Started Mar 31 03:47:55 PM PDT 24
Finished Mar 31 03:48:04 PM PDT 24
Peak memory 203784 kb
Host smart-435490a6-e009-48e4-bfdf-4f51467db09c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646168706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx.
646168706
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.2757050786
Short name T1043
Test name
Test status
Simulation time 4406730725 ps
CPU time 108.5 seconds
Started Mar 31 03:47:48 PM PDT 24
Finished Mar 31 03:49:37 PM PDT 24
Peak memory 1254056 kb
Host smart-b1f02b63-7a75-4bc3-af0e-ad9d7da3fbd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757050786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.2757050786
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.1511761628
Short name T546
Test name
Test status
Simulation time 203159007 ps
CPU time 2.91 seconds
Started Mar 31 03:47:48 PM PDT 24
Finished Mar 31 03:47:52 PM PDT 24
Peak memory 203864 kb
Host smart-ff5b6765-036b-455e-b6a0-b3590457a777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511761628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.1511761628
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.209336782
Short name T850
Test name
Test status
Simulation time 6686218152 ps
CPU time 59 seconds
Started Mar 31 03:47:50 PM PDT 24
Finished Mar 31 03:48:49 PM PDT 24
Peak memory 349176 kb
Host smart-e9d40808-79ba-4093-9f4a-b58fd4b0ede9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209336782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.209336782
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_host_override.3709993773
Short name T1
Test name
Test status
Simulation time 31287418 ps
CPU time 0.65 seconds
Started Mar 31 03:47:51 PM PDT 24
Finished Mar 31 03:47:52 PM PDT 24
Peak memory 203612 kb
Host smart-2443d075-f41b-437a-a404-b86818dd324c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709993773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.3709993773
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.1215244929
Short name T363
Test name
Test status
Simulation time 7046971366 ps
CPU time 129.59 seconds
Started Mar 31 03:47:53 PM PDT 24
Finished Mar 31 03:50:02 PM PDT 24
Peak memory 203884 kb
Host smart-e0394a5c-4277-4113-ab48-dbd107854637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215244929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.1215244929
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.2366804615
Short name T783
Test name
Test status
Simulation time 1101957031 ps
CPU time 21.39 seconds
Started Mar 31 03:47:49 PM PDT 24
Finished Mar 31 03:48:11 PM PDT 24
Peak memory 274804 kb
Host smart-482e032d-6354-4de2-9a82-98c5a6942fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366804615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.2366804615
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.615975447
Short name T607
Test name
Test status
Simulation time 3612216322 ps
CPU time 4.47 seconds
Started Mar 31 03:47:52 PM PDT 24
Finished Mar 31 03:47:57 PM PDT 24
Peak memory 203892 kb
Host smart-0304a640-1381-40f4-80c9-9c08d2670c7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615975447 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.615975447
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.2698644703
Short name T299
Test name
Test status
Simulation time 10219891937 ps
CPU time 14.97 seconds
Started Mar 31 03:47:51 PM PDT 24
Finished Mar 31 03:48:06 PM PDT 24
Peak memory 302144 kb
Host smart-512d3b59-d74a-4d1e-ba03-749a1537d275
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698644703 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_fifo_reset_acq.2698644703
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.1532054590
Short name T714
Test name
Test status
Simulation time 10109868342 ps
CPU time 84.4 seconds
Started Mar 31 03:47:54 PM PDT 24
Finished Mar 31 03:49:19 PM PDT 24
Peak memory 646204 kb
Host smart-da9653bf-f3fc-4103-a393-f084eeb46677
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532054590 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_tx.1532054590
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.1641227356
Short name T1167
Test name
Test status
Simulation time 1116522943 ps
CPU time 1.77 seconds
Started Mar 31 03:47:47 PM PDT 24
Finished Mar 31 03:47:49 PM PDT 24
Peak memory 203804 kb
Host smart-96acee60-e5bc-46ee-8f1e-e1bc634e917a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641227356 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_hrst.1641227356
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.3053008736
Short name T302
Test name
Test status
Simulation time 1823064143 ps
CPU time 5.08 seconds
Started Mar 31 03:47:48 PM PDT 24
Finished Mar 31 03:47:54 PM PDT 24
Peak memory 204780 kb
Host smart-b4ad7406-5d95-449e-bdf7-d382ba19320f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053008736 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_intr_smoke.3053008736
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.2300250184
Short name T875
Test name
Test status
Simulation time 4826020163 ps
CPU time 11.33 seconds
Started Mar 31 03:47:53 PM PDT 24
Finished Mar 31 03:48:05 PM PDT 24
Peak memory 203708 kb
Host smart-b91710b2-3b8f-4339-86f8-8203181debb6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300250184 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.2300250184
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.3385101670
Short name T95
Test name
Test status
Simulation time 1359934573 ps
CPU time 21.36 seconds
Started Mar 31 03:47:49 PM PDT 24
Finished Mar 31 03:48:10 PM PDT 24
Peak memory 203768 kb
Host smart-87be19fa-3c0e-46c6-88fb-90d246e4dd64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385101670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta
rget_smoke.3385101670
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.1458380603
Short name T257
Test name
Test status
Simulation time 1546858058 ps
CPU time 29.73 seconds
Started Mar 31 03:47:51 PM PDT 24
Finished Mar 31 03:48:21 PM PDT 24
Peak memory 203812 kb
Host smart-7f20aedf-be17-4c30-87f3-5631ba728493
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458380603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_rd.1458380603
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.3656804300
Short name T48
Test name
Test status
Simulation time 7005664472 ps
CPU time 31.71 seconds
Started Mar 31 03:47:54 PM PDT 24
Finished Mar 31 03:48:26 PM PDT 24
Peak memory 312232 kb
Host smart-e681c952-7c7f-46f8-bc14-64b6d1fb6365
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656804300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.3656804300
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.2995425775
Short name T377
Test name
Test status
Simulation time 5523355570 ps
CPU time 7.29 seconds
Started Mar 31 03:47:50 PM PDT 24
Finished Mar 31 03:47:57 PM PDT 24
Peak memory 210680 kb
Host smart-0ae7e649-7a6d-4379-ad1a-a0dfda55508f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995425775 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.2995425775
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_alert_test.1214144774
Short name T1012
Test name
Test status
Simulation time 15972202 ps
CPU time 0.63 seconds
Started Mar 31 03:48:02 PM PDT 24
Finished Mar 31 03:48:03 PM PDT 24
Peak memory 203712 kb
Host smart-f8a3ca8c-74d8-47e5-af34-51be379be3eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214144774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.1214144774
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.1984193852
Short name T1204
Test name
Test status
Simulation time 239637857 ps
CPU time 1.35 seconds
Started Mar 31 03:48:04 PM PDT 24
Finished Mar 31 03:48:06 PM PDT 24
Peak memory 212040 kb
Host smart-301dd2c9-0ab0-4f74-b034-b2cc4c40b8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984193852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.1984193852
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.1121159834
Short name T1145
Test name
Test status
Simulation time 274576355 ps
CPU time 13.11 seconds
Started Mar 31 03:47:52 PM PDT 24
Finished Mar 31 03:48:05 PM PDT 24
Peak memory 245316 kb
Host smart-0e09b292-699e-49ef-83c4-a940509ee27d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121159834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.1121159834
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.2405625391
Short name T58
Test name
Test status
Simulation time 3257129913 ps
CPU time 120.42 seconds
Started Mar 31 03:47:53 PM PDT 24
Finished Mar 31 03:49:53 PM PDT 24
Peak memory 617792 kb
Host smart-b9a9bd43-9c12-494a-ac3f-d13312350d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405625391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.2405625391
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.825902084
Short name T682
Test name
Test status
Simulation time 4826142218 ps
CPU time 74.47 seconds
Started Mar 31 03:47:52 PM PDT 24
Finished Mar 31 03:49:07 PM PDT 24
Peak memory 470536 kb
Host smart-cecdb8d7-2689-49c2-91ca-ff92414c67fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825902084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.825902084
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.4095529403
Short name T309
Test name
Test status
Simulation time 545389418 ps
CPU time 1.32 seconds
Started Mar 31 03:47:45 PM PDT 24
Finished Mar 31 03:47:47 PM PDT 24
Peak memory 203804 kb
Host smart-40e981d5-b31e-493a-8f4d-c6251208b57c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095529403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.4095529403
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.1318001313
Short name T558
Test name
Test status
Simulation time 650039641 ps
CPU time 3.88 seconds
Started Mar 31 03:47:52 PM PDT 24
Finished Mar 31 03:47:56 PM PDT 24
Peak memory 224624 kb
Host smart-57c54d42-dffd-4052-9a29-a12b9df8cf7b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318001313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.1318001313
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.1433088644
Short name T241
Test name
Test status
Simulation time 5894541859 ps
CPU time 348.23 seconds
Started Mar 31 03:47:52 PM PDT 24
Finished Mar 31 03:53:40 PM PDT 24
Peak memory 1272896 kb
Host smart-3216602c-9e70-4809-b737-cae01a58b56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433088644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.1433088644
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.353038617
Short name T403
Test name
Test status
Simulation time 415941861 ps
CPU time 17.18 seconds
Started Mar 31 03:47:57 PM PDT 24
Finished Mar 31 03:48:14 PM PDT 24
Peak memory 203876 kb
Host smart-fec3622a-6d96-4ac1-8bb2-e0df0c2aaecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353038617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.353038617
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.157821141
Short name T1092
Test name
Test status
Simulation time 11722602529 ps
CPU time 27 seconds
Started Mar 31 03:47:56 PM PDT 24
Finished Mar 31 03:48:23 PM PDT 24
Peak memory 343244 kb
Host smart-1e57f04d-31eb-48bc-9cc4-263621f9a2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157821141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.157821141
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.2783821349
Short name T942
Test name
Test status
Simulation time 28309121 ps
CPU time 0.64 seconds
Started Mar 31 03:47:50 PM PDT 24
Finished Mar 31 03:47:50 PM PDT 24
Peak memory 203624 kb
Host smart-7befa43f-4643-4e0a-9f59-b3bdf44f4718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783821349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.2783821349
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.1640381706
Short name T1209
Test name
Test status
Simulation time 3396378054 ps
CPU time 166.5 seconds
Started Mar 31 03:47:54 PM PDT 24
Finished Mar 31 03:50:41 PM PDT 24
Peak memory 419128 kb
Host smart-035838a5-ada3-4c76-add6-00ca25505ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640381706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.1640381706
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.153534176
Short name T70
Test name
Test status
Simulation time 1096252328 ps
CPU time 49.19 seconds
Started Mar 31 03:47:53 PM PDT 24
Finished Mar 31 03:48:42 PM PDT 24
Peak memory 296572 kb
Host smart-dda32638-2161-4605-84a4-eafd95f9d5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153534176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.153534176
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.3452450778
Short name T1101
Test name
Test status
Simulation time 15407031921 ps
CPU time 1465.04 seconds
Started Mar 31 03:48:07 PM PDT 24
Finished Mar 31 04:12:32 PM PDT 24
Peak memory 3751548 kb
Host smart-32cab2f9-e3f1-450e-a044-8d870c9ed510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452450778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.3452450778
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.360852597
Short name T876
Test name
Test status
Simulation time 728580606 ps
CPU time 3.35 seconds
Started Mar 31 03:47:54 PM PDT 24
Finished Mar 31 03:47:57 PM PDT 24
Peak memory 203752 kb
Host smart-733b5dc5-f513-4bd9-9557-f9f315fb53df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360852597 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.360852597
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.1388798742
Short name T326
Test name
Test status
Simulation time 10628128519 ps
CPU time 8.46 seconds
Started Mar 31 03:47:52 PM PDT 24
Finished Mar 31 03:48:01 PM PDT 24
Peak memory 256628 kb
Host smart-ce30d1b6-759f-403c-a8e7-edf60ff34c32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388798742 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_fifo_reset_acq.1388798742
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.3431476856
Short name T63
Test name
Test status
Simulation time 10108182738 ps
CPU time 34.24 seconds
Started Mar 31 03:48:07 PM PDT 24
Finished Mar 31 03:48:41 PM PDT 24
Peak memory 441712 kb
Host smart-762c60bc-1245-4a3d-8769-ce7935399ee9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431476856 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_tx.3431476856
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.772876324
Short name T904
Test name
Test status
Simulation time 775580750 ps
CPU time 2.43 seconds
Started Mar 31 03:48:01 PM PDT 24
Finished Mar 31 03:48:04 PM PDT 24
Peak memory 203732 kb
Host smart-20837582-97a6-4711-94ec-de3f66b7b079
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772876324 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 47.i2c_target_hrst.772876324
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.3899136785
Short name T111
Test name
Test status
Simulation time 5386524567 ps
CPU time 6.77 seconds
Started Mar 31 03:47:59 PM PDT 24
Finished Mar 31 03:48:06 PM PDT 24
Peak memory 217044 kb
Host smart-cf02c0b8-6d08-4354-8495-08993ce3721e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899136785 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.3899136785
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.2144386031
Short name T1181
Test name
Test status
Simulation time 7911507485 ps
CPU time 29.17 seconds
Started Mar 31 03:47:51 PM PDT 24
Finished Mar 31 03:48:20 PM PDT 24
Peak memory 203808 kb
Host smart-804b94bc-814c-42a5-b946-ed53374f36dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144386031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_smoke.2144386031
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.851513761
Short name T849
Test name
Test status
Simulation time 6785140405 ps
CPU time 46.64 seconds
Started Mar 31 03:47:52 PM PDT 24
Finished Mar 31 03:48:39 PM PDT 24
Peak memory 204852 kb
Host smart-f08b4a80-e176-4450-b9b4-3333d74b20f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851513761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c
_target_stress_rd.851513761
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.1003693155
Short name T452
Test name
Test status
Simulation time 24635480726 ps
CPU time 36.16 seconds
Started Mar 31 03:48:01 PM PDT 24
Finished Mar 31 03:48:37 PM PDT 24
Peak memory 457128 kb
Host smart-6ce52af2-b87c-4f72-9702-4d2a72817b08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003693155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.1003693155
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.1115218617
Short name T670
Test name
Test status
Simulation time 3085221259 ps
CPU time 8.28 seconds
Started Mar 31 03:47:59 PM PDT 24
Finished Mar 31 03:48:08 PM PDT 24
Peak memory 220044 kb
Host smart-5a8a30bd-1e28-493d-9ede-72b29561ee9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115218617 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.1115218617
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_alert_test.513322450
Short name T944
Test name
Test status
Simulation time 18082213 ps
CPU time 0.62 seconds
Started Mar 31 03:47:55 PM PDT 24
Finished Mar 31 03:47:56 PM PDT 24
Peak memory 203700 kb
Host smart-dcebc9f3-bfe1-486c-852e-ce6be8d92099
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513322450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.513322450
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.2229306957
Short name T1151
Test name
Test status
Simulation time 1634613010 ps
CPU time 1.87 seconds
Started Mar 31 03:48:05 PM PDT 24
Finished Mar 31 03:48:07 PM PDT 24
Peak memory 212028 kb
Host smart-51ac12da-19d6-4c4e-be94-66de7debc0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229306957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.2229306957
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.2773112399
Short name T1116
Test name
Test status
Simulation time 442456765 ps
CPU time 2.42 seconds
Started Mar 31 03:47:59 PM PDT 24
Finished Mar 31 03:48:03 PM PDT 24
Peak memory 215784 kb
Host smart-bb0f12b5-8237-41d2-a17a-117b2cee016c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773112399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.2773112399
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.2786732086
Short name T1022
Test name
Test status
Simulation time 1483506332 ps
CPU time 94.02 seconds
Started Mar 31 03:48:11 PM PDT 24
Finished Mar 31 03:49:45 PM PDT 24
Peak memory 512456 kb
Host smart-3226a229-080a-4064-a745-f9e5b831ecd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786732086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.2786732086
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.2306414142
Short name T75
Test name
Test status
Simulation time 8894615471 ps
CPU time 84.48 seconds
Started Mar 31 03:47:58 PM PDT 24
Finished Mar 31 03:49:23 PM PDT 24
Peak memory 757228 kb
Host smart-7c2917aa-c5d8-43cd-9a83-7953affabf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306414142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.2306414142
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.2818835258
Short name T923
Test name
Test status
Simulation time 486025320 ps
CPU time 1.01 seconds
Started Mar 31 03:48:04 PM PDT 24
Finished Mar 31 03:48:06 PM PDT 24
Peak memory 203724 kb
Host smart-b06e3348-1c4c-4075-a738-61131ff3d95e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818835258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_f
mt.2818835258
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.3109771544
Short name T324
Test name
Test status
Simulation time 357562681 ps
CPU time 3.89 seconds
Started Mar 31 03:47:58 PM PDT 24
Finished Mar 31 03:48:02 PM PDT 24
Peak memory 203784 kb
Host smart-c07308c9-7a45-49ac-9310-afbcd34a20d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109771544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx
.3109771544
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.1443851989
Short name T161
Test name
Test status
Simulation time 12163753822 ps
CPU time 103.73 seconds
Started Mar 31 03:47:54 PM PDT 24
Finished Mar 31 03:49:38 PM PDT 24
Peak memory 1171560 kb
Host smart-7fbe66cb-abec-4681-a944-aae856a60ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443851989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.1443851989
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.1959710161
Short name T380
Test name
Test status
Simulation time 356171632 ps
CPU time 11.2 seconds
Started Mar 31 03:48:08 PM PDT 24
Finished Mar 31 03:48:19 PM PDT 24
Peak memory 203792 kb
Host smart-6087b426-15ac-45d9-b054-f7457803370a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959710161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.1959710161
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.2735624394
Short name T27
Test name
Test status
Simulation time 6168317849 ps
CPU time 73.46 seconds
Started Mar 31 03:48:04 PM PDT 24
Finished Mar 31 03:49:18 PM PDT 24
Peak memory 333780 kb
Host smart-2e024905-1ba8-45a4-94e2-641681d8aff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735624394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.2735624394
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.3660076606
Short name T407
Test name
Test status
Simulation time 27345650 ps
CPU time 0.66 seconds
Started Mar 31 03:48:07 PM PDT 24
Finished Mar 31 03:48:08 PM PDT 24
Peak memory 203620 kb
Host smart-acd20538-ec6d-469a-9fe2-00147904b305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660076606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.3660076606
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.3184189702
Short name T189
Test name
Test status
Simulation time 48952848327 ps
CPU time 338.71 seconds
Started Mar 31 03:48:04 PM PDT 24
Finished Mar 31 03:53:43 PM PDT 24
Peak memory 460132 kb
Host smart-300ad5fb-9a82-4dcd-91c3-a4c386eadc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184189702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.3184189702
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.2465724821
Short name T381
Test name
Test status
Simulation time 2391985104 ps
CPU time 56.03 seconds
Started Mar 31 03:48:02 PM PDT 24
Finished Mar 31 03:48:58 PM PDT 24
Peak memory 329604 kb
Host smart-958d8894-848c-45b8-b030-de9109ae1667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465724821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.2465724821
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.1709302799
Short name T1109
Test name
Test status
Simulation time 484713756 ps
CPU time 2.53 seconds
Started Mar 31 03:48:10 PM PDT 24
Finished Mar 31 03:48:13 PM PDT 24
Peak memory 203772 kb
Host smart-6645df30-4b41-4894-8c92-468cb48e717a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709302799 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.1709302799
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.836408401
Short name T760
Test name
Test status
Simulation time 10046030448 ps
CPU time 27.72 seconds
Started Mar 31 03:47:56 PM PDT 24
Finished Mar 31 03:48:24 PM PDT 24
Peak memory 361336 kb
Host smart-a3833ffc-36d4-4c95-a35c-40eef67ef4a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836408401 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_acq.836408401
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.3302210833
Short name T345
Test name
Test status
Simulation time 1694704894 ps
CPU time 2.48 seconds
Started Mar 31 03:48:09 PM PDT 24
Finished Mar 31 03:48:12 PM PDT 24
Peak memory 203848 kb
Host smart-f587fcde-3708-45dd-b47f-190c2e901651
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302210833 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_hrst.3302210833
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.4073459353
Short name T930
Test name
Test status
Simulation time 1124992004 ps
CPU time 4.9 seconds
Started Mar 31 03:48:10 PM PDT 24
Finished Mar 31 03:48:15 PM PDT 24
Peak memory 203804 kb
Host smart-64b5528d-a3c2-43e6-a941-11a7b365ebc6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073459353 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.4073459353
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.1488586855
Short name T303
Test name
Test status
Simulation time 783236108 ps
CPU time 10.14 seconds
Started Mar 31 03:48:02 PM PDT 24
Finished Mar 31 03:48:13 PM PDT 24
Peak memory 203816 kb
Host smart-3db5c984-56d7-4da6-ab8b-c9f89cd29145
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488586855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ta
rget_smoke.1488586855
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.1041354941
Short name T906
Test name
Test status
Simulation time 3551836922 ps
CPU time 17.07 seconds
Started Mar 31 03:48:06 PM PDT 24
Finished Mar 31 03:48:23 PM PDT 24
Peak memory 213208 kb
Host smart-df0425d0-76d9-4fcb-8bf1-4fab9b247c46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041354941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.1041354941
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.1429174086
Short name T806
Test name
Test status
Simulation time 33126752020 ps
CPU time 203.7 seconds
Started Mar 31 03:48:03 PM PDT 24
Finished Mar 31 03:51:27 PM PDT 24
Peak memory 1724768 kb
Host smart-16f5a9ca-6c38-4735-b1e7-b3834a7f4555
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429174086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_
target_stretch.1429174086
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.2620034327
Short name T419
Test name
Test status
Simulation time 5397727852 ps
CPU time 7.71 seconds
Started Mar 31 03:48:04 PM PDT 24
Finished Mar 31 03:48:12 PM PDT 24
Peak memory 214920 kb
Host smart-d6865ca9-3346-4171-9ce3-42ee914a5dc1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620034327 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.2620034327
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_alert_test.1685206912
Short name T430
Test name
Test status
Simulation time 16464192 ps
CPU time 0.65 seconds
Started Mar 31 03:48:07 PM PDT 24
Finished Mar 31 03:48:07 PM PDT 24
Peak memory 203664 kb
Host smart-26584311-1cc8-4fae-a6a3-f021e6541e5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685206912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.1685206912
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.1528016520
Short name T505
Test name
Test status
Simulation time 176631642 ps
CPU time 1.61 seconds
Started Mar 31 03:48:03 PM PDT 24
Finished Mar 31 03:48:05 PM PDT 24
Peak memory 212008 kb
Host smart-18442dc6-4e84-411b-9694-ea570a38d13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528016520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.1528016520
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.551023549
Short name T932
Test name
Test status
Simulation time 246616336 ps
CPU time 4.28 seconds
Started Mar 31 03:48:02 PM PDT 24
Finished Mar 31 03:48:07 PM PDT 24
Peak memory 241092 kb
Host smart-28fb0ab9-5321-4457-a0c6-f3b0a53b4da4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551023549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_empt
y.551023549
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.3901500890
Short name T858
Test name
Test status
Simulation time 1857234671 ps
CPU time 115.08 seconds
Started Mar 31 03:48:04 PM PDT 24
Finished Mar 31 03:49:59 PM PDT 24
Peak memory 553464 kb
Host smart-765d99a5-abf6-41d8-a3a6-acca7be37bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901500890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.3901500890
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.2519367500
Short name T1075
Test name
Test status
Simulation time 1407696192 ps
CPU time 102.55 seconds
Started Mar 31 03:48:07 PM PDT 24
Finished Mar 31 03:49:50 PM PDT 24
Peak memory 550632 kb
Host smart-3b854305-4068-4d8b-a9b9-3d9d10a7c0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519367500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.2519367500
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.1151180035
Short name T1050
Test name
Test status
Simulation time 225014553 ps
CPU time 0.81 seconds
Started Mar 31 03:48:08 PM PDT 24
Finished Mar 31 03:48:09 PM PDT 24
Peak memory 203672 kb
Host smart-81737994-dbfb-4191-b552-178cfe147390
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151180035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.1151180035
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.1972420832
Short name T7
Test name
Test status
Simulation time 202499360 ps
CPU time 5.59 seconds
Started Mar 31 03:48:03 PM PDT 24
Finished Mar 31 03:48:09 PM PDT 24
Peak memory 238428 kb
Host smart-be39ac9f-9b3f-4384-87f7-f0ffa5bdfd18
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972420832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.1972420832
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.457872398
Short name T23
Test name
Test status
Simulation time 2648480824 ps
CPU time 56.15 seconds
Started Mar 31 03:48:04 PM PDT 24
Finished Mar 31 03:49:00 PM PDT 24
Peak memory 797564 kb
Host smart-8942af80-a2c1-49da-a370-99df03f40536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457872398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.457872398
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.3590701004
Short name T689
Test name
Test status
Simulation time 510085750 ps
CPU time 20.64 seconds
Started Mar 31 03:48:08 PM PDT 24
Finished Mar 31 03:48:28 PM PDT 24
Peak memory 203816 kb
Host smart-7d0caeeb-b9a6-462b-b26b-ddaa640dc7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590701004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.3590701004
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.2871948578
Short name T642
Test name
Test status
Simulation time 1916554970 ps
CPU time 39.29 seconds
Started Mar 31 03:48:11 PM PDT 24
Finished Mar 31 03:48:51 PM PDT 24
Peak memory 368808 kb
Host smart-86a9d39c-2a54-42f8-8538-642f3e696b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871948578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.2871948578
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.41785274
Short name T970
Test name
Test status
Simulation time 76880356 ps
CPU time 0.72 seconds
Started Mar 31 03:48:01 PM PDT 24
Finished Mar 31 03:48:02 PM PDT 24
Peak memory 203576 kb
Host smart-988898fb-554a-4e50-9f45-67c9feebdb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41785274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.41785274
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.2260462554
Short name T1013
Test name
Test status
Simulation time 50334729686 ps
CPU time 399.88 seconds
Started Mar 31 03:48:06 PM PDT 24
Finished Mar 31 03:54:46 PM PDT 24
Peak memory 1747748 kb
Host smart-96331c5a-fd4b-4cc9-baf2-94793b607640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260462554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.2260462554
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.1671243209
Short name T507
Test name
Test status
Simulation time 6936238892 ps
CPU time 93.05 seconds
Started Mar 31 03:48:04 PM PDT 24
Finished Mar 31 03:49:38 PM PDT 24
Peak memory 416796 kb
Host smart-41a30677-78c0-4a9c-a73b-0409c2313c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671243209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.1671243209
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.1838436419
Short name T1098
Test name
Test status
Simulation time 3622631255 ps
CPU time 3.75 seconds
Started Mar 31 03:48:02 PM PDT 24
Finished Mar 31 03:48:06 PM PDT 24
Peak memory 203924 kb
Host smart-8b2f8c6b-5a88-4b99-a78d-ddc3c1e9f144
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838436419 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.1838436419
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.2296455419
Short name T681
Test name
Test status
Simulation time 10232405989 ps
CPU time 34.55 seconds
Started Mar 31 03:48:05 PM PDT 24
Finished Mar 31 03:48:40 PM PDT 24
Peak memory 404236 kb
Host smart-befba5df-ec9e-4e7a-af2a-92274e730991
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296455419 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.2296455419
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.1447043345
Short name T413
Test name
Test status
Simulation time 11455500810 ps
CPU time 7.22 seconds
Started Mar 31 03:48:08 PM PDT 24
Finished Mar 31 03:48:15 PM PDT 24
Peak memory 249564 kb
Host smart-def0481a-ae39-4871-85d4-c9526f6b58e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447043345 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_tx.1447043345
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.1619983875
Short name T983
Test name
Test status
Simulation time 8729159952 ps
CPU time 2.54 seconds
Started Mar 31 03:48:07 PM PDT 24
Finished Mar 31 03:48:10 PM PDT 24
Peak memory 203672 kb
Host smart-4a6848ab-dfeb-472a-81ee-30501f44e154
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619983875 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_hrst.1619983875
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.1744893776
Short name T445
Test name
Test status
Simulation time 3729469356 ps
CPU time 5.03 seconds
Started Mar 31 03:47:59 PM PDT 24
Finished Mar 31 03:48:05 PM PDT 24
Peak memory 206832 kb
Host smart-7ee82cf5-185d-49e8-a7e5-955b21041a20
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744893776 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.1744893776
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.2014866042
Short name T655
Test name
Test status
Simulation time 3752800253 ps
CPU time 1.74 seconds
Started Mar 31 03:48:03 PM PDT 24
Finished Mar 31 03:48:05 PM PDT 24
Peak memory 203892 kb
Host smart-6baca7a8-e654-433e-a050-99584d8dff0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014866042 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.2014866042
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.800780660
Short name T753
Test name
Test status
Simulation time 928188761 ps
CPU time 11.84 seconds
Started Mar 31 03:48:03 PM PDT 24
Finished Mar 31 03:48:15 PM PDT 24
Peak memory 203812 kb
Host smart-c44b94d1-d353-4caf-a628-68bdf7c9a81b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800780660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_tar
get_smoke.800780660
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.2156103702
Short name T280
Test name
Test status
Simulation time 1942894828 ps
CPU time 5.26 seconds
Started Mar 31 03:48:02 PM PDT 24
Finished Mar 31 03:48:08 PM PDT 24
Peak memory 203832 kb
Host smart-4adadec6-9927-4f43-93f5-fdf48ad646cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156103702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.2156103702
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.1283294906
Short name T575
Test name
Test status
Simulation time 16815431970 ps
CPU time 24.42 seconds
Started Mar 31 03:48:05 PM PDT 24
Finished Mar 31 03:48:30 PM PDT 24
Peak memory 409048 kb
Host smart-b642538b-2f35-461e-8e7a-7b5e263f9597
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283294906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_
target_stretch.1283294906
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.3826446890
Short name T551
Test name
Test status
Simulation time 6525135790 ps
CPU time 7.34 seconds
Started Mar 31 03:48:04 PM PDT 24
Finished Mar 31 03:48:11 PM PDT 24
Peak memory 212112 kb
Host smart-b6f3e3e9-86b8-4ecb-add6-4feca0805e8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826446890 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_timeout.3826446890
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_alert_test.614179412
Short name T864
Test name
Test status
Simulation time 28799710 ps
CPU time 0.58 seconds
Started Mar 31 03:44:16 PM PDT 24
Finished Mar 31 03:44:17 PM PDT 24
Peak memory 203740 kb
Host smart-cfe058cc-4938-49ac-aa4d-291187cc85e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614179412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.614179412
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.3722581897
Short name T205
Test name
Test status
Simulation time 97610740 ps
CPU time 1.59 seconds
Started Mar 31 03:44:03 PM PDT 24
Finished Mar 31 03:44:05 PM PDT 24
Peak memory 212020 kb
Host smart-4b23acbe-b9b1-4fa5-b85d-f7002fd3b23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722581897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.3722581897
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.134494194
Short name T396
Test name
Test status
Simulation time 1980074529 ps
CPU time 3.7 seconds
Started Mar 31 03:44:06 PM PDT 24
Finished Mar 31 03:44:10 PM PDT 24
Peak memory 225184 kb
Host smart-6040eac9-3a5f-4f22-b550-af587910d1dc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134494194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empty
.134494194
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.1773827841
Short name T90
Test name
Test status
Simulation time 3483701692 ps
CPU time 72.5 seconds
Started Mar 31 03:44:06 PM PDT 24
Finished Mar 31 03:45:19 PM PDT 24
Peak memory 479664 kb
Host smart-db49beae-df60-419b-b73a-c1317002ca39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773827841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.1773827841
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.3730991533
Short name T679
Test name
Test status
Simulation time 1743533285 ps
CPU time 118.26 seconds
Started Mar 31 03:44:06 PM PDT 24
Finished Mar 31 03:46:05 PM PDT 24
Peak memory 595036 kb
Host smart-f9eadcdc-f637-46f5-9604-665a33587297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730991533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.3730991533
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.1729545997
Short name T254
Test name
Test status
Simulation time 98153486 ps
CPU time 0.83 seconds
Started Mar 31 03:44:04 PM PDT 24
Finished Mar 31 03:44:05 PM PDT 24
Peak memory 203688 kb
Host smart-5e269a52-dcaf-4b5d-9ccf-b92d4b0eb3a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729545997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.1729545997
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.134855736
Short name T342
Test name
Test status
Simulation time 570528714 ps
CPU time 4.64 seconds
Started Mar 31 03:44:06 PM PDT 24
Finished Mar 31 03:44:11 PM PDT 24
Peak memory 231412 kb
Host smart-a4e7ad95-6b19-4919-a393-628880c2c4f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134855736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.134855736
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.416577232
Short name T975
Test name
Test status
Simulation time 21998120548 ps
CPU time 87.47 seconds
Started Mar 31 03:44:03 PM PDT 24
Finished Mar 31 03:45:31 PM PDT 24
Peak memory 1078760 kb
Host smart-d149a3fc-1b3a-4ff3-8513-532f2660b558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416577232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.416577232
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.3526177126
Short name T18
Test name
Test status
Simulation time 289526557 ps
CPU time 4.48 seconds
Started Mar 31 03:44:15 PM PDT 24
Finished Mar 31 03:44:20 PM PDT 24
Peak memory 203792 kb
Host smart-45820afd-88cb-4446-af76-ce20dce2625c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526177126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.3526177126
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.1380968227
Short name T592
Test name
Test status
Simulation time 1655522209 ps
CPU time 94.64 seconds
Started Mar 31 03:44:14 PM PDT 24
Finished Mar 31 03:45:48 PM PDT 24
Peak memory 460704 kb
Host smart-834e5653-eaa9-4074-a964-a41ab50b762b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380968227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.1380968227
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.2021814740
Short name T927
Test name
Test status
Simulation time 26178431 ps
CPU time 0.67 seconds
Started Mar 31 03:44:04 PM PDT 24
Finished Mar 31 03:44:05 PM PDT 24
Peak memory 203588 kb
Host smart-b05130fe-40cf-432c-b4b9-d51feff35471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021814740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.2021814740
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.1594382428
Short name T793
Test name
Test status
Simulation time 2510491529 ps
CPU time 37.02 seconds
Started Mar 31 03:44:04 PM PDT 24
Finished Mar 31 03:44:41 PM PDT 24
Peak memory 203900 kb
Host smart-7e3feeb2-6995-431a-96c2-78b5ce8226a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594382428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.1594382428
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.3188673557
Short name T456
Test name
Test status
Simulation time 13494047719 ps
CPU time 26.39 seconds
Started Mar 31 03:44:02 PM PDT 24
Finished Mar 31 03:44:29 PM PDT 24
Peak memory 404932 kb
Host smart-c3016023-0a0e-41a7-8edb-abf1347dac81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188673557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.3188673557
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.3436217690
Short name T540
Test name
Test status
Simulation time 3164581134 ps
CPU time 2.96 seconds
Started Mar 31 03:44:20 PM PDT 24
Finished Mar 31 03:44:24 PM PDT 24
Peak memory 203828 kb
Host smart-b21b1783-5c2c-4a40-b7ca-1bf2b3a6ea6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436217690 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.3436217690
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.363869088
Short name T195
Test name
Test status
Simulation time 11341966347 ps
CPU time 4.7 seconds
Started Mar 31 03:44:15 PM PDT 24
Finished Mar 31 03:44:20 PM PDT 24
Peak memory 235980 kb
Host smart-130fc9fc-b373-4454-a15a-57d5a9785ebe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363869088 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_acq.363869088
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.1387919574
Short name T805
Test name
Test status
Simulation time 10385135244 ps
CPU time 15.76 seconds
Started Mar 31 03:44:19 PM PDT 24
Finished Mar 31 03:44:35 PM PDT 24
Peak memory 337924 kb
Host smart-64c054c2-83b2-40d9-bd6a-48db86173713
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387919574 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_tx.1387919574
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.1933846379
Short name T42
Test name
Test status
Simulation time 2564066880 ps
CPU time 2.56 seconds
Started Mar 31 03:44:11 PM PDT 24
Finished Mar 31 03:44:14 PM PDT 24
Peak memory 203828 kb
Host smart-bb937e48-54a7-4ee8-99c8-2c816846fa0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933846379 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_hrst.1933846379
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.3191366934
Short name T1173
Test name
Test status
Simulation time 1065997204 ps
CPU time 5.54 seconds
Started Mar 31 03:44:07 PM PDT 24
Finished Mar 31 03:44:13 PM PDT 24
Peak memory 211988 kb
Host smart-c20aed93-0e04-4433-9535-d1be6bbb87a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191366934 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_intr_smoke.3191366934
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.280443354
Short name T341
Test name
Test status
Simulation time 4234379086 ps
CPU time 16.16 seconds
Started Mar 31 03:44:04 PM PDT 24
Finished Mar 31 03:44:20 PM PDT 24
Peak memory 203872 kb
Host smart-09abe329-ce8f-4cfa-a7db-167e8f3f5baa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280443354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_targ
et_smoke.280443354
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.4083289676
Short name T1182
Test name
Test status
Simulation time 506216758 ps
CPU time 20.47 seconds
Started Mar 31 03:44:06 PM PDT 24
Finished Mar 31 03:44:27 PM PDT 24
Peak memory 203788 kb
Host smart-eef42ae1-5573-4acc-819e-85b0590f2981
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083289676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.4083289676
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.3834241339
Short name T1063
Test name
Test status
Simulation time 6037819910 ps
CPU time 7.42 seconds
Started Mar 31 03:44:14 PM PDT 24
Finished Mar 31 03:44:21 PM PDT 24
Peak memory 210860 kb
Host smart-b2ef7051-0fe3-47b2-93fb-fc81e86b2d32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834241339 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.3834241339
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_alert_test.1262946149
Short name T1047
Test name
Test status
Simulation time 18837447 ps
CPU time 0.61 seconds
Started Mar 31 03:44:18 PM PDT 24
Finished Mar 31 03:44:18 PM PDT 24
Peak memory 203688 kb
Host smart-c0cd150a-a36f-4713-982b-0466e20240ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262946149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.1262946149
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.439895420
Short name T1042
Test name
Test status
Simulation time 74502823 ps
CPU time 1.45 seconds
Started Mar 31 03:44:15 PM PDT 24
Finished Mar 31 03:44:16 PM PDT 24
Peak memory 212172 kb
Host smart-4dda3e01-07df-4ae7-962e-89cf0c8b9cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439895420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.439895420
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.926194878
Short name T274
Test name
Test status
Simulation time 448474842 ps
CPU time 2.95 seconds
Started Mar 31 03:44:20 PM PDT 24
Finished Mar 31 03:44:23 PM PDT 24
Peak memory 223092 kb
Host smart-95bb12e0-ce61-487d-a160-39d022489116
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926194878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empty
.926194878
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.1582708707
Short name T953
Test name
Test status
Simulation time 1218122738 ps
CPU time 32.08 seconds
Started Mar 31 03:44:11 PM PDT 24
Finished Mar 31 03:44:43 PM PDT 24
Peak memory 490828 kb
Host smart-92ee2f16-9fb2-4de1-9d99-055ca8d3b138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582708707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.1582708707
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.2499155816
Short name T468
Test name
Test status
Simulation time 6679510853 ps
CPU time 45.66 seconds
Started Mar 31 03:44:20 PM PDT 24
Finished Mar 31 03:45:06 PM PDT 24
Peak memory 583784 kb
Host smart-d9f07e65-7675-4fca-a6f9-99b4112a821a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499155816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.2499155816
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.4061900113
Short name T500
Test name
Test status
Simulation time 160532533 ps
CPU time 0.89 seconds
Started Mar 31 03:44:10 PM PDT 24
Finished Mar 31 03:44:11 PM PDT 24
Peak memory 203632 kb
Host smart-5f9f14b6-cd08-426a-a0ef-8fb929cd582e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061900113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fm
t.4061900113
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.3310076954
Short name T1039
Test name
Test status
Simulation time 115907609 ps
CPU time 3.09 seconds
Started Mar 31 03:44:10 PM PDT 24
Finished Mar 31 03:44:13 PM PDT 24
Peak memory 218748 kb
Host smart-6d7b32b9-3e91-40e1-82e3-63fc7e644ed0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310076954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
3310076954
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.3451871047
Short name T327
Test name
Test status
Simulation time 22460334278 ps
CPU time 147.56 seconds
Started Mar 31 03:44:12 PM PDT 24
Finished Mar 31 03:46:39 PM PDT 24
Peak memory 763692 kb
Host smart-7bce9480-964b-4e37-93ef-045d89265d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451871047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.3451871047
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.1134199271
Short name T298
Test name
Test status
Simulation time 879453350 ps
CPU time 17.99 seconds
Started Mar 31 03:44:16 PM PDT 24
Finished Mar 31 03:44:34 PM PDT 24
Peak memory 203792 kb
Host smart-5570a936-8ac1-448a-8003-d906cae2cb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134199271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.1134199271
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.3735417376
Short name T1203
Test name
Test status
Simulation time 6732371711 ps
CPU time 69 seconds
Started Mar 31 03:44:20 PM PDT 24
Finished Mar 31 03:45:30 PM PDT 24
Peak memory 331728 kb
Host smart-66ad406e-7f8a-4b11-9359-018868b8481e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735417376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.3735417376
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.1192702080
Short name T819
Test name
Test status
Simulation time 29127564 ps
CPU time 0.67 seconds
Started Mar 31 03:44:15 PM PDT 24
Finished Mar 31 03:44:16 PM PDT 24
Peak memory 203620 kb
Host smart-3e0e3017-0a53-4681-92e1-66732a7b9ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192702080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.1192702080
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.184426259
Short name T896
Test name
Test status
Simulation time 2887880773 ps
CPU time 38.27 seconds
Started Mar 31 03:44:09 PM PDT 24
Finished Mar 31 03:44:47 PM PDT 24
Peak memory 378372 kb
Host smart-43381598-4bc5-4be2-b07b-5b397da055c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184426259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.184426259
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.2158878200
Short name T946
Test name
Test status
Simulation time 4379532131 ps
CPU time 23.87 seconds
Started Mar 31 03:44:15 PM PDT 24
Finished Mar 31 03:44:39 PM PDT 24
Peak memory 340264 kb
Host smart-d33f4857-5858-480b-a60d-1072d76cdf60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158878200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.2158878200
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stress_all.3729721808
Short name T22
Test name
Test status
Simulation time 21339759381 ps
CPU time 602.44 seconds
Started Mar 31 03:44:09 PM PDT 24
Finished Mar 31 03:54:12 PM PDT 24
Peak memory 2195872 kb
Host smart-f4e0fa65-90db-49c7-8abd-7b9630a13109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729721808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.3729721808
Directory /workspace/6.i2c_host_stress_all/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.3223409359
Short name T2
Test name
Test status
Simulation time 774857761 ps
CPU time 2.68 seconds
Started Mar 31 03:44:16 PM PDT 24
Finished Mar 31 03:44:19 PM PDT 24
Peak memory 203828 kb
Host smart-d6188825-3d80-45f2-9729-41edfb936ed0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223409359 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.3223409359
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.1239272944
Short name T1025
Test name
Test status
Simulation time 10054956773 ps
CPU time 35.96 seconds
Started Mar 31 03:44:11 PM PDT 24
Finished Mar 31 03:44:47 PM PDT 24
Peak memory 479412 kb
Host smart-854d36e9-49e7-4b09-83c4-db783a005867
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239272944 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_tx.1239272944
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.3383646474
Short name T49
Test name
Test status
Simulation time 732721950 ps
CPU time 2.28 seconds
Started Mar 31 03:44:18 PM PDT 24
Finished Mar 31 03:44:20 PM PDT 24
Peak memory 203816 kb
Host smart-358033ca-e2f0-4a4e-a40b-e166479df1d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383646474 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_hrst.3383646474
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.2950096799
Short name T968
Test name
Test status
Simulation time 8055860471 ps
CPU time 4.51 seconds
Started Mar 31 03:44:10 PM PDT 24
Finished Mar 31 03:44:15 PM PDT 24
Peak memory 203908 kb
Host smart-d5285166-344c-4c65-affa-e81baedd402d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950096799 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.2950096799
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.3655423592
Short name T907
Test name
Test status
Simulation time 3745557776 ps
CPU time 15.13 seconds
Started Mar 31 03:44:11 PM PDT 24
Finished Mar 31 03:44:26 PM PDT 24
Peak memory 203792 kb
Host smart-ab0e9b4f-1e2d-4603-8a4f-c97d7b7ddeb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655423592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_smoke.3655423592
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.2572338157
Short name T898
Test name
Test status
Simulation time 2308761882 ps
CPU time 49.58 seconds
Started Mar 31 03:44:17 PM PDT 24
Finished Mar 31 03:45:07 PM PDT 24
Peak memory 204956 kb
Host smart-ae4d7f55-f17e-469d-8971-6518fe50a810
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572338157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.2572338157
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.1437492667
Short name T441
Test name
Test status
Simulation time 29685009113 ps
CPU time 705.82 seconds
Started Mar 31 03:44:15 PM PDT 24
Finished Mar 31 03:56:07 PM PDT 24
Peak memory 3688372 kb
Host smart-f14d65c0-5cab-4570-9ee2-ae6028a2942f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437492667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_t
arget_stretch.1437492667
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.3013975234
Short name T814
Test name
Test status
Simulation time 5845673227 ps
CPU time 6.48 seconds
Started Mar 31 03:44:16 PM PDT 24
Finished Mar 31 03:44:22 PM PDT 24
Peak memory 212176 kb
Host smart-78db55a1-4091-4650-b916-a51f4f1bfe05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013975234 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_timeout.3013975234
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_alert_test.2159015118
Short name T596
Test name
Test status
Simulation time 21909053 ps
CPU time 0.61 seconds
Started Mar 31 03:44:29 PM PDT 24
Finished Mar 31 03:44:30 PM PDT 24
Peak memory 203680 kb
Host smart-25ef58bc-a2fe-4103-a49e-63c0bd4cde99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159015118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.2159015118
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.997091132
Short name T204
Test name
Test status
Simulation time 87158016 ps
CPU time 1.68 seconds
Started Mar 31 03:44:16 PM PDT 24
Finished Mar 31 03:44:18 PM PDT 24
Peak memory 212024 kb
Host smart-ac6d2d83-b383-4614-8d0b-279f9343da43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997091132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.997091132
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.108075078
Short name T401
Test name
Test status
Simulation time 1410613596 ps
CPU time 18.57 seconds
Started Mar 31 03:44:15 PM PDT 24
Finished Mar 31 03:44:34 PM PDT 24
Peak memory 279860 kb
Host smart-b6b9b690-83b2-4912-ac5d-b3fc98de7691
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108075078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empty
.108075078
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.509629989
Short name T1009
Test name
Test status
Simulation time 2112846484 ps
CPU time 147.14 seconds
Started Mar 31 03:44:16 PM PDT 24
Finished Mar 31 03:46:43 PM PDT 24
Peak memory 662056 kb
Host smart-b871cf5c-476a-4544-a20c-ae5b07612bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509629989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.509629989
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.285795407
Short name T518
Test name
Test status
Simulation time 1333039504 ps
CPU time 38.75 seconds
Started Mar 31 03:44:14 PM PDT 24
Finished Mar 31 03:44:53 PM PDT 24
Peak memory 528444 kb
Host smart-4261217f-4559-4647-a264-6730c974378b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285795407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.285795407
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.201937218
Short name T375
Test name
Test status
Simulation time 126662302 ps
CPU time 1.12 seconds
Started Mar 31 03:44:20 PM PDT 24
Finished Mar 31 03:44:22 PM PDT 24
Peak memory 203812 kb
Host smart-e3a40400-ec1c-4df7-944c-23eb0a7a1146
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201937218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fmt
.201937218
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.2036006847
Short name T844
Test name
Test status
Simulation time 1391850046 ps
CPU time 3.57 seconds
Started Mar 31 03:44:18 PM PDT 24
Finished Mar 31 03:44:22 PM PDT 24
Peak memory 203768 kb
Host smart-ae009e95-88ab-4740-a06f-2a861088bc02
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036006847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
2036006847
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.638872277
Short name T322
Test name
Test status
Simulation time 538440340 ps
CPU time 6.73 seconds
Started Mar 31 03:44:30 PM PDT 24
Finished Mar 31 03:44:37 PM PDT 24
Peak memory 203872 kb
Host smart-da84df63-4bbc-4b96-955d-e1f772002970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638872277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.638872277
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.1039785641
Short name T372
Test name
Test status
Simulation time 9835612315 ps
CPU time 26.58 seconds
Started Mar 31 03:44:21 PM PDT 24
Finished Mar 31 03:44:48 PM PDT 24
Peak memory 384556 kb
Host smart-d401de82-0c24-4311-89d8-9d524df5716f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039785641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.1039785641
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.631855627
Short name T795
Test name
Test status
Simulation time 29301480 ps
CPU time 0.73 seconds
Started Mar 31 03:44:19 PM PDT 24
Finished Mar 31 03:44:19 PM PDT 24
Peak memory 203612 kb
Host smart-ba8d18a4-f9e5-4e6a-b402-5a42cfaf1a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631855627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.631855627
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.2497559178
Short name T645
Test name
Test status
Simulation time 27661948898 ps
CPU time 413.93 seconds
Started Mar 31 03:44:21 PM PDT 24
Finished Mar 31 03:51:15 PM PDT 24
Peak memory 1841496 kb
Host smart-ff7122e2-2886-4e5c-8a96-e334fb2de574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497559178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.2497559178
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.2268165179
Short name T677
Test name
Test status
Simulation time 1554101620 ps
CPU time 30.59 seconds
Started Mar 31 03:44:16 PM PDT 24
Finished Mar 31 03:44:47 PM PDT 24
Peak memory 346572 kb
Host smart-d75f9589-3fa8-4b83-91da-e9126272b6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268165179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.2268165179
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.2033218008
Short name T1058
Test name
Test status
Simulation time 1471758614 ps
CPU time 2.29 seconds
Started Mar 31 03:44:29 PM PDT 24
Finished Mar 31 03:44:32 PM PDT 24
Peak memory 203840 kb
Host smart-4e291b6b-dce4-44ec-8030-da0ecbda54a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033218008 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.2033218008
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.1689351947
Short name T976
Test name
Test status
Simulation time 10065996134 ps
CPU time 84 seconds
Started Mar 31 03:44:16 PM PDT 24
Finished Mar 31 03:45:40 PM PDT 24
Peak memory 572588 kb
Host smart-5e930cf7-3b62-40a2-bd2a-33ede29cfac1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689351947 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_fifo_reset_acq.1689351947
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.2267785982
Short name T1033
Test name
Test status
Simulation time 10055917816 ps
CPU time 96.33 seconds
Started Mar 31 03:44:32 PM PDT 24
Finished Mar 31 03:46:09 PM PDT 24
Peak memory 703304 kb
Host smart-3f88412f-7a7b-4b30-a6a9-5fbed6fcc54c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267785982 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.2267785982
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_hrst.2702743096
Short name T249
Test name
Test status
Simulation time 1088199013 ps
CPU time 2.72 seconds
Started Mar 31 03:44:25 PM PDT 24
Finished Mar 31 03:44:28 PM PDT 24
Peak memory 203780 kb
Host smart-67268ccb-108f-4c14-a567-477efe724b68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702743096 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_hrst.2702743096
Directory /workspace/7.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.4202947800
Short name T266
Test name
Test status
Simulation time 1063073105 ps
CPU time 5.43 seconds
Started Mar 31 03:44:19 PM PDT 24
Finished Mar 31 03:44:25 PM PDT 24
Peak memory 217036 kb
Host smart-c01e56d1-7659-4e2c-b048-6312512265d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202947800 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.4202947800
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.2161431021
Short name T752
Test name
Test status
Simulation time 5831701369 ps
CPU time 13.98 seconds
Started Mar 31 03:44:20 PM PDT 24
Finished Mar 31 03:44:35 PM PDT 24
Peak memory 203856 kb
Host smart-97b625b4-8075-4752-8abd-794c444d5271
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161431021 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.2161431021
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.2306503369
Short name T96
Test name
Test status
Simulation time 1421484557 ps
CPU time 33.03 seconds
Started Mar 31 03:44:18 PM PDT 24
Finished Mar 31 03:44:51 PM PDT 24
Peak memory 203792 kb
Host smart-5cd008dd-4303-4c44-a2bd-202d26f86c0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306503369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar
get_smoke.2306503369
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.2108763867
Short name T1079
Test name
Test status
Simulation time 1469952248 ps
CPU time 13.71 seconds
Started Mar 31 03:44:19 PM PDT 24
Finished Mar 31 03:44:33 PM PDT 24
Peak memory 203816 kb
Host smart-5f61ff6f-0f8e-4d87-a4d2-25ed3eded759
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108763867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_rd.2108763867
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.3657655826
Short name T755
Test name
Test status
Simulation time 13636848127 ps
CPU time 7.99 seconds
Started Mar 31 03:44:19 PM PDT 24
Finished Mar 31 03:44:27 PM PDT 24
Peak memory 203852 kb
Host smart-752b3104-40ef-47bb-aa24-0e36d3dc5616
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657655826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_wr.3657655826
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.3985039073
Short name T273
Test name
Test status
Simulation time 26846622537 ps
CPU time 1343.44 seconds
Started Mar 31 03:44:16 PM PDT 24
Finished Mar 31 04:06:40 PM PDT 24
Peak memory 4950652 kb
Host smart-c8b97904-ae81-45f6-a3b2-0a5e882c2573
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985039073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stretch.3985039073
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.978468061
Short name T545
Test name
Test status
Simulation time 1713238623 ps
CPU time 7.88 seconds
Started Mar 31 03:44:20 PM PDT 24
Finished Mar 31 03:44:28 PM PDT 24
Peak memory 212016 kb
Host smart-2b992e86-35d0-4525-806b-663d2a582b4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978468061 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_timeout.978468061
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_alert_test.2854357538
Short name T885
Test name
Test status
Simulation time 16442243 ps
CPU time 0.65 seconds
Started Mar 31 03:44:27 PM PDT 24
Finished Mar 31 03:44:28 PM PDT 24
Peak memory 203708 kb
Host smart-5684d018-55e2-4164-a050-6763a5808d7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854357538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.2854357538
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.82933701
Short name T277
Test name
Test status
Simulation time 454679689 ps
CPU time 1.17 seconds
Started Mar 31 03:44:24 PM PDT 24
Finished Mar 31 03:44:27 PM PDT 24
Peak memory 203880 kb
Host smart-cd3652a2-035b-429d-acc2-9c72622404ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82933701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.82933701
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.3869543168
Short name T910
Test name
Test status
Simulation time 1863445930 ps
CPU time 7.9 seconds
Started Mar 31 03:44:26 PM PDT 24
Finished Mar 31 03:44:34 PM PDT 24
Peak memory 225064 kb
Host smart-a92d2df4-f9ce-43dc-9469-bc570b3f8ff5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869543168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empt
y.3869543168
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.1378378494
Short name T823
Test name
Test status
Simulation time 2022592071 ps
CPU time 139.59 seconds
Started Mar 31 03:44:25 PM PDT 24
Finished Mar 31 03:46:45 PM PDT 24
Peak memory 681276 kb
Host smart-5b161025-7d2c-4adc-be6c-b20bc5fb4f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378378494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.1378378494
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.360854787
Short name T72
Test name
Test status
Simulation time 5350534758 ps
CPU time 34.79 seconds
Started Mar 31 03:44:29 PM PDT 24
Finished Mar 31 03:45:04 PM PDT 24
Peak memory 408620 kb
Host smart-b5e538ba-2922-402a-ad05-b4c8899bb599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360854787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.360854787
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.3155403128
Short name T1164
Test name
Test status
Simulation time 97765855 ps
CPU time 0.87 seconds
Started Mar 31 03:44:31 PM PDT 24
Finished Mar 31 03:44:32 PM PDT 24
Peak memory 203684 kb
Host smart-4bda7c59-30b9-4080-914c-de2cf7ea2545
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155403128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.3155403128
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.2128355632
Short name T1080
Test name
Test status
Simulation time 239482958 ps
CPU time 6.57 seconds
Started Mar 31 03:44:39 PM PDT 24
Finished Mar 31 03:44:46 PM PDT 24
Peak memory 203776 kb
Host smart-07e6b7d8-725a-4c62-a1c9-c42541286ee6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128355632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
2128355632
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.1216788405
Short name T561
Test name
Test status
Simulation time 4026207808 ps
CPU time 69.45 seconds
Started Mar 31 03:44:21 PM PDT 24
Finished Mar 31 03:45:31 PM PDT 24
Peak memory 832864 kb
Host smart-5b0b5b89-fc7b-4337-8c84-c3cac67ee049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216788405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.1216788405
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.2337766315
Short name T19
Test name
Test status
Simulation time 2129021326 ps
CPU time 4.87 seconds
Started Mar 31 03:44:32 PM PDT 24
Finished Mar 31 03:44:37 PM PDT 24
Peak memory 203844 kb
Host smart-57028b5b-d19d-4cc0-bde8-424d12872b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337766315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.2337766315
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_override.4045177980
Short name T1076
Test name
Test status
Simulation time 47508337 ps
CPU time 0.72 seconds
Started Mar 31 03:44:30 PM PDT 24
Finished Mar 31 03:44:31 PM PDT 24
Peak memory 203560 kb
Host smart-3a071fe5-4503-4c24-b32c-b710c2a768a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045177980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.4045177980
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.3531446696
Short name T777
Test name
Test status
Simulation time 72475128301 ps
CPU time 130.9 seconds
Started Mar 31 03:44:25 PM PDT 24
Finished Mar 31 03:46:37 PM PDT 24
Peak memory 203912 kb
Host smart-fed7f502-b9e4-4ff2-a381-1739ae73a5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531446696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.3531446696
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.334667455
Short name T246
Test name
Test status
Simulation time 4076511910 ps
CPU time 102.39 seconds
Started Mar 31 03:44:24 PM PDT 24
Finished Mar 31 03:46:08 PM PDT 24
Peak memory 357636 kb
Host smart-7a01386a-3163-469c-b2be-5dba44804ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334667455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.334667455
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.3860883167
Short name T116
Test name
Test status
Simulation time 2137348843 ps
CPU time 2.97 seconds
Started Mar 31 03:44:36 PM PDT 24
Finished Mar 31 03:44:39 PM PDT 24
Peak memory 203796 kb
Host smart-2e4e2045-dffe-4b24-9d4d-e1391b74c470
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860883167 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.3860883167
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.456410876
Short name T242
Test name
Test status
Simulation time 10046077649 ps
CPU time 76.05 seconds
Started Mar 31 03:44:37 PM PDT 24
Finished Mar 31 03:45:54 PM PDT 24
Peak memory 571092 kb
Host smart-3f8e2f3d-0605-4fc8-bb1f-b75589e61040
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456410876 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_acq.456410876
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.2992531484
Short name T60
Test name
Test status
Simulation time 10082981261 ps
CPU time 107.58 seconds
Started Mar 31 03:44:25 PM PDT 24
Finished Mar 31 03:46:13 PM PDT 24
Peak memory 686964 kb
Host smart-5b5d3fb6-497f-45dc-b501-ed4a2070dcae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992531484 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.2992531484
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.2074090013
Short name T1147
Test name
Test status
Simulation time 323930917 ps
CPU time 2.23 seconds
Started Mar 31 03:44:26 PM PDT 24
Finished Mar 31 03:44:29 PM PDT 24
Peak memory 203764 kb
Host smart-12ffabff-60cb-4df4-913c-e064e0f5b19f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074090013 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_hrst.2074090013
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.3415069631
Short name T652
Test name
Test status
Simulation time 3594986362 ps
CPU time 4.58 seconds
Started Mar 31 03:44:22 PM PDT 24
Finished Mar 31 03:44:27 PM PDT 24
Peak memory 203892 kb
Host smart-f7a56cf3-13e9-416b-adef-6c3b2d7827b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415069631 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.3415069631
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.3954808641
Short name T506
Test name
Test status
Simulation time 18759614498 ps
CPU time 6.52 seconds
Started Mar 31 03:44:28 PM PDT 24
Finished Mar 31 03:44:35 PM PDT 24
Peak memory 203848 kb
Host smart-f5cedb71-0d42-4ac7-84b8-55b508a92ee1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954808641 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.3954808641
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.246409532
Short name T538
Test name
Test status
Simulation time 1713325658 ps
CPU time 12.44 seconds
Started Mar 31 03:44:28 PM PDT 24
Finished Mar 31 03:44:42 PM PDT 24
Peak memory 203668 kb
Host smart-0eadb6a1-d071-47f9-b570-d8df8fc9ed2f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246409532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_targ
et_smoke.246409532
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.3729620100
Short name T272
Test name
Test status
Simulation time 478978331 ps
CPU time 19.39 seconds
Started Mar 31 03:44:23 PM PDT 24
Finished Mar 31 03:44:43 PM PDT 24
Peak memory 203808 kb
Host smart-64158b3d-babe-4a10-9e21-211094ea5bf3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729620100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_rd.3729620100
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.3600739994
Short name T353
Test name
Test status
Simulation time 19992870094 ps
CPU time 11.3 seconds
Started Mar 31 03:44:21 PM PDT 24
Finished Mar 31 03:44:32 PM PDT 24
Peak memory 203784 kb
Host smart-81bf6606-e647-453a-9aad-8356303888ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600739994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_wr.3600739994
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.2823019902
Short name T429
Test name
Test status
Simulation time 15318849597 ps
CPU time 29.06 seconds
Started Mar 31 03:44:28 PM PDT 24
Finished Mar 31 03:44:58 PM PDT 24
Peak memory 475512 kb
Host smart-2e14e84b-f966-4cb4-800a-6a49a7e9fed3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823019902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.2823019902
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.1859685045
Short name T696
Test name
Test status
Simulation time 1544646625 ps
CPU time 6.92 seconds
Started Mar 31 03:44:26 PM PDT 24
Finished Mar 31 03:44:33 PM PDT 24
Peak memory 210524 kb
Host smart-82bc4345-2f5b-45a8-89d8-9c88def6623c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859685045 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.1859685045
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_unexp_stop.1362571982
Short name T770
Test name
Test status
Simulation time 787897771 ps
CPU time 4.84 seconds
Started Mar 31 03:44:27 PM PDT 24
Finished Mar 31 03:44:32 PM PDT 24
Peak memory 204804 kb
Host smart-1ff4eed2-c034-4151-889d-5efc760e96b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362571982 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.i2c_target_unexp_stop.1362571982
Directory /workspace/8.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/9.i2c_alert_test.2420933985
Short name T1195
Test name
Test status
Simulation time 48104378 ps
CPU time 0.61 seconds
Started Mar 31 03:44:38 PM PDT 24
Finished Mar 31 03:44:39 PM PDT 24
Peak memory 203692 kb
Host smart-24ff7d9f-a386-45c0-88df-9b9066af69eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420933985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.2420933985
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.837117317
Short name T724
Test name
Test status
Simulation time 154599634 ps
CPU time 1.26 seconds
Started Mar 31 03:44:31 PM PDT 24
Finished Mar 31 03:44:32 PM PDT 24
Peak memory 212084 kb
Host smart-a6eddebc-16ea-4618-8f73-844ab4e7ea8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837117317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.837117317
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.2589512381
Short name T1161
Test name
Test status
Simulation time 1050537101 ps
CPU time 16.96 seconds
Started Mar 31 03:44:33 PM PDT 24
Finished Mar 31 03:44:51 PM PDT 24
Peak memory 269300 kb
Host smart-881b5094-56ed-4e4a-bf77-63ff9b1f5bf2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589512381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.2589512381
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.304413057
Short name T361
Test name
Test status
Simulation time 5397768069 ps
CPU time 74.26 seconds
Started Mar 31 03:44:26 PM PDT 24
Finished Mar 31 03:45:40 PM PDT 24
Peak memory 308632 kb
Host smart-eb7481c4-6df7-43f2-b7cb-4834b42fe956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304413057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.304413057
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.4208669237
Short name T980
Test name
Test status
Simulation time 1300308894 ps
CPU time 43.07 seconds
Started Mar 31 03:44:30 PM PDT 24
Finished Mar 31 03:45:13 PM PDT 24
Peak memory 520372 kb
Host smart-9db8741d-f6d8-4e53-b843-742970f45a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208669237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.4208669237
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.4110839122
Short name T420
Test name
Test status
Simulation time 76398441 ps
CPU time 0.86 seconds
Started Mar 31 03:44:28 PM PDT 24
Finished Mar 31 03:44:30 PM PDT 24
Peak memory 203668 kb
Host smart-d5fee46d-e9ff-4ff1-aa38-975463cdbd49
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110839122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm
t.4110839122
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.541926615
Short name T434
Test name
Test status
Simulation time 2164618448 ps
CPU time 7.98 seconds
Started Mar 31 03:44:36 PM PDT 24
Finished Mar 31 03:44:44 PM PDT 24
Peak memory 203896 kb
Host smart-a995d301-756a-4aec-8675-192eae97cd0b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541926615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.541926615
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.1305780981
Short name T1014
Test name
Test status
Simulation time 15461632348 ps
CPU time 278.75 seconds
Started Mar 31 03:44:26 PM PDT 24
Finished Mar 31 03:49:05 PM PDT 24
Peak memory 1128508 kb
Host smart-f90c8833-35ce-4747-97cc-69cdc1118b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305780981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.1305780981
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.1046362431
Short name T510
Test name
Test status
Simulation time 1422436676 ps
CPU time 14.77 seconds
Started Mar 31 03:44:40 PM PDT 24
Finished Mar 31 03:44:56 PM PDT 24
Peak memory 203880 kb
Host smart-2d011a80-0599-4d08-82da-0a27f8686da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046362431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.1046362431
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.3124086300
Short name T307
Test name
Test status
Simulation time 6007264405 ps
CPU time 29.54 seconds
Started Mar 31 03:44:31 PM PDT 24
Finished Mar 31 03:45:01 PM PDT 24
Peak memory 369280 kb
Host smart-fef5bd4a-2939-41cf-bf84-5c8e527e933a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124086300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.3124086300
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.2261184504
Short name T188
Test name
Test status
Simulation time 61650859 ps
CPU time 0.68 seconds
Started Mar 31 03:44:33 PM PDT 24
Finished Mar 31 03:44:34 PM PDT 24
Peak memory 203576 kb
Host smart-62881307-9f89-4a4a-bb3e-503951b66d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261184504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.2261184504
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.1969522295
Short name T860
Test name
Test status
Simulation time 6461872198 ps
CPU time 136.45 seconds
Started Mar 31 03:44:33 PM PDT 24
Finished Mar 31 03:46:49 PM PDT 24
Peak memory 237300 kb
Host smart-0e75192c-fe84-4c64-9863-a15ed911f1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969522295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.1969522295
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.3889096773
Short name T1114
Test name
Test status
Simulation time 4358299044 ps
CPU time 38.12 seconds
Started Mar 31 03:44:40 PM PDT 24
Finished Mar 31 03:45:19 PM PDT 24
Peak memory 368760 kb
Host smart-64f91633-ec82-43a9-ab69-9f0498e2f68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889096773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.3889096773
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.3894088871
Short name T563
Test name
Test status
Simulation time 664172437 ps
CPU time 3.67 seconds
Started Mar 31 03:44:37 PM PDT 24
Finished Mar 31 03:44:41 PM PDT 24
Peak memory 203800 kb
Host smart-b19f799e-6295-4a66-86e3-8fd0b34cc605
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894088871 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.3894088871
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.2527573274
Short name T465
Test name
Test status
Simulation time 10335741542 ps
CPU time 16.72 seconds
Started Mar 31 03:44:34 PM PDT 24
Finished Mar 31 03:44:51 PM PDT 24
Peak memory 293708 kb
Host smart-c686fe2f-1395-4c8c-a95d-5e718b1b4cb4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527573274 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_reset_acq.2527573274
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.1143844812
Short name T1130
Test name
Test status
Simulation time 10618153440 ps
CPU time 17.02 seconds
Started Mar 31 03:44:32 PM PDT 24
Finished Mar 31 03:44:50 PM PDT 24
Peak memory 316680 kb
Host smart-a4006ccb-6978-42b1-aa42-ab2a2a86f55b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143844812 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_tx.1143844812
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.326758862
Short name T1197
Test name
Test status
Simulation time 514339940 ps
CPU time 1.87 seconds
Started Mar 31 03:44:37 PM PDT 24
Finished Mar 31 03:44:39 PM PDT 24
Peak memory 203860 kb
Host smart-2dfc703e-e553-4c1d-952a-2896cee1cee6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326758862 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 9.i2c_target_hrst.326758862
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.1114197416
Short name T438
Test name
Test status
Simulation time 8508891321 ps
CPU time 5.09 seconds
Started Mar 31 03:44:32 PM PDT 24
Finished Mar 31 03:44:37 PM PDT 24
Peak memory 209840 kb
Host smart-7e4f032c-adf1-475f-85f6-41844ea973e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114197416 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.1114197416
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.556731431
Short name T926
Test name
Test status
Simulation time 4729977025 ps
CPU time 11.1 seconds
Started Mar 31 03:44:24 PM PDT 24
Finished Mar 31 03:44:36 PM PDT 24
Peak memory 203896 kb
Host smart-916eb669-f2c4-4bbb-b7af-6a47756bfac6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556731431 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.556731431
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.3031943672
Short name T464
Test name
Test status
Simulation time 11691319205 ps
CPU time 43.96 seconds
Started Mar 31 03:44:31 PM PDT 24
Finished Mar 31 03:45:15 PM PDT 24
Peak memory 203856 kb
Host smart-b8f7efbb-9085-4652-ae9b-3fb983245251
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031943672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_smoke.3031943672
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.1649794199
Short name T521
Test name
Test status
Simulation time 1972389256 ps
CPU time 3.95 seconds
Started Mar 31 03:44:29 PM PDT 24
Finished Mar 31 03:44:34 PM PDT 24
Peak memory 203784 kb
Host smart-6137478b-a580-43f6-a889-a430293f7bac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649794199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_rd.1649794199
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.3691262053
Short name T1011
Test name
Test status
Simulation time 13526362089 ps
CPU time 7.97 seconds
Started Mar 31 03:44:31 PM PDT 24
Finished Mar 31 03:44:39 PM PDT 24
Peak memory 203668 kb
Host smart-028228d0-0d02-497b-9648-acc631fe9ae5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691262053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_wr.3691262053
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.4230661201
Short name T1146
Test name
Test status
Simulation time 11208892807 ps
CPU time 20.1 seconds
Started Mar 31 03:44:27 PM PDT 24
Finished Mar 31 03:44:47 PM PDT 24
Peak memory 371792 kb
Host smart-2b968811-63c6-448f-a837-bca35aff7b9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230661201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_t
arget_stretch.4230661201
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.3387836061
Short name T275
Test name
Test status
Simulation time 14799306937 ps
CPU time 7.18 seconds
Started Mar 31 03:44:26 PM PDT 24
Finished Mar 31 03:44:33 PM PDT 24
Peak memory 212044 kb
Host smart-e6a5eb3e-78c2-4a95-bf61-7307682ce420
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387836061 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_timeout.3387836061
Directory /workspace/9.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_unexp_stop.1439764895
Short name T543
Test name
Test status
Simulation time 2840078881 ps
CPU time 4.9 seconds
Started Mar 31 03:44:30 PM PDT 24
Finished Mar 31 03:44:35 PM PDT 24
Peak memory 203920 kb
Host smart-28473798-a963-405b-a5c1-c3144cca7a34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439764895 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.i2c_target_unexp_stop.1439764895
Directory /workspace/9.i2c_target_unexp_stop/latest
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