Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
94.44	94.44	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	94.44	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.44	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	3	24	88.89

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	3	24	88.89	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

104387

1

T7

91

T18

11

T49

185

ack

8334

1

T7

1

T17

27

T18

4

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	435	1			T7	1		T49	1		T16	1
high	23444	1			T7	18		T17	2		T18	6
med	42154	1			T7	34		T17	3		T18	3
sml	46220	1			T7	39		T17	22		T18	6
all_zero	468	1			T44	2		T21	7		T57	5

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56529

1

T7

36

T17

15

T18

11

auto[1]

56192

1

T7

56

T17

12

T18

4

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

76775

1

T7

69

T17

15

T18

12

auto[1]

35946

1

T7

23

T17

12

T18

3

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

108130

1

T7

92

T17

8

T18

14

auto[1]

4591

1

T17

19

T18

1

T16

33

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

107290

1

T7

91

T17

19

T18

12

auto[1]

5431

1

T7

1

T17

8

T18

3

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

107879

1

T7

91

T17

20

T18

13

auto[1]

4842

1

T7

1

T17

7

T18

2

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56529

1

T7

36

T17

15

T18

11

auto[1]

56192

1

T7

56

T17

12

T18

4

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

76775

1

T7

69

T17

15

T18

12

auto[1]

35946

1

T7

23

T17

12

T18

3

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

108130

1

T7

92

T17

8

T18

14

auto[1]

4591

1

T17

19

T18

1

T16

33

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

107290

1

T7

91

T17

19

T18

12

auto[1]

5431

1

T7

1

T17

8

T18

3

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

107879

1

T7

91

T17

20

T18

13

auto[1]

4842

1

T7

1

T17

7

T18

2

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	3	24	88.89	1
Automatically Generated Cross Bins	15	1	14	93.33	1
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

cp_fbyte	start	stop	read	rcont	nakok	cp_ack	COUNT	AT LEAST	NUMBER	STATUS
[all_ones]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[ack]	0	1	1

Covered bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

6

1

T57

1

T151

1

T217

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

1

1

T218

1

-

-

-

-

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

104

1

T21

6

T57

1

T36

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

46

1

T85

1

T28

1

T219

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

64

1

T44

1

T21

4

T57

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

256

1

T21

5

T57

2

T36

4

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

124

1

T21

4

T84

2

T85

2

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

120

1

T21

1

T57

2

T219

4

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

224

1

T21

7

T57

5

T84

3

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

119

1

T21

2

T57

2

T85

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

122

1

T44

1

T21

3

T57

2

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

1

1

T220

1

-

-

-

-

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

1

1

T59

1

-

-

-

-

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

1

1

T221

1

-

-

-

-

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	33687	1			T7	26		T18	6		T49	60
write_address_byte	5431	1			T7	1		T17	8		T18	3
read_with_ack	1619	1			T17	12		T16	18		T44	4
read_with_nack	2972	1			T17	7		T18	1		T16	15
stop_byte	4842	1			T7	1		T17	7		T18	2
write_address_byte_nak	2316	1			T44	5		T21	48		T57	26
data_byte_nack	104387	1			T7	91		T18	11		T49	185
stop_byte_nack	2810	1			T7	1		T18	1		T49	13
nakok_byte_nack	52028	1			T7	56		T18	3		T49	84
nakok_addr_byte_nack	1135	1			T44	3		T21	23		T57	15