Summary for Variable RStart_before_read_data_ACK_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for RStart_before_read_data_ACK_cp
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| Start_before_read_data_ACK_Nack |
20708 |
1 |
|
|
T1 |
35 |
|
T2 |
11 |
|
T3 |
7 |
Summary for Variable RStart_during_address_Ack_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
1 |
0 |
0.00 |
User Defined Bins for RStart_during_address_Ack_cp
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| Start_during_address_Acknowledge |
0 |
1 |
1 |
|
Summary for Variable RStart_during_address_transmission_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for RStart_during_address_transmission_cp
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| Start_during_address_transmission |
17 |
1 |
|
|
T50 |
1 |
|
T51 |
1 |
|
T201 |
1 |
Summary for Variable RStart_during_read_data_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for RStart_during_read_data_cp
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| Start_during_read_data |
110 |
1 |
|
|
T40 |
12 |
|
T41 |
10 |
|
T42 |
13 |
Summary for Variable RStart_during_rw_bit_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
1 |
0 |
0.00 |
User Defined Bins for RStart_during_rw_bit_cp
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| Start_during_rw_bit |
0 |
1 |
1 |
|
Summary for Variable RStart_during_write_data_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for RStart_during_write_data_cp
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| Start_during_write_data |
14135 |
1 |
|
|
T1 |
27 |
|
T2 |
5 |
|
T3 |
8 |
Summary for Variable Read_data_ack_before_stop_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for Read_data_ack_before_stop_cp
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| Read_data_ack_before_stop |
25 |
1 |
|
|
T40 |
3 |
|
T41 |
3 |
|
T42 |
1 |
Summary for Variable Rstart_after_Address_Ack_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
1 |
0 |
0.00 |
User Defined Bins for Rstart_after_Address_Ack_cp
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| Rstart_after_Address_Ack |
0 |
1 |
1 |
|
Summary for Variable Rstart_after_Address_Nack_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for Rstart_after_Address_Nack_cp
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| Rstart_after_Address_Nack |
74 |
1 |
|
|
T27 |
2 |
|
T28 |
4 |
|
T29 |
1 |
Summary for Variable Start_followed_by_Rstart_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
1 |
0 |
1 |
100.00 |
Automatically Generated Bins for Start_followed_by_Rstart_cp
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| unused |
0 |
Excluded |
| [auto[0]] |
0 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
6 |
1 |
|
|
T202 |
3 |
|
T203 |
1 |
|
T149 |
2 |
Summary for Variable Stop_after_read_data_Nack_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for Stop_after_read_data_Nack_cp
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| Stop_after_read_data_Nack |
12233 |
1 |
|
|
T1 |
21 |
|
T2 |
5 |
|
T6 |
10 |
Summary for Variable Stop_after_read_data_ack_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for Stop_after_read_data_ack_cp
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| Stop_after_read_data_ack |
25 |
1 |
|
|
T40 |
3 |
|
T41 |
3 |
|
T42 |
1 |
Summary for Variable Stop_after_write_data_Nack_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for Stop_after_write_data_Nack_cp
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| Stop_after_write_data_Nack |
68 |
1 |
|
|
T18 |
1 |
|
T28 |
2 |
|
T29 |
2 |
Summary for Variable Stop_after_write_data_ack_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for Stop_after_write_data_ack_cp
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| Stop_after_write_data_ack |
6540 |
1 |
|
|
T1 |
18 |
|
T2 |
2 |
|
T3 |
3 |
Summary for Variable Stop_without_ACK_after_addr_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for Stop_without_ACK_after_addr_cp
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| Stop_without_ACK_after_addr |
11 |
1 |
|
|
T204 |
1 |
|
T205 |
1 |
|
T206 |
1 |
Summary for Variable Stop_without_ACK_after_data_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for Stop_without_ACK_after_data_cp
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| Stop_without_ACK_after_data |
4823 |
1 |
|
|
T1 |
18 |
|
T2 |
2 |
|
T3 |
3 |
Summary for Variable Stop_without_ACK_after_read_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
1 |
0 |
0.00 |
User Defined Bins for Stop_without_ACK_after_read_cp
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| Stop_without_ACK_after_read |
0 |
1 |
1 |
|
Summary for Variable Stop_without_ACK_after_write_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
1 |
0 |
0.00 |
User Defined Bins for Stop_without_ACK_after_write_cp
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| Stop_without_ACK_after_write |
0 |
1 |
1 |
|
Summary for Variable bus_state_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
17 |
0 |
17 |
100.00 |
User Defined Bins for bus_state_cp
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| idle |
219664 |
1 |
|
|
T1 |
1 |
|
T2 |
349 |
|
T3 |
2 |
| stop |
19629 |
1 |
|
|
T1 |
39 |
|
T2 |
10 |
|
T3 |
4 |
| write_data_nack |
29120 |
1 |
|
|
T18 |
209 |
|
T27 |
152 |
|
T28 |
263 |
| write_data_ack |
844038 |
1 |
|
|
T1 |
919 |
|
T2 |
223 |
|
T3 |
373 |
| read_data_nack |
151342 |
1 |
|
|
T1 |
193 |
|
T2 |
53 |
|
T3 |
21 |
| read_data_ack |
1485225 |
1 |
|
|
T1 |
888 |
|
T2 |
469 |
|
T3 |
142 |
| write_data |
5759395 |
1 |
|
|
T1 |
6810 |
|
T2 |
1647 |
|
T3 |
3088 |
| read_data |
10411183 |
1 |
|
|
T1 |
6559 |
|
T2 |
3129 |
|
T3 |
971 |
| write_addr_nack |
33146 |
1 |
|
|
T27 |
356 |
|
T28 |
1530 |
|
T29 |
195 |
| write_addr_ack |
72837 |
1 |
|
|
T1 |
155 |
|
T2 |
29 |
|
T3 |
33 |
| read_addr_nack |
69688 |
1 |
|
|
T27 |
3460 |
|
T28 |
1030 |
|
T29 |
984 |
| read_addr_ack |
117612 |
1 |
|
|
T1 |
198 |
|
T2 |
56 |
|
T3 |
26 |
| write |
86295 |
1 |
|
|
T1 |
180 |
|
T2 |
32 |
|
T3 |
48 |
| read |
101530 |
1 |
|
|
T1 |
171 |
|
T2 |
48 |
|
T3 |
21 |
| addr |
1160496 |
1 |
|
|
T1 |
2248 |
|
T2 |
731 |
|
T3 |
480 |
| rstart |
92681 |
1 |
|
|
T1 |
156 |
|
T2 |
66 |
|
T3 |
45 |
| start |
52784 |
1 |
|
|
T1 |
101 |
|
T2 |
28 |
|
T3 |
14 |
Summary for Variable ip_mode_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for ip_mode_cp
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| device |
11040493 |
1 |
|
|
T1 |
18618 |
|
T2 |
6870 |
|
T3 |
5268 |
| host |
9666172 |
1 |
|
|
T4 |
8 |
|
T7 |
2260 |
|
T17 |
15488 |
Summary for Variable num_rd_bytes_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
5 |
0 |
5 |
100.00 |
User Defined Bins for num_rd_bytes_cp
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| sixtyfour |
39022 |
1 |
|
|
T17 |
26 |
|
T16 |
92 |
|
T44 |
64 |
| high |
1368366 |
1 |
|
|
T17 |
808 |
|
T16 |
1943 |
|
T44 |
1669 |
| mid |
2101814 |
1 |
|
|
T2 |
29 |
|
T3 |
164 |
|
T6 |
583 |
| low |
6244838 |
1 |
|
|
T1 |
5188 |
|
T2 |
2921 |
|
T3 |
707 |
| one |
787723 |
1 |
|
|
T1 |
1239 |
|
T2 |
372 |
|
T3 |
123 |
Summary for Variable num_wr_bytes_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
5 |
0 |
5 |
100.00 |
User Defined Bins for num_wr_bytes_cp
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| sixtyfour |
14213 |
1 |
|
|
T7 |
24 |
|
T44 |
74 |
|
T21 |
577 |
| high |
623314 |
1 |
|
|
T7 |
492 |
|
T44 |
1464 |
|
T21 |
16670 |
| mid |
879233 |
1 |
|
|
T3 |
122 |
|
T6 |
28 |
|
T7 |
544 |
| low |
3745357 |
1 |
|
|
T1 |
5492 |
|
T2 |
1437 |
|
T3 |
2728 |
| one |
532663 |
1 |
|
|
T1 |
1116 |
|
T2 |
228 |
|
T3 |
316 |
Summary for Cross bus_state_x_ip_mode_cp
Samples crossed: bus_state_cp ip_mode_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
34 |
3 |
31 |
91.18 |
3 |
Automatically Generated Cross Bins for bus_state_x_ip_mode_cp
Uncovered bins
| bus_state_cp | ip_mode_cp | COUNT | AT LEAST | NUMBER | STATUS |
| [write_data_nack] |
[device] |
0 |
1 |
1 |
|
| [write_addr_nack] |
[device] |
0 |
1 |
1 |
|
| [read_addr_nack] |
[device] |
0 |
1 |
1 |
|
Covered bins
| bus_state_cp | ip_mode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| idle |
device |
217276 |
1 |
|
|
T1 |
1 |
|
T2 |
349 |
|
T3 |
2 |
| idle |
host |
2388 |
1 |
|
|
T4 |
8 |
|
T7 |
1 |
|
T17 |
1 |
| stop |
device |
11556 |
1 |
|
|
T1 |
39 |
|
T2 |
10 |
|
T3 |
4 |
| stop |
host |
8073 |
1 |
|
|
T17 |
26 |
|
T18 |
2 |
|
T49 |
12 |
| write_data_nack |
host |
29120 |
1 |
|
|
T18 |
209 |
|
T27 |
152 |
|
T28 |
263 |
| write_data_ack |
device |
488815 |
1 |
|
|
T1 |
919 |
|
T2 |
223 |
|
T3 |
373 |
| write_data_ack |
host |
355223 |
1 |
|
|
T7 |
320 |
|
T18 |
4 |
|
T49 |
651 |
| read_data_nack |
device |
88730 |
1 |
|
|
T1 |
193 |
|
T2 |
53 |
|
T3 |
21 |
| read_data_nack |
host |
62612 |
1 |
|
|
T17 |
108 |
|
T18 |
7354 |
|
T16 |
196 |
| read_data_ack |
device |
661870 |
1 |
|
|
T1 |
888 |
|
T2 |
469 |
|
T3 |
142 |
| read_data_ack |
host |
823355 |
1 |
|
|
T17 |
1750 |
|
T18 |
8 |
|
T16 |
3247 |
| write_data |
device |
3626197 |
1 |
|
|
T1 |
6810 |
|
T2 |
1647 |
|
T3 |
3088 |
| write_data |
host |
2133198 |
1 |
|
|
T7 |
1912 |
|
T18 |
58 |
|
T49 |
3907 |
| read_data |
device |
4498964 |
1 |
|
|
T1 |
6559 |
|
T2 |
3129 |
|
T3 |
971 |
| read_data |
host |
5912219 |
1 |
|
|
T17 |
12887 |
|
T18 |
88 |
|
T16 |
24089 |
| write_addr_nack |
host |
33146 |
1 |
|
|
T27 |
356 |
|
T28 |
1530 |
|
T29 |
195 |
| write_addr_ack |
device |
65213 |
1 |
|
|
T1 |
155 |
|
T2 |
29 |
|
T3 |
33 |
| write_addr_ack |
host |
7624 |
1 |
|
|
T7 |
3 |
|
T49 |
43 |
|
T16 |
4 |
| read_addr_nack |
host |
69688 |
1 |
|
|
T27 |
3460 |
|
T28 |
1030 |
|
T29 |
984 |
| read_addr_ack |
device |
96195 |
1 |
|
|
T1 |
198 |
|
T2 |
56 |
|
T3 |
26 |
| read_addr_ack |
host |
21417 |
1 |
|
|
T17 |
96 |
|
T16 |
171 |
|
T44 |
9 |
| write |
device |
76497 |
1 |
|
|
T1 |
180 |
|
T2 |
32 |
|
T3 |
48 |
| write |
host |
9798 |
1 |
|
|
T7 |
4 |
|
T18 |
8 |
|
T49 |
52 |
| read |
device |
82521 |
1 |
|
|
T1 |
171 |
|
T2 |
48 |
|
T3 |
21 |
| read |
host |
19009 |
1 |
|
|
T17 |
81 |
|
T18 |
6 |
|
T16 |
147 |
| addr |
device |
1004235 |
1 |
|
|
T1 |
2248 |
|
T2 |
731 |
|
T3 |
480 |
| addr |
host |
156261 |
1 |
|
|
T7 |
18 |
|
T17 |
472 |
|
T18 |
63 |
| rstart |
device |
91785 |
1 |
|
|
T1 |
156 |
|
T2 |
66 |
|
T3 |
45 |
| rstart |
host |
896 |
1 |
|
|
T18 |
3 |
|
T21 |
31 |
|
T36 |
23 |
| start |
device |
30639 |
1 |
|
|
T1 |
101 |
|
T2 |
28 |
|
T3 |
14 |
| start |
host |
22145 |
1 |
|
|
T7 |
2 |
|
T17 |
67 |
|
T18 |
8 |
Summary for Cross num_rd_bytes_x_ip_mode_cp
Samples crossed: ip_mode_cp num_rd_bytes_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
10 |
0 |
10 |
100.00 |
|
Automatically Generated Cross Bins for num_rd_bytes_x_ip_mode_cp
Bins
| ip_mode_cp | num_rd_bytes_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| device |
sixtyfour |
100 |
1 |
|
|
T207 |
24 |
|
T208 |
24 |
|
T209 |
24 |
| device |
high |
10182 |
1 |
|
|
T61 |
79 |
|
T67 |
4 |
|
T63 |
242 |
| device |
mid |
231758 |
1 |
|
|
T2 |
29 |
|
T3 |
164 |
|
T6 |
583 |
| device |
low |
3837656 |
1 |
|
|
T1 |
5188 |
|
T2 |
2921 |
|
T3 |
707 |
| device |
one |
597041 |
1 |
|
|
T1 |
1239 |
|
T2 |
372 |
|
T3 |
123 |
| host |
sixtyfour |
38922 |
1 |
|
|
T17 |
26 |
|
T16 |
92 |
|
T44 |
64 |
| host |
high |
1358184 |
1 |
|
|
T17 |
808 |
|
T16 |
1943 |
|
T44 |
1669 |
| host |
mid |
1870056 |
1 |
|
|
T17 |
3916 |
|
T16 |
6229 |
|
T44 |
1816 |
| host |
low |
2407182 |
1 |
|
|
T17 |
7899 |
|
T18 |
7369 |
|
T16 |
15498 |
| host |
one |
190682 |
1 |
|
|
T17 |
599 |
|
T18 |
38 |
|
T16 |
1258 |
Summary for Cross num_wr_bytes_x_ip_mode_cp
Samples crossed: ip_mode_cp num_wr_bytes_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
10 |
0 |
10 |
100.00 |
|
Automatically Generated Cross Bins for num_wr_bytes_x_ip_mode_cp
Bins
| ip_mode_cp | num_wr_bytes_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| device |
sixtyfour |
50 |
1 |
|
|
T210 |
24 |
|
T211 |
26 |
|
- |
- |
| device |
high |
6844 |
1 |
|
|
T79 |
167 |
|
T41 |
2170 |
|
T212 |
222 |
| device |
mid |
174069 |
1 |
|
|
T3 |
122 |
|
T6 |
28 |
|
T10 |
234 |
| device |
low |
2991915 |
1 |
|
|
T1 |
5492 |
|
T2 |
1437 |
|
T3 |
2728 |
| device |
one |
473469 |
1 |
|
|
T1 |
1116 |
|
T2 |
228 |
|
T3 |
316 |
| host |
sixtyfour |
14163 |
1 |
|
|
T7 |
24 |
|
T44 |
74 |
|
T21 |
577 |
| host |
high |
616470 |
1 |
|
|
T7 |
492 |
|
T44 |
1464 |
|
T21 |
16670 |
| host |
mid |
705164 |
1 |
|
|
T7 |
544 |
|
T49 |
761 |
|
T44 |
1640 |
| host |
low |
753442 |
1 |
|
|
T7 |
490 |
|
T18 |
105 |
|
T49 |
3221 |
| host |
one |
59194 |
1 |
|
|
T7 |
24 |
|
T18 |
129 |
|
T49 |
303 |
Summary for Cross Stop_after_write_data_ack_x_ip_mode_cp
Samples crossed: Stop_after_write_data_ack_cp ip_mode_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
Automatically Generated Cross Bins for Stop_after_write_data_ack_x_ip_mode_cp
Bins
| Stop_after_write_data_ack_cp | ip_mode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| Stop_after_write_data_ack |
device |
4786 |
1 |
|
|
T1 |
18 |
|
T2 |
2 |
|
T3 |
3 |
| Stop_after_write_data_ack |
host |
1754 |
1 |
|
|
T49 |
12 |
|
T16 |
1 |
|
T44 |
2 |
Summary for Cross Stop_after_read_data_ack_x_ip_mode_cp
Samples crossed: Stop_after_read_data_ack_cp ip_mode_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
2 |
1 |
1 |
50.00 |
1 |
Automatically Generated Cross Bins for Stop_after_read_data_ack_x_ip_mode_cp
Element holes
| Stop_after_read_data_ack_cp | ip_mode_cp | COUNT | AT LEAST | NUMBER | STATUS |
| * |
[host] |
0 |
1 |
1 |
|
Covered bins
| Stop_after_read_data_ack_cp | ip_mode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| Stop_after_read_data_ack |
device |
25 |
1 |
|
|
T40 |
3 |
|
T41 |
3 |
|
T42 |
1 |
Summary for Cross Stop_after_write_data_Nack_x_ip_mode_cp
Samples crossed: Stop_after_write_data_Nack_cp ip_mode_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
2 |
1 |
1 |
50.00 |
1 |
Automatically Generated Cross Bins for Stop_after_write_data_Nack_x_ip_mode_cp
Element holes
| Stop_after_write_data_Nack_cp | ip_mode_cp | COUNT | AT LEAST | NUMBER | STATUS |
| * |
[device] |
0 |
1 |
1 |
|
Covered bins
| Stop_after_write_data_Nack_cp | ip_mode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| Stop_after_write_data_Nack |
host |
68 |
1 |
|
|
T18 |
1 |
|
T28 |
2 |
|
T29 |
2 |
Summary for Cross Stop_after_read_data_Nack_x_ip_mode_cp
Samples crossed: Stop_after_read_data_Nack_cp ip_mode_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
Automatically Generated Cross Bins for Stop_after_read_data_Nack_x_ip_mode_cp
Bins
| Stop_after_read_data_Nack_cp | ip_mode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| Stop_after_read_data_Nack |
device |
6395 |
1 |
|
|
T1 |
21 |
|
T2 |
5 |
|
T6 |
10 |
| Stop_after_read_data_Nack |
host |
5838 |
1 |
|
|
T17 |
26 |
|
T18 |
1 |
|
T16 |
48 |
Summary for Cross Rstart_after_Address_Ack_x_ip_mode_cp
Samples crossed: Rstart_after_Address_Ack_cp ip_mode_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
2 |
2 |
0 |
0.00 |
2 |
Automatically Generated Cross Bins for Rstart_after_Address_Ack_x_ip_mode_cp
Uncovered bins
| Rstart_after_Address_Ack_cp | ip_mode_cp | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
2 |
|
Summary for Cross Rstart_after_Address_Nack_x_ip_mode_cp
Samples crossed: Rstart_after_Address_Nack_cp ip_mode_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
2 |
1 |
1 |
50.00 |
1 |
Automatically Generated Cross Bins for Rstart_after_Address_Nack_x_ip_mode_cp
Element holes
| Rstart_after_Address_Nack_cp | ip_mode_cp | COUNT | AT LEAST | NUMBER | STATUS |
| * |
[device] |
0 |
1 |
1 |
|
Covered bins
| Rstart_after_Address_Nack_cp | ip_mode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| Rstart_after_Address_Nack |
host |
74 |
1 |
|
|
T27 |
2 |
|
T28 |
4 |
|
T29 |
1 |
Summary for Cross Start_followed_by_Rstart_cp_x_ip_mode_cp
Samples crossed: Start_followed_by_Rstart_cp ip_mode_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
2 |
1 |
1 |
50.00 |
1 |
Automatically Generated Cross Bins for Start_followed_by_Rstart_cp_x_ip_mode_cp
Element holes
| Start_followed_by_Rstart_cp | ip_mode_cp | COUNT | AT LEAST | NUMBER | STATUS |
| * |
[device] |
0 |
1 |
1 |
|
Excluded/Illegal bins
| Start_followed_by_Rstart_cp | ip_mode_cp | COUNT | STATUS | |
| [auto[0]] |
[device , host] |
-- |
Excluded |
(2 bins) |
Covered bins
| Start_followed_by_Rstart_cp | ip_mode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
host |
6 |
1 |
|
|
T202 |
3 |
|
T203 |
1 |
|
T149 |
2 |