Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	29757965	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6597562

1

T1

492

T2

154

T3

118

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	35731595	1			T1	1065		T2	394		T3	358
values[0x0]	310475	1			T1	290		T2	126		T3	44
values[0x1]	313457	1			T1	286		T2	107		T3	53

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	21217344	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

15138183

1

T1

786

T2

276

T3

220

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	138033	1			T1	8		T7	42		T8	9
valid_sources[0x01]	156972	1			T1	6		T7	31		T8	6
valid_sources[0x02]	130778	1			T1	9		T6	480		T7	35
valid_sources[0x03]	129054	1			T1	8		T3	7		T7	32
valid_sources[0x04]	140544	1			T1	7		T7	40		T8	11
valid_sources[0x05]	129822	1			T1	7		T3	1		T7	28
valid_sources[0x06]	132276	1			T1	4		T3	1		T6	1688
valid_sources[0x07]	148635	1			T1	6		T6	4302		T7	39
valid_sources[0x08]	130173	1			T1	5		T6	428		T7	34
valid_sources[0x09]	135845	1			T1	4		T2	59		T3	5
valid_sources[0x0a]	128908	1			T1	6		T3	13		T7	38
valid_sources[0x0b]	167507	1			T1	7		T7	39		T8	4
valid_sources[0x0c]	149172	1			T1	5		T7	29		T8	8
valid_sources[0x0d]	121734	1			T1	6		T7	40		T8	13
valid_sources[0x0e]	138603	1			T1	10		T7	29		T8	5
valid_sources[0x0f]	125406	1			T1	4		T7	33		T8	15
valid_sources[0x10]	131951	1			T1	12		T7	33		T8	2
valid_sources[0x11]	145652	1			T1	3		T7	38		T8	6
valid_sources[0x12]	141200	1			T1	6		T3	8		T7	36
valid_sources[0x13]	143527	1			T1	3		T2	56		T7	39
valid_sources[0x14]	224360	1			T1	10		T7	25		T8	8
valid_sources[0x15]	273127	1			T1	9		T6	171		T7	36
valid_sources[0x16]	128701	1			T1	2		T3	46		T7	38
valid_sources[0x17]	151689	1			T1	10		T7	33		T8	6
valid_sources[0x18]	138382	1			T1	7		T7	30		T8	2
valid_sources[0x19]	147811	1			T1	8		T7	37		T8	2
valid_sources[0x1a]	130758	1			T1	7		T7	29		T8	10
valid_sources[0x1b]	133224	1			T1	12		T7	24		T8	5
valid_sources[0x1c]	136321	1			T1	9		T4	25		T7	44
valid_sources[0x1d]	132489	1			T1	7		T3	3		T7	23
valid_sources[0x1e]	134892	1			T1	5		T3	3		T7	32
valid_sources[0x1f]	139164	1			T1	5		T7	37		T8	7
valid_sources[0x20]	134372	1			T1	4		T7	35		T8	3
valid_sources[0x21]	171448	1			T1	11		T7	33		T8	5
valid_sources[0x22]	130971	1			T1	10		T7	44		T8	7
valid_sources[0x23]	129911	1			T1	8		T7	33		T8	5
valid_sources[0x24]	136683	1			T1	9		T4	12		T7	42
valid_sources[0x25]	130756	1			T1	5		T3	6		T7	33
valid_sources[0x26]	126556	1			T1	11		T7	37		T8	4
valid_sources[0x27]	137989	1			T1	4		T7	27		T8	7
valid_sources[0x28]	130155	1			T1	8		T6	299		T7	44
valid_sources[0x29]	135123	1			T1	8		T3	15		T7	35
valid_sources[0x2a]	137123	1			T1	5		T7	34		T8	4
valid_sources[0x2b]	146646	1			T1	3		T7	34		T8	4
valid_sources[0x2c]	123482	1			T1	7		T7	33		T8	8
valid_sources[0x2d]	126751	1			T1	4		T6	128		T7	38
valid_sources[0x2e]	120351	1			T1	7		T6	342		T7	38
valid_sources[0x2f]	129334	1			T1	8		T7	35		T8	8
valid_sources[0x30]	143335	1			T1	4		T7	29		T8	15
valid_sources[0x31]	126431	1			T1	5		T2	21		T3	3
valid_sources[0x32]	138042	1			T1	9		T7	23		T8	2
valid_sources[0x33]	128590	1			T1	8		T7	28		T8	2
valid_sources[0x34]	130902	1			T1	2		T7	31		T8	4
valid_sources[0x35]	137336	1			T1	8		T3	2		T7	47
valid_sources[0x36]	121999	1			T1	6		T3	9		T7	31
valid_sources[0x37]	148157	1			T1	6		T3	5		T7	41
valid_sources[0x38]	131164	1			T1	6		T6	1923		T7	31
valid_sources[0x39]	123267	1			T1	3		T7	32		T8	2
valid_sources[0x3a]	176907	1			T1	5		T7	35		T8	1
valid_sources[0x3b]	129016	1			T1	4		T3	8		T7	35
valid_sources[0x3c]	137625	1			T1	5		T7	27		T8	7
valid_sources[0x3d]	141253	1			T1	8		T7	35		T8	10
valid_sources[0x3e]	151331	1			T1	5		T7	27		T8	4
valid_sources[0x3f]	135689	1			T1	9		T2	108		T7	31
valid_sources[0x40]	134656	1			T1	5		T7	28		T8	4
valid_sources[0x41]	123390	1			T1	3		T7	33		T8	3
valid_sources[0x42]	125920	1			T1	10		T7	30		T8	7
valid_sources[0x43]	135836	1			T1	8		T7	26		T8	9
valid_sources[0x44]	118357	1			T1	13		T3	13		T7	36
valid_sources[0x45]	126524	1			T1	8		T6	1766		T7	35
valid_sources[0x46]	133145	1			T1	10		T7	31		T8	3
valid_sources[0x47]	139527	1			T1	7		T7	32		T8	7
valid_sources[0x48]	219773	1			T1	6		T3	31		T7	31
valid_sources[0x49]	141129	1			T1	7		T7	27		T17	64
valid_sources[0x4a]	121571	1			T1	4		T6	555		T7	30
valid_sources[0x4b]	164434	1			T1	6		T7	43		T8	4
valid_sources[0x4c]	141570	1			T1	2		T7	31		T8	10
valid_sources[0x4d]	139032	1			T1	10		T7	28		T8	10
valid_sources[0x4e]	163823	1			T1	7		T7	31		T8	2
valid_sources[0x4f]	126211	1			T1	15		T3	18		T7	30
valid_sources[0x50]	601223	1			T1	5		T7	38		T8	1
valid_sources[0x51]	134621	1			T1	2		T3	3		T7	29
valid_sources[0x52]	125069	1			T1	6		T3	2		T7	30
valid_sources[0x53]	134238	1			T1	7		T3	10		T6	2688
valid_sources[0x54]	133329	1			T1	9		T3	12		T7	36
valid_sources[0x55]	138983	1			T1	8		T4	18		T7	40
valid_sources[0x56]	133994	1			T1	3		T7	38		T8	2
valid_sources[0x57]	151185	1			T1	7		T6	2437		T7	33
valid_sources[0x58]	124372	1			T1	4		T3	18		T7	30
valid_sources[0x59]	128423	1			T1	8		T6	304		T7	44
valid_sources[0x5a]	134471	1			T1	8		T7	29		T8	6
valid_sources[0x5b]	123127	1			T1	12		T3	5		T7	32
valid_sources[0x5c]	122787	1			T1	2		T7	22		T8	10
valid_sources[0x5d]	123168	1			T1	7		T7	40		T8	9
valid_sources[0x5e]	129603	1			T1	6		T3	1		T4	7
valid_sources[0x5f]	134247	1			T1	9		T7	24		T8	2
valid_sources[0x60]	156527	1			T1	7		T6	5135		T7	25
valid_sources[0x61]	139147	1			T1	6		T7	27		T8	2
valid_sources[0x62]	244237	1			T1	7		T7	26		T8	14
valid_sources[0x63]	120886	1			T1	5		T7	28		T8	5
valid_sources[0x64]	146288	1			T1	6		T3	7		T7	31
valid_sources[0x65]	145187	1			T1	9		T3	12		T7	34
valid_sources[0x66]	134122	1			T1	10		T6	437		T7	41
valid_sources[0x67]	152484	1			T1	5		T6	4698		T7	33
valid_sources[0x68]	133570	1			T1	5		T3	1		T7	33
valid_sources[0x69]	132852	1			T1	9		T3	7		T7	29
valid_sources[0x6a]	118565	1			T1	6		T7	38		T8	5
valid_sources[0x6b]	126207	1			T1	7		T4	28		T7	22
valid_sources[0x6c]	127340	1			T1	6		T7	36		T8	10
valid_sources[0x6d]	145177	1			T1	9		T7	31		T8	5
valid_sources[0x6e]	145242	1			T1	4		T3	5		T7	31
valid_sources[0x6f]	126115	1			T1	8		T5	6		T7	33
valid_sources[0x70]	122962	1			T1	5		T7	26		T8	10
valid_sources[0x71]	150076	1			T1	4		T7	28		T8	14
valid_sources[0x72]	149483	1			T1	6		T7	32		T8	6
valid_sources[0x73]	133770	1			T1	8		T7	34		T8	9
valid_sources[0x74]	146843	1			T1	5		T6	1159		T7	40
valid_sources[0x75]	129477	1			T1	4		T7	24		T8	3
valid_sources[0x76]	133098	1			T1	4		T7	28		T8	7
valid_sources[0x77]	125751	1			T1	4		T3	4		T7	40
valid_sources[0x78]	152390	1			T1	13		T4	36		T7	32
valid_sources[0x79]	146757	1			T1	11		T7	25		T17	57
valid_sources[0x7a]	133696	1			T1	3		T7	35		T8	5
valid_sources[0x7b]	150602	1			T1	6		T7	27		T8	21
valid_sources[0x7c]	138070	1			T1	8		T7	36		T17	61
valid_sources[0x7d]	133324	1			T1	9		T3	3		T7	38
valid_sources[0x7e]	128189	1			T1	3		T3	2		T7	38
valid_sources[0x7f]	138375	1			T1	4		T3	3		T7	29
valid_sources[0x80]	128361	1			T1	3		T7	35		T8	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6329933

1

T1

259

T2

66

T3

78

values[0x0]

all_enables

biggest_size

158008

1

T1

140

T2

59

T3

24

values[0x1]

all_enables

biggest_size

109621

1

T1

93

T2

29

T3

16