Module Definition
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Module : prim_onehot_check
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_onehot_check_0/rtl/prim_onehot_check.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check 100.00 100.00


Module Instance : tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_reg_we_check


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : prim_onehot_check
TotalCoveredPercent
Totals 5 5 100.00
Total Bits 50 50 100.00
Total Bits 0->1 25 25 100.00
Total Bits 1->0 25 25 100.00

Ports 5 5 100.00
Port Bits 50 50 100.00
Port Bits 0->1 25 25 100.00
Port Bits 1->0 25 25 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T16,T43,T24 Yes T1,T2,T3 INPUT
oh_i[4:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
oh_i[6:5] Unreachable Unreachable Unreachable INPUT
oh_i[10:7] Yes Yes *T4,T7,T17 Yes T4,T7,T17 INPUT
oh_i[12:11] Unreachable Unreachable Unreachable INPUT
oh_i[13] Yes Yes *T11,*T12,*T13 Yes T11,T12,T13 INPUT
oh_i[14] Unreachable Unreachable Unreachable INPUT
oh_i[21:15] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
oh_i[22] Unreachable Unreachable Unreachable INPUT
oh_i[25:23] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
oh_i[26] Unreachable Unreachable Unreachable INPUT
oh_i[27] Yes Yes T27,T28,T29 Yes T27,T28,T29 INPUT
addr_i[4:0] Unreachable Unreachable Unreachable INPUT
en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
err_o Yes Yes T99,T100,T101 Yes T99,T100,T101 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%