Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.72	100.00	100.00	94.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	221995347	8847	0	0
host_fifo_config_rd_A	221995347	4298	0	0
host_nack_handler_timeout_rd_A	221995347	1016	0	0
host_timeout_ctrl_rd_A	221995347	663	0	0
intr_enable_rd_A	221995347	3843	0	0
ovrd_rd_A	221995347	1914	0	0
target_fifo_config_rd_A	221995347	1361	0	0
target_id_rd_A	221995347	1567	0	0
target_timeout_ctrl_rd_A	221995347	1049	0	0
timeout_ctrl_rd_A	221995347	935	0	0
timing0_rd_A	221995347	1120	0	0
timing1_rd_A	221995347	977	0	0
timing2_rd_A	221995347	1092	0	0
timing3_rd_A	221995347	1049	0	0
timing4_rd_A	221995347	995	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221995347	8847	0	0
T76	7803	3	0	0
T77	2191	5	0	0
T97	2982	93	0	0
T113	11197	525	0	0
T114	7409	4	0	0
T115	2986	101	0	0
T117	2601	373	0	0
T118	9697	345	0	0
T130	3283	14	0	0
T131	2642	11	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221995347	4298	0	0
T54	7184	0	0	0
T60	0	273	0	0
T88	179082	0	0	0
T89	17173	0	0	0
T150	361679	74	0	0
T151	0	123	0	0
T152	0	95	0	0
T153	0	172	0	0
T154	0	198	0	0
T155	0	148	0	0
T156	0	128	0	0
T157	0	62	0	0
T158	0	62	0	0
T159	40557	0	0	0
T160	147148	0	0	0
T161	137065	0	0	0
T162	101822	0	0	0
T163	120561	0	0	0
T164	430918	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221995347	1016	0	0
T77	2191	7	0	0
T114	7409	50	0	0
T116	14526	125	0	0
T125	13577	123	0	0
T134	1333	6	0	0
T144	5280	44	0	0
T146	3432	13	0	0
T165	3597	37	0	0
T166	5628	96	0	0
T167	13298	17	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221995347	663	0	0
T77	2191	8	0	0
T114	7409	33	0	0
T116	14526	75	0	0
T125	13577	94	0	0
T134	1333	6	0	0
T144	5280	1	0	0
T145	2450	5	0	0
T165	3597	19	0	0
T166	5628	80	0	0
T167	13298	18	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221995347	3843	0	0
T31	0	15	0	0
T32	0	35	0	0
T77	0	3	0	0
T95	169238	8	0	0
T114	0	229	0	0
T116	0	667	0	0
T134	0	7	0	0
T144	0	68	0	0
T168	0	10	0	0
T169	0	23	0	0
T170	245457	0	0	0
T171	123092	0	0	0
T172	157589	0	0	0
T173	105115	0	0	0
T174	35368	0	0	0
T175	129588	0	0	0
T176	388551	0	0	0
T177	184283	0	0	0
T178	36177	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221995347	1914	0	0
T11	1735	17	0	0
T12	0	37	0	0
T13	0	71	0	0
T14	10145	0	0	0
T16	172508	0	0	0
T19	105123	0	0	0
T20	172992	0	0	0
T22	115043	0	0	0
T24	146324	0	0	0
T38	66496	0	0	0
T43	5009	0	0	0
T44	114387	0	0	0
T179	0	61	0	0
T180	0	61	0	0
T181	0	36	0	0
T182	0	74	0	0
T183	0	33	0	0
T184	0	55	0	0
T185	0	56	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221995347	1361	0	0
T77	2191	1	0	0
T114	7409	98	0	0
T116	14526	123	0	0
T125	13577	155	0	0
T134	1333	6	0	0
T144	5280	30	0	0
T146	3432	37	0	0
T165	3597	36	0	0
T166	5628	123	0	0
T167	13298	18	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221995347	1567	0	0
T77	2191	22	0	0
T114	7409	120	0	0
T116	14526	222	0	0
T125	13577	188	0	0
T134	1333	23	0	0
T144	5280	53	0	0
T145	2450	2	0	0
T165	3597	32	0	0
T166	5628	100	0	0
T167	13298	16	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221995347	1049	0	0
T114	7409	67	0	0
T116	14526	86	0	0
T125	13577	130	0	0
T134	1333	5	0	0
T144	5280	48	0	0
T145	2450	1	0	0
T146	3432	27	0	0
T165	3597	8	0	0
T166	5628	106	0	0
T167	13298	8	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221995347	935	0	0
T77	2191	4	0	0
T114	7409	70	0	0
T116	14526	156	0	0
T125	13577	117	0	0
T134	1333	1	0	0
T144	5280	31	0	0
T145	2450	1	0	0
T165	3597	9	0	0
T166	5628	103	0	0
T167	13298	17	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221995347	1120	0	0
T77	2191	17	0	0
T114	7409	84	0	0
T116	14526	84	0	0
T125	13577	111	0	0
T134	1333	7	0	0
T144	5280	51	0	0
T145	2450	25	0	0
T165	3597	22	0	0
T166	5628	83	0	0
T167	13298	12	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221995347	977	0	0
T77	2191	5	0	0
T114	7409	68	0	0
T116	14526	106	0	0
T125	13577	110	0	0
T134	1333	8	0	0
T144	5280	11	0	0
T145	2450	13	0	0
T165	3597	9	0	0
T166	5628	118	0	0
T167	13298	9	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221995347	1092	0	0
T77	2191	9	0	0
T114	7409	50	0	0
T116	14526	113	0	0
T125	13577	134	0	0
T134	1333	17	0	0
T144	5280	64	0	0
T145	2450	3	0	0
T165	3597	19	0	0
T166	5628	125	0	0
T167	13298	38	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221995347	1049	0	0
T77	2191	13	0	0
T114	7409	79	0	0
T116	14526	107	0	0
T125	13577	105	0	0
T134	1333	3	0	0
T144	5280	7	0	0
T145	2450	17	0	0
T165	3597	29	0	0
T166	5628	92	0	0
T167	13298	23	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221995347	995	0	0
T77	2191	10	0	0
T114	7409	76	0	0
T116	14526	143	0	0
T125	13577	112	0	0
T144	5280	57	0	0
T145	2450	14	0	0
T146	3432	26	0	0
T165	3597	35	0	0
T166	5628	65	0	0
T167	13298	22	0	0