Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.72	100.00	100.00	94.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	413837473	8375	0	0
ctrl_rd_A	413837473	1826	0	0
host_fifo_config_rd_A	413837473	5064	0	0
host_nack_handler_timeout_rd_A	413837473	1693	0	0
host_timeout_ctrl_rd_A	413837473	1636	0	0
intr_enable_rd_A	413837473	3067	0	0
ovrd_rd_A	413837473	2789	0	0
target_fifo_config_rd_A	413837473	1898	0	0
target_id_rd_A	413837473	1893	0	0
target_timeout_ctrl_rd_A	413837473	1762	0	0
timeout_ctrl_rd_A	413837473	1678	0	0
timing0_rd_A	413837473	1658	0	0
timing1_rd_A	413837473	1737	0	0
timing2_rd_A	413837473	1698	0	0
timing3_rd_A	413837473	1778	0	0
timing4_rd_A	413837473	1750	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413837473	8375	0	0
T63	2170	23	0	0
T64	1935	11	0	0
T116	10268	317	0	0
T129	2744	27	0	0
T130	16068	794	0	0
T131	7803	1	0	0
T132	2091	203	0	0
T135	2851	566	0	0
T151	2266	4	0	0
T152	2693	5	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413837473	1826	0	0
T62	2512	3	0	0
T116	10268	14	0	0
T130	16068	21	0	0
T153	5080	2	0	0
T158	1602	4	0	0
T161	2313	4	0	0
T170	6120	51	0	0
T171	3210	8	0	0
T175	2517	7	0	0
T176	5572	27	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413837473	5064	0	0
T24	44788	0	0	0
T45	267085	0	0	0
T96	12670	0	0	0
T109	86606	0	0	0
T177	264853	151	0	0
T178	0	114	0	0
T179	0	165	0	0
T180	0	159	0	0
T181	0	190	0	0
T182	0	125	0	0
T183	0	126	0	0
T184	0	86	0	0
T185	0	179	0	0
T186	0	158	0	0
T187	169868	0	0	0
T188	98352	0	0	0
T189	11364	0	0	0
T190	131969	0	0	0
T191	109140	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413837473	1693	0	0
T62	2512	5	0	0
T116	10268	29	0	0
T130	16068	30	0	0
T153	5080	24	0	0
T158	1602	3	0	0
T170	6120	26	0	0
T171	3210	27	0	0
T175	2517	10	0	0
T176	5572	6	0	0
T192	11601	31	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413837473	1636	0	0
T62	2512	11	0	0
T116	10268	21	0	0
T130	16068	22	0	0
T153	5080	13	0	0
T158	1602	8	0	0
T161	2313	6	0	0
T170	6120	22	0	0
T171	3210	16	0	0
T175	2517	12	0	0
T176	5572	24	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413837473	3067	0	0
T62	0	9	0	0
T116	0	25	0	0
T136	512502	29	0	0
T174	126699	0	0	0
T178	0	43	0	0
T185	0	36	0	0
T193	0	26	0	0
T194	0	18	0	0
T195	0	12	0	0
T196	0	7	0	0
T197	0	10	0	0
T198	172855	0	0	0
T199	2593	0	0	0
T200	30214	0	0	0
T201	163332	0	0	0
T202	54028	0	0	0
T203	123663	0	0	0
T204	520273	0	0	0
T205	107706	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413837473	2789	0	0
T13	103743	0	0	0
T22	748679	0	0	0
T34	1404	27	0	0
T68	30861	0	0	0
T74	805463	0	0	0
T85	9708	0	0	0
T86	7813	0	0	0
T206	0	23	0	0
T207	0	79	0	0
T208	0	59	0	0
T209	0	67	0	0
T210	0	30	0	0
T211	0	27	0	0
T212	0	66	0	0
T213	0	78	0	0
T214	0	80	0	0
T215	2084	0	0	0
T216	32712	0	0	0
T217	27420	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413837473	1898	0	0
T62	2512	1	0	0
T116	10268	51	0	0
T130	16068	35	0	0
T158	1602	12	0	0
T161	2313	14	0	0
T170	6120	47	0	0
T171	3210	32	0	0
T175	2517	9	0	0
T176	5572	37	0	0
T192	11601	25	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413837473	1893	0	0
T62	2512	9	0	0
T116	10268	15	0	0
T130	16068	30	0	0
T153	5080	10	0	0
T158	1602	4	0	0
T170	6120	70	0	0
T171	3210	47	0	0
T175	2517	6	0	0
T176	5572	31	0	0
T192	11601	30	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413837473	1762	0	0
T62	2512	13	0	0
T116	10268	11	0	0
T130	16068	23	0	0
T153	5080	11	0	0
T158	1602	4	0	0
T161	2313	4	0	0
T170	6120	73	0	0
T171	3210	28	0	0
T175	2517	7	0	0
T176	5572	11	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413837473	1678	0	0
T116	10268	17	0	0
T130	16068	32	0	0
T153	5080	4	0	0
T158	1602	2	0	0
T161	2313	8	0	0
T170	6120	44	0	0
T171	3210	3	0	0
T175	2517	8	0	0
T176	5572	22	0	0
T192	11601	6	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413837473	1658	0	0
T62	2512	10	0	0
T116	10268	4	0	0
T130	16068	35	0	0
T158	1602	1	0	0
T161	2313	1	0	0
T170	6120	38	0	0
T171	3210	10	0	0
T175	2517	6	0	0
T176	5572	3	0	0
T192	11601	17	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413837473	1737	0	0
T62	2512	6	0	0
T116	10268	13	0	0
T130	16068	34	0	0
T153	5080	4	0	0
T158	1602	8	0	0
T161	2313	6	0	0
T170	6120	21	0	0
T171	3210	17	0	0
T175	2517	7	0	0
T176	5572	27	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413837473	1698	0	0
T62	2512	5	0	0
T116	10268	21	0	0
T130	16068	30	0	0
T153	5080	20	0	0
T158	1602	6	0	0
T161	2313	4	0	0
T170	6120	31	0	0
T171	3210	16	0	0
T175	2517	13	0	0
T176	5572	7	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413837473	1778	0	0
T62	2512	7	0	0
T116	10268	1	0	0
T130	16068	27	0	0
T153	5080	13	0	0
T158	1602	13	0	0
T161	2313	5	0	0
T170	6120	16	0	0
T171	3210	40	0	0
T175	2517	12	0	0
T176	5572	46	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413837473	1750	0	0
T62	2512	5	0	0
T116	10268	22	0	0
T130	16068	21	0	0
T158	1602	7	0	0
T161	2313	13	0	0
T170	6120	53	0	0
T171	3210	17	0	0
T175	2517	10	0	0
T176	5572	17	0	0
T192	11601	20	0	0