Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : i2c
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.72 100.00 100.00 94.87 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 98.72 100.00 100.00 94.87 100.00



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.72 100.00 100.00 94.87 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.60 98.12 92.46 97.66 91.30 95.42 98.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
i2c_core 93.13 97.82 87.97 91.30 93.85 94.74
i2c_csr_assert 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
u_reg 98.81 98.52 98.20 100.00 97.35 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : i2c
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN6811100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN13011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
129 1 1
130 1 1


Cond Coverage for Module : i2c
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       68
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------
-1--2-StatusTests
01CoveredT32,T107,T60
10CoveredT1,T2,T3
11CoveredT32,T107,T115

Toggle Coverage for Module : i2c
TotalCoveredPercent
Totals 49 45 91.84
Total Bits 390 370 94.87
Total Bits 0->1 195 185 94.87
Total Bits 1->0 195 185 94.87

Ports 49 45 91.84
Port Bits 390 370 94.87
Port Bits 0->1 195 185 94.87
Port Bits 1->0 195 185 94.87

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T41,T38 Yes T1,T2,T3 INPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T6,T8,T9 Yes T6,T8,T9 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T116,T63,T64 Yes T116,T63,T64 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T32,T107,T115 Yes T32,T107,T115 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T32,T107,T115 Yes T32,T107,T115 OUTPUT
cio_scl_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
cio_scl_o Unreachable Unreachable Unreachable OUTPUT
cio_scl_en_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cio_sda_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
cio_sda_o Unreachable Unreachable Unreachable OUTPUT
cio_sda_en_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
intr_fmt_threshold_o Yes Yes T1,T4,T6 Yes T1,T2,T3 OUTPUT
intr_rx_threshold_o Yes Yes T4,T6,T39 Yes T4,T6,T39 OUTPUT
intr_acq_threshold_o Yes Yes T2,T11,T30 Yes T2,T11,T30 OUTPUT
intr_rx_overflow_o Yes Yes T39,T40,T41 Yes T39,T40,T41 OUTPUT
intr_controller_halt_o Yes Yes T5,T68,T69 Yes T5,T68,T69 OUTPUT
intr_scl_interference_o Yes Yes T65,T66,T67 Yes T65,T66,T67 OUTPUT
intr_sda_interference_o Yes Yes T1,T4,T6 Yes T1,T4,T6 OUTPUT
intr_stretch_timeout_o Yes Yes T1,T4,T6 Yes T1,T4,T6 OUTPUT
intr_sda_unstable_o Yes Yes T1,T4,T6 Yes T1,T4,T6 OUTPUT
intr_cmd_complete_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
intr_tx_stretch_o Yes Yes T3,T8,T10 Yes T3,T8,T10 OUTPUT
intr_tx_threshold_o Yes Yes T1,T8,T11 Yes T1,T2,T3 OUTPUT
intr_acq_full_o Yes Yes T2,T21,T22 Yes T2,T21,T22 OUTPUT
intr_unexp_stop_o Yes Yes T65,T66,T17 Yes T65,T66,T17 OUTPUT
intr_host_timeout_o Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT

*Tests covering at least one bit in the range

Assert Coverage for Module : i2c
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 23 23 100.00 23 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 23 23 100.00 23 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertKnownO_A 413189226 413016351 0 0
CioSclEnKnownO_A 413189226 413016351 0 0
CioSclKnownO_A 413189226 413016351 0 0
CioSdaEnKnownO_A 413189226 413016351 0 0
CioSdaKnownO_A 413189226 413016351 0 0
FpvSecCmRegWeOnehotCheck_A 413189226 90 0 0
IntrAcqFulllwKnownO_A 413189226 413016351 0 0
IntrAcqWtmkKnownO_A 413189226 413016351 0 0
IntrCommandCompleteKnownO_A 413189226 413016351 0 0
IntrControllerHaltKnownO_A 413189226 413016351 0 0
IntrFmtWtmkKnownO_A 413189226 413016351 0 0
IntrHostTimeoutKnownO_A 413189226 413016351 0 0
IntrRxOflwKnownO_A 413189226 413016351 0 0
IntrRxWtmkKnownO_A 413189226 413016351 0 0
IntrSclInterfKnownO_A 413189226 413016351 0 0
IntrSdaInterfKnownO_A 413189226 413016351 0 0
IntrSdaUnstableKnownO_A 413189226 413016351 0 0
IntrStretchTimeoutKnownO_A 413189226 413016351 0 0
IntrTxStretchKnownO_A 413189226 413016351 0 0
IntrTxWtmkKnownO_A 413189226 413016351 0 0
IntrUnexpStopKnownO_A 413189226 413016351 0 0
TlAReadyKnownO_A 413189226 413016351 0 0
TlDValidKnownO_A 413189226 413016351 0 0


AlertKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 413189226 413016351 0 0
T1 6377 5709 0 0
T2 155936 155930 0 0
T3 174779 174688 0 0
T4 90151 90086 0 0
T5 35665 35580 0 0
T6 279074 279004 0 0
T7 1726 1674 0 0
T8 97115 97022 0 0
T9 315453 315401 0 0
T10 34318 34230 0 0

CioSclEnKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 413189226 413016351 0 0
T1 6377 5709 0 0
T2 155936 155930 0 0
T3 174779 174688 0 0
T4 90151 90086 0 0
T5 35665 35580 0 0
T6 279074 279004 0 0
T7 1726 1674 0 0
T8 97115 97022 0 0
T9 315453 315401 0 0
T10 34318 34230 0 0

CioSclKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 413189226 413016351 0 0
T1 6377 5709 0 0
T2 155936 155930 0 0
T3 174779 174688 0 0
T4 90151 90086 0 0
T5 35665 35580 0 0
T6 279074 279004 0 0
T7 1726 1674 0 0
T8 97115 97022 0 0
T9 315453 315401 0 0
T10 34318 34230 0 0

CioSdaEnKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 413189226 413016351 0 0
T1 6377 5709 0 0
T2 155936 155930 0 0
T3 174779 174688 0 0
T4 90151 90086 0 0
T5 35665 35580 0 0
T6 279074 279004 0 0
T7 1726 1674 0 0
T8 97115 97022 0 0
T9 315453 315401 0 0
T10 34318 34230 0 0

CioSdaKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 413189226 413016351 0 0
T1 6377 5709 0 0
T2 155936 155930 0 0
T3 174779 174688 0 0
T4 90151 90086 0 0
T5 35665 35580 0 0
T6 279074 279004 0 0
T7 1726 1674 0 0
T8 97115 97022 0 0
T9 315453 315401 0 0
T10 34318 34230 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 413189226 90 0 0
T46 107087 0 0 0
T50 989482 0 0 0
T117 4871 10 0 0
T118 0 20 0 0
T119 0 20 0 0
T120 0 20 0 0
T121 0 20 0 0
T122 183937 0 0 0
T123 317463 0 0 0
T124 12813 0 0 0
T125 52085 0 0 0
T126 197072 0 0 0
T127 39004 0 0 0
T128 98356 0 0 0

IntrAcqFulllwKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 413189226 413016351 0 0
T1 6377 5709 0 0
T2 155936 155930 0 0
T3 174779 174688 0 0
T4 90151 90086 0 0
T5 35665 35580 0 0
T6 279074 279004 0 0
T7 1726 1674 0 0
T8 97115 97022 0 0
T9 315453 315401 0 0
T10 34318 34230 0 0

IntrAcqWtmkKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 413189226 413016351 0 0
T1 6377 5709 0 0
T2 155936 155930 0 0
T3 174779 174688 0 0
T4 90151 90086 0 0
T5 35665 35580 0 0
T6 279074 279004 0 0
T7 1726 1674 0 0
T8 97115 97022 0 0
T9 315453 315401 0 0
T10 34318 34230 0 0

IntrCommandCompleteKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 413189226 413016351 0 0
T1 6377 5709 0 0
T2 155936 155930 0 0
T3 174779 174688 0 0
T4 90151 90086 0 0
T5 35665 35580 0 0
T6 279074 279004 0 0
T7 1726 1674 0 0
T8 97115 97022 0 0
T9 315453 315401 0 0
T10 34318 34230 0 0

IntrControllerHaltKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 413189226 413016351 0 0
T1 6377 5709 0 0
T2 155936 155930 0 0
T3 174779 174688 0 0
T4 90151 90086 0 0
T5 35665 35580 0 0
T6 279074 279004 0 0
T7 1726 1674 0 0
T8 97115 97022 0 0
T9 315453 315401 0 0
T10 34318 34230 0 0

IntrFmtWtmkKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 413189226 413016351 0 0
T1 6377 5709 0 0
T2 155936 155930 0 0
T3 174779 174688 0 0
T4 90151 90086 0 0
T5 35665 35580 0 0
T6 279074 279004 0 0
T7 1726 1674 0 0
T8 97115 97022 0 0
T9 315453 315401 0 0
T10 34318 34230 0 0

IntrHostTimeoutKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 413189226 413016351 0 0
T1 6377 5709 0 0
T2 155936 155930 0 0
T3 174779 174688 0 0
T4 90151 90086 0 0
T5 35665 35580 0 0
T6 279074 279004 0 0
T7 1726 1674 0 0
T8 97115 97022 0 0
T9 315453 315401 0 0
T10 34318 34230 0 0

IntrRxOflwKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 413189226 413016351 0 0
T1 6377 5709 0 0
T2 155936 155930 0 0
T3 174779 174688 0 0
T4 90151 90086 0 0
T5 35665 35580 0 0
T6 279074 279004 0 0
T7 1726 1674 0 0
T8 97115 97022 0 0
T9 315453 315401 0 0
T10 34318 34230 0 0

IntrRxWtmkKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 413189226 413016351 0 0
T1 6377 5709 0 0
T2 155936 155930 0 0
T3 174779 174688 0 0
T4 90151 90086 0 0
T5 35665 35580 0 0
T6 279074 279004 0 0
T7 1726 1674 0 0
T8 97115 97022 0 0
T9 315453 315401 0 0
T10 34318 34230 0 0

IntrSclInterfKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 413189226 413016351 0 0
T1 6377 5709 0 0
T2 155936 155930 0 0
T3 174779 174688 0 0
T4 90151 90086 0 0
T5 35665 35580 0 0
T6 279074 279004 0 0
T7 1726 1674 0 0
T8 97115 97022 0 0
T9 315453 315401 0 0
T10 34318 34230 0 0

IntrSdaInterfKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 413189226 413016351 0 0
T1 6377 5709 0 0
T2 155936 155930 0 0
T3 174779 174688 0 0
T4 90151 90086 0 0
T5 35665 35580 0 0
T6 279074 279004 0 0
T7 1726 1674 0 0
T8 97115 97022 0 0
T9 315453 315401 0 0
T10 34318 34230 0 0

IntrSdaUnstableKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 413189226 413016351 0 0
T1 6377 5709 0 0
T2 155936 155930 0 0
T3 174779 174688 0 0
T4 90151 90086 0 0
T5 35665 35580 0 0
T6 279074 279004 0 0
T7 1726 1674 0 0
T8 97115 97022 0 0
T9 315453 315401 0 0
T10 34318 34230 0 0

IntrStretchTimeoutKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 413189226 413016351 0 0
T1 6377 5709 0 0
T2 155936 155930 0 0
T3 174779 174688 0 0
T4 90151 90086 0 0
T5 35665 35580 0 0
T6 279074 279004 0 0
T7 1726 1674 0 0
T8 97115 97022 0 0
T9 315453 315401 0 0
T10 34318 34230 0 0

IntrTxStretchKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 413189226 413016351 0 0
T1 6377 5709 0 0
T2 155936 155930 0 0
T3 174779 174688 0 0
T4 90151 90086 0 0
T5 35665 35580 0 0
T6 279074 279004 0 0
T7 1726 1674 0 0
T8 97115 97022 0 0
T9 315453 315401 0 0
T10 34318 34230 0 0

IntrTxWtmkKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 413189226 413016351 0 0
T1 6377 5709 0 0
T2 155936 155930 0 0
T3 174779 174688 0 0
T4 90151 90086 0 0
T5 35665 35580 0 0
T6 279074 279004 0 0
T7 1726 1674 0 0
T8 97115 97022 0 0
T9 315453 315401 0 0
T10 34318 34230 0 0

IntrUnexpStopKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 413189226 413016351 0 0
T1 6377 5709 0 0
T2 155936 155930 0 0
T3 174779 174688 0 0
T4 90151 90086 0 0
T5 35665 35580 0 0
T6 279074 279004 0 0
T7 1726 1674 0 0
T8 97115 97022 0 0
T9 315453 315401 0 0
T10 34318 34230 0 0

TlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 413189226 413016351 0 0
T1 6377 5709 0 0
T2 155936 155930 0 0
T3 174779 174688 0 0
T4 90151 90086 0 0
T5 35665 35580 0 0
T6 279074 279004 0 0
T7 1726 1674 0 0
T8 97115 97022 0 0
T9 315453 315401 0 0
T10 34318 34230 0 0

TlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 413189226 413016351 0 0
T1 6377 5709 0 0
T2 155936 155930 0 0
T3 174779 174688 0 0
T4 90151 90086 0 0
T5 35665 35580 0 0
T6 279074 279004 0 0
T7 1726 1674 0 0
T8 97115 97022 0 0
T9 315453 315401 0 0
T10 34318 34230 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%