Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
94.44	94.44	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	94.44	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.44	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	3	24	88.89

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	3	24	88.89	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

161438

1

T4

92

T5

716

T7

619

ack

15001

1

T1

15

T2

50

T3

32

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	621	1			T5	4		T7	2		T61	1
high	36234	1			T1	3		T2	1		T3	1
med	65621	1			T1	4		T2	11		T3	6
sml	73330	1			T1	8		T2	38		T3	25
all_zero	633	1			T4	1		T5	4		T7	2

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

87922

1

T1

8

T2

26

T3

19

auto[1]

88517

1

T1

7

T2

24

T3

13

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

121711

1

T1

15

T2

37

T3

27

auto[1]

54728

1

T2

13

T3

5

T4

41

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

168516

1

T1

8

T2

19

T3

14

auto[1]

7923

1

T1

7

T2

31

T3

18

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

165964

1

T1

7

T2

31

T3

18

auto[1]

10475

1

T1

8

T2

19

T3

14

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

166843

1

T1

8

T2

32

T3

19

auto[1]

9596

1

T1

7

T2

18

T3

13

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

87922

1

T1

8

T2

26

T3

19

auto[1]

88517

1

T1

7

T2

24

T3

13

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

121711

1

T1

15

T2

37

T3

27

auto[1]

54728

1

T2

13

T3

5

T4

41

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

168516

1

T1

8

T2

19

T3

14

auto[1]

7923

1

T1

7

T2

31

T3

18

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

165964

1

T1

7

T2

31

T3

18

auto[1]

10475

1

T1

8

T2

19

T3

14

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

166843

1

T1

8

T2

32

T3

19

auto[1]

9596

1

T1

7

T2

18

T3

13

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	3	24	88.89	1
Automatically Generated Cross Bins	15	1	14	93.33	1
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

cp_fbyte	start	stop	read	rcont	nakok	cp_ack	COUNT	AT LEAST	NUMBER	STATUS
[all_zero]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[ack]	0	1	1

Covered bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

8

1

T232

1

T233

1

T234

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

3

1

T235

1

T236

1

T237

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

5

1

T162

1

T238

1

T239

1

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

303

1

T61

4

T47

2

T70

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

164

1

T5

1

T40

1

T87

2

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

123

1

T7

1

T62

2

T47

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

587

1

T7

4

T40

6

T61

3

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

293

1

T5

1

T61

1

T62

2

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

288

1

T5

2

T40

1

T62

1

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

543

1

T5

2

T7

1

T40

4

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

286

1

T7

1

T40

3

T61

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

270

1

T61

1

T62

1

T47

1

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

10

1

T217

1

T240

1

T241

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

2

1

T242

1

T243

1

-

-

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	51234	1			T4	21		T5	242		T7	223
write_address_byte	10475	1			T1	8		T2	19		T3	14
read_with_ack	2198	1			T2	13		T3	5		T5	3
read_with_nack	5725	1			T1	7		T2	18		T3	13
stop_byte	9596	1			T1	7		T2	18		T3	13
write_address_byte_nak	5462	1			T5	9		T7	10		T40	21
data_byte_nack	161438	1			T4	92		T5	716		T7	619
stop_byte_nack	5858	1			T4	1		T5	8		T7	10
nakok_byte_nack	81044	1			T4	56		T5	341		T7	294
nakok_addr_byte_nack	2739	1			T5	4		T7	4		T40	13