Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	42757409	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

10544534

1

T1

38456

T2

4755

T3

3587

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	52366793	1			T1	78145		T2	15249		T3	12418
values[0x0]	467938	1			T1	66		T2	425		T3	291
values[0x1]	467212	1			T1	77		T2	456		T3	268

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	30408791	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

22893152

1

T1

46681

T2

8017

T3

6288

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	226394	1			T1	314		T2	34		T3	46
valid_sources[0x01]	199587	1			T1	301		T2	49		T3	49
valid_sources[0x02]	203540	1			T1	302		T2	30		T3	55
valid_sources[0x03]	213363	1			T1	296		T2	73		T3	66
valid_sources[0x04]	217150	1			T1	298		T2	110		T3	57
valid_sources[0x05]	193605	1			T1	363		T2	76		T3	70
valid_sources[0x06]	197717	1			T1	318		T2	34		T3	62
valid_sources[0x07]	182661	1			T1	249		T2	73		T3	63
valid_sources[0x08]	201837	1			T1	284		T2	35		T3	60
valid_sources[0x09]	179002	1			T1	295		T2	74		T3	62
valid_sources[0x0a]	200980	1			T1	334		T2	86		T3	69
valid_sources[0x0b]	266387	1			T1	268		T2	40		T3	46
valid_sources[0x0c]	368255	1			T1	275		T2	27		T3	62
valid_sources[0x0d]	200330	1			T1	363		T2	65		T3	63
valid_sources[0x0e]	196225	1			T1	348		T2	36		T3	45
valid_sources[0x0f]	188802	1			T1	368		T2	113		T3	53
valid_sources[0x10]	200474	1			T1	289		T2	53		T3	49
valid_sources[0x11]	198417	1			T1	320		T2	82		T3	51
valid_sources[0x12]	198653	1			T1	310		T2	62		T3	55
valid_sources[0x13]	190987	1			T1	280		T2	49		T3	60
valid_sources[0x14]	209905	1			T1	283		T2	37		T3	43
valid_sources[0x15]	199967	1			T1	281		T2	42		T3	45
valid_sources[0x16]	198796	1			T1	335		T2	50		T3	52
valid_sources[0x17]	208328	1			T1	289		T2	102		T3	41
valid_sources[0x18]	187708	1			T1	330		T2	53		T3	31
valid_sources[0x19]	187909	1			T1	321		T2	117		T3	39
valid_sources[0x1a]	200582	1			T1	260		T2	52		T3	57
valid_sources[0x1b]	195224	1			T1	275		T2	66		T3	57
valid_sources[0x1c]	191774	1			T1	284		T2	67		T3	50
valid_sources[0x1d]	198724	1			T1	294		T2	12		T3	64
valid_sources[0x1e]	198104	1			T1	250		T2	64		T3	57
valid_sources[0x1f]	200171	1			T1	288		T2	96		T3	54
valid_sources[0x20]	210398	1			T1	302		T2	67		T3	41
valid_sources[0x21]	198827	1			T1	269		T2	96		T3	37
valid_sources[0x22]	206643	1			T1	317		T2	49		T3	47
valid_sources[0x23]	190880	1			T1	262		T2	69		T3	45
valid_sources[0x24]	212094	1			T1	282		T2	46		T3	53
valid_sources[0x25]	194452	1			T1	305		T2	27		T3	67
valid_sources[0x26]	209093	1			T1	322		T2	53		T3	49
valid_sources[0x27]	194345	1			T1	279		T2	62		T3	41
valid_sources[0x28]	205654	1			T1	300		T2	69		T3	46
valid_sources[0x29]	205496	1			T1	297		T2	97		T3	42
valid_sources[0x2a]	185942	1			T1	262		T2	78		T3	42
valid_sources[0x2b]	194653	1			T1	318		T2	89		T3	53
valid_sources[0x2c]	196838	1			T1	325		T2	94		T3	47
valid_sources[0x2d]	205955	1			T1	288		T2	66		T3	45
valid_sources[0x2e]	192332	1			T1	328		T2	92		T3	71
valid_sources[0x2f]	200002	1			T1	321		T2	64		T3	57
valid_sources[0x30]	200899	1			T1	273		T2	58		T3	57
valid_sources[0x31]	186634	1			T1	325		T2	51		T3	57
valid_sources[0x32]	190887	1			T1	300		T2	61		T3	45
valid_sources[0x33]	202524	1			T1	240		T2	72		T3	43
valid_sources[0x34]	204146	1			T1	327		T2	37		T3	57
valid_sources[0x35]	189321	1			T1	303		T2	69		T3	44
valid_sources[0x36]	193823	1			T1	271		T2	42		T3	55
valid_sources[0x37]	200721	1			T1	279		T2	46		T3	39
valid_sources[0x38]	208941	1			T1	284		T2	35		T3	39
valid_sources[0x39]	187357	1			T1	274		T2	57		T3	52
valid_sources[0x3a]	202273	1			T1	337		T2	31		T3	49
valid_sources[0x3b]	241271	1			T1	341		T2	27		T3	55
valid_sources[0x3c]	194850	1			T1	342		T2	72		T3	45
valid_sources[0x3d]	213597	1			T1	270		T2	70		T3	54
valid_sources[0x3e]	205406	1			T1	246		T2	45		T3	44
valid_sources[0x3f]	197358	1			T1	327		T2	34		T3	49
valid_sources[0x40]	198955	1			T1	382		T2	41		T3	63
valid_sources[0x41]	186227	1			T1	300		T2	35		T3	72
valid_sources[0x42]	199636	1			T1	353		T2	50		T3	52
valid_sources[0x43]	268033	1			T1	274		T2	80		T3	53
valid_sources[0x44]	190891	1			T1	305		T2	34		T3	40
valid_sources[0x45]	201759	1			T1	280		T2	42		T3	46
valid_sources[0x46]	208140	1			T1	309		T2	50		T3	43
valid_sources[0x47]	215407	1			T1	315		T2	40		T3	38
valid_sources[0x48]	204658	1			T1	292		T2	45		T3	35
valid_sources[0x49]	195298	1			T1	262		T2	65		T3	55
valid_sources[0x4a]	190552	1			T1	308		T2	38		T3	57
valid_sources[0x4b]	197566	1			T1	335		T2	43		T3	50
valid_sources[0x4c]	188658	1			T1	322		T2	46		T3	49
valid_sources[0x4d]	203628	1			T1	339		T2	67		T3	47
valid_sources[0x4e]	254804	1			T1	366		T2	54		T3	49
valid_sources[0x4f]	193340	1			T1	275		T2	20		T3	61
valid_sources[0x50]	219149	1			T1	338		T2	97		T3	54
valid_sources[0x51]	183692	1			T1	300		T2	68		T3	59
valid_sources[0x52]	202781	1			T1	294		T2	26		T3	35
valid_sources[0x53]	556121	1			T1	253		T2	66		T3	53
valid_sources[0x54]	190679	1			T1	279		T2	126		T3	52
valid_sources[0x55]	196010	1			T1	338		T2	45		T3	63
valid_sources[0x56]	181527	1			T1	375		T2	54		T3	44
valid_sources[0x57]	197512	1			T1	295		T2	36		T3	55
valid_sources[0x58]	186088	1			T1	318		T2	42		T3	75
valid_sources[0x59]	203930	1			T1	315		T2	40		T3	53
valid_sources[0x5a]	207666	1			T1	277		T2	44		T3	59
valid_sources[0x5b]	434557	1			T1	270		T2	49		T3	70
valid_sources[0x5c]	288533	1			T1	283		T2	46		T3	42
valid_sources[0x5d]	192926	1			T1	343		T2	58		T3	40
valid_sources[0x5e]	213590	1			T1	281		T2	49		T3	49
valid_sources[0x5f]	215328	1			T1	305		T2	59		T3	50
valid_sources[0x60]	189363	1			T1	320		T2	45		T3	45
valid_sources[0x61]	185574	1			T1	311		T2	126		T3	41
valid_sources[0x62]	187487	1			T1	287		T2	80		T3	41
valid_sources[0x63]	218838	1			T1	336		T2	42		T3	40
valid_sources[0x64]	289376	1			T1	293		T2	74		T3	43
valid_sources[0x65]	188612	1			T1	350		T2	91		T3	57
valid_sources[0x66]	209471	1			T1	314		T2	52		T3	49
valid_sources[0x67]	182396	1			T1	323		T2	74		T3	51
valid_sources[0x68]	187277	1			T1	303		T2	45		T3	61
valid_sources[0x69]	195938	1			T1	337		T2	122		T3	32
valid_sources[0x6a]	193289	1			T1	317		T2	31		T3	52
valid_sources[0x6b]	316223	1			T1	342		T2	55		T3	53
valid_sources[0x6c]	215144	1			T1	310		T2	64		T3	50
valid_sources[0x6d]	200291	1			T1	301		T2	23		T3	52
valid_sources[0x6e]	200698	1			T1	309		T2	69		T3	67
valid_sources[0x6f]	215673	1			T1	335		T2	42		T3	51
valid_sources[0x70]	198206	1			T1	297		T2	103		T3	45
valid_sources[0x71]	194005	1			T1	324		T2	47		T3	53
valid_sources[0x72]	231161	1			T1	330		T2	87		T3	43
valid_sources[0x73]	215350	1			T1	340		T2	58		T3	55
valid_sources[0x74]	203643	1			T1	327		T2	66		T3	46
valid_sources[0x75]	195504	1			T1	310		T2	59		T3	42
valid_sources[0x76]	213345	1			T1	310		T2	53		T3	49
valid_sources[0x77]	192782	1			T1	348		T2	47		T3	56
valid_sources[0x78]	213839	1			T1	304		T2	52		T3	53
valid_sources[0x79]	195734	1			T1	325		T2	86		T3	54
valid_sources[0x7a]	207857	1			T1	288		T2	105		T3	40
valid_sources[0x7b]	198956	1			T1	321		T2	32		T3	42
valid_sources[0x7c]	192361	1			T1	287		T2	72		T3	59
valid_sources[0x7d]	222895	1			T1	304		T2	99		T3	35
valid_sources[0x7e]	194617	1			T1	269		T2	66		T3	47
valid_sources[0x7f]	224432	1			T1	351		T2	58		T3	59
valid_sources[0x80]	177786	1			T1	296		T2	60		T3	43

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

10142752

1

T1

38340

T2

4220

T3

3262

values[0x0]

all_enables

biggest_size

239025

1

T1

57

T2

289

T3

174

values[0x1]

all_enables

biggest_size

162757

1

T1

59

T2

246

T3

151