Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.83	100.00	83.33			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf	93.75	100.00	75.00			100.00	100.00
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf	93.75	100.00	75.00			100.00	100.00
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf	93.75	100.00	75.00			100.00	100.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf	93.75	100.00	75.00			100.00	100.00
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf	94.79	100.00	79.17			100.00	100.00
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf	94.79	100.00	79.17			100.00	100.00
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf	95.83	100.00	83.33			100.00	100.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf	95.83	100.00	83.33			100.00	100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.32	100.00	81.82			95.45	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.59	100.00	82.35			100.00	100.00	u_fmt_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	94.10	100.00	90.00			92.31

---

Module Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.32	100.00	81.82			95.45	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.12	100.00	76.47			100.00	100.00	u_rx_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	94.10	100.00	90.00			92.31

---

Module Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.32	100.00	81.82			95.45	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.59	100.00	82.35			100.00	100.00	u_tx_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	94.10	100.00	90.00			92.31

---

Module Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.32	100.00	81.82			95.45	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.08	100.00	84.31			100.00	100.00	u_acq_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	94.10	100.00	90.00			92.31

---

Module Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.79	100.00	79.17			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.16	100.00	88.64			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.12	100.00	76.47			100.00	100.00	u_rx_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.79	100.00	79.17			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.16	100.00	88.64			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.59	100.00	82.35			100.00	100.00	u_tx_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.83	100.00	83.33			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.59	100.00	82.35			100.00	100.00	u_fmt_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.83	100.00	83.33			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.08	100.00	84.31			100.00	100.00	u_acq_fifo_sram_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	24	20	83.33
Logical	24	20	83.33
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	504522281	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	2147483647	504522281	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	504522281	0	0
T1	629052	153674	0	0
T2	658124	154734	0	0
T3	373608	85306	0	0
T4	70256	15421	0	0
T5	826984	205896	0	0
T6	1232792	72976	0	0
T7	1448976	179662	0	0
T8	617800	48598	0	0
T9	66896	6708	0	0
T10	466536	37246	0	0
T16	620880	1763	0	0
T20	0	260132	0	0
T33	390660	46255	0	0
T34	0	476606	0	0
T35	0	488032	0	0
T36	0	231588	0	0
T37	0	233061	0	0
T39	532192	128886	0	0
T40	329620	78336	0	0
T41	58076	11812	0	0
T61	0	167	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1258104	1257432	0	0
T2	1316248	1315816	0	0
T3	747216	745784	0	0
T4	140512	139800	0	0
T5	1653968	1653480	0	0
T6	1232792	1232200	0	0
T7	1448976	1448176	0	0
T8	617800	617240	0	0
T9	66896	66312	0	0
T10	466536	465768	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1258104	1257432	0	0
T2	1316248	1315816	0	0
T3	747216	745784	0	0
T4	140512	139800	0	0
T5	1653968	1653480	0	0
T6	1232792	1232200	0	0
T7	1448976	1448176	0	0
T8	617800	617240	0	0
T9	66896	66312	0	0
T10	466536	465768	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1258104	1257432	0	0
T2	1316248	1315816	0	0
T3	747216	745784	0	0
T4	140512	139800	0	0
T5	1653968	1653480	0	0
T6	1232792	1232200	0	0
T7	1448976	1448176	0	0
T8	617800	617240	0	0
T9	66896	66312	0	0
T10	466536	465768	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	504522281	0	0
T1	629052	153674	0	0
T2	658124	154734	0	0
T3	373608	85306	0	0
T4	70256	15421	0	0
T5	826984	205896	0	0
T6	1232792	72976	0	0
T7	1448976	179662	0	0
T8	617800	48598	0	0
T9	66896	6708	0	0
T10	466536	37246	0	0
T16	620880	1763	0	0
T20	0	260132	0	0
T33	390660	46255	0	0
T34	0	476606	0	0
T35	0	488032	0	0
T36	0	231588	0	0
T37	0	233061	0	0
T39	532192	128886	0	0
T40	329620	78336	0	0
T41	58076	11812	0	0
T61	0	167	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	411754288	199523	0	0
DepthKnown_A	411754288	411581215	0	0
RvalidKnown_A	411754288	411581215	0	0
WreadyKnown_A	411754288	411581215	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	411754288	199523	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	199523	0	0
T1	157263	30	0	0
T2	164531	130	0	0
T3	93402	84	0	0
T4	17564	96	0	0
T5	206746	742	0	0
T6	154099	0	0	0
T7	181122	643	0	0
T8	77225	0	0	0
T9	8362	106	0	0
T10	58317	0	0	0
T39	0	126	0	0
T40	0	271	0	0
T41	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	411581215	0	0
T1	157263	157179	0	0
T2	164531	164477	0	0
T3	93402	93223	0	0
T4	17564	17475	0	0
T5	206746	206685	0	0
T6	154099	154025	0	0
T7	181122	181022	0	0
T8	77225	77155	0	0
T9	8362	8289	0	0
T10	58317	58221	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	411581215	0	0
T1	157263	157179	0	0
T2	164531	164477	0	0
T3	93402	93223	0	0
T4	17564	17475	0	0
T5	206746	206685	0	0
T6	154099	154025	0	0
T7	181122	181022	0	0
T8	77225	77155	0	0
T9	8362	8289	0	0
T10	58317	58221	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	411581215	0	0
T1	157263	157179	0	0
T2	164531	164477	0	0
T3	93402	93223	0	0
T4	17564	17475	0	0
T5	206746	206685	0	0
T6	154099	154025	0	0
T7	181122	181022	0	0
T8	77225	77155	0	0
T9	8362	8289	0	0
T10	58317	58221	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	199523	0	0
T1	157263	30	0	0
T2	164531	130	0	0
T3	93402	84	0	0
T4	17564	96	0	0
T5	206746	742	0	0
T6	154099	0	0	0
T7	181122	643	0	0
T8	77225	0	0	0
T9	8362	106	0	0
T10	58317	0	0	0
T39	0	126	0	0
T40	0	271	0	0
T41	0	2	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T55,T82
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T55,T82
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	411754288	382868	0	0
DepthKnown_A	411754288	411581215	0	0
RvalidKnown_A	411754288	411581215	0	0
WreadyKnown_A	411754288	411581215	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	411754288	382868	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	382868	0	0
T1	157263	960	0	0
T2	164531	929	0	0
T3	93402	504	0	0
T4	17564	0	0	0
T5	206746	512	0	0
T6	154099	0	0	0
T7	181122	513	0	0
T8	77225	0	0	0
T9	8362	0	0	0
T10	58317	0	0	0
T39	0	771	0	0
T40	0	218	0	0
T41	0	64	0	0
T61	0	167	0	0
T62	0	125	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	411581215	0	0
T1	157263	157179	0	0
T2	164531	164477	0	0
T3	93402	93223	0	0
T4	17564	17475	0	0
T5	206746	206685	0	0
T6	154099	154025	0	0
T7	181122	181022	0	0
T8	77225	77155	0	0
T9	8362	8289	0	0
T10	58317	58221	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	411581215	0	0
T1	157263	157179	0	0
T2	164531	164477	0	0
T3	93402	93223	0	0
T4	17564	17475	0	0
T5	206746	206685	0	0
T6	154099	154025	0	0
T7	181122	181022	0	0
T8	77225	77155	0	0
T9	8362	8289	0	0
T10	58317	58221	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	411581215	0	0
T1	157263	157179	0	0
T2	164531	164477	0	0
T3	93402	93223	0	0
T4	17564	17475	0	0
T5	206746	206685	0	0
T6	154099	154025	0	0
T7	181122	181022	0	0
T8	77225	77155	0	0
T9	8362	8289	0	0
T10	58317	58221	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	382868	0	0
T1	157263	960	0	0
T2	164531	929	0	0
T3	93402	504	0	0
T4	17564	0	0	0
T5	206746	512	0	0
T6	154099	0	0	0
T7	181122	513	0	0
T8	77225	0	0	0
T9	8362	0	0	0
T10	58317	0	0	0
T39	0	771	0	0
T40	0	218	0	0
T41	0	64	0	0
T61	0	167	0	0
T62	0	125	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T6,T8,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T6,T8,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T16,T33,T34
1	1	0	Not Covered
1	1	1	Covered	T6,T8,T10

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T8,T10

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T8,T10

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T16,T33,T34
1	0	Covered	T6,T8,T10
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T6,T8,T10
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T8,T10

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	411754288	255427	0	0
DepthKnown_A	411754288	411581215	0	0
RvalidKnown_A	411754288	411581215	0	0
WreadyKnown_A	411754288	411581215	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	411754288	255427	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	255427	0	0
T6	154099	355	0	0
T7	181122	0	0	0
T8	77225	146	0	0
T9	8362	0	0	0
T10	58317	47	0	0
T16	155220	678	0	0
T33	97665	310	0	0
T34	0	4454	0	0
T35	0	2852	0	0
T36	0	26	0	0
T37	0	1785	0	0
T38	0	108	0	0
T39	133048	0	0	0
T40	82405	0	0	0
T41	14519	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	411581215	0	0
T1	157263	157179	0	0
T2	164531	164477	0	0
T3	93402	93223	0	0
T4	17564	17475	0	0
T5	206746	206685	0	0
T6	154099	154025	0	0
T7	181122	181022	0	0
T8	77225	77155	0	0
T9	8362	8289	0	0
T10	58317	58221	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	411581215	0	0
T1	157263	157179	0	0
T2	164531	164477	0	0
T3	93402	93223	0	0
T4	17564	17475	0	0
T5	206746	206685	0	0
T6	154099	154025	0	0
T7	181122	181022	0	0
T8	77225	77155	0	0
T9	8362	8289	0	0
T10	58317	58221	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	411581215	0	0
T1	157263	157179	0	0
T2	164531	164477	0	0
T3	93402	93223	0	0
T4	17564	17475	0	0
T5	206746	206685	0	0
T6	154099	154025	0	0
T7	181122	181022	0	0
T8	77225	77155	0	0
T9	8362	8289	0	0
T10	58317	58221	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	255427	0	0
T6	154099	355	0	0
T7	181122	0	0	0
T8	77225	146	0	0
T9	8362	0	0	0
T10	58317	47	0	0
T16	155220	678	0	0
T33	97665	310	0	0
T34	0	4454	0	0
T35	0	2852	0	0
T36	0	26	0	0
T37	0	1785	0	0
T38	0	108	0	0
T39	133048	0	0	0
T40	82405	0	0	0
T41	14519	0	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T6,T8,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T6,T8,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T34,T35,T37
1	1	0	Not Covered
1	1	1	Covered	T6,T8,T10

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T8,T10

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T8,T10

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T37
1	0	Covered	T6,T8,T10
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T6,T8,T10
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T8,T10

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	411754288	277148	0	0
DepthKnown_A	411754288	411581215	0	0
RvalidKnown_A	411754288	411581215	0	0
WreadyKnown_A	411754288	411581215	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	411754288	277148	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	277148	0	0
T6	154099	394	0	0
T7	181122	0	0	0
T8	77225	303	0	0
T9	8362	0	0	0
T10	58317	144	0	0
T16	155220	80	0	0
T20	0	346	0	0
T33	97665	279	0	0
T34	0	2111	0	0
T35	0	1622	0	0
T36	0	126	0	0
T37	0	753	0	0
T39	133048	0	0	0
T40	82405	0	0	0
T41	14519	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	411581215	0	0
T1	157263	157179	0	0
T2	164531	164477	0	0
T3	93402	93223	0	0
T4	17564	17475	0	0
T5	206746	206685	0	0
T6	154099	154025	0	0
T7	181122	181022	0	0
T8	77225	77155	0	0
T9	8362	8289	0	0
T10	58317	58221	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	411581215	0	0
T1	157263	157179	0	0
T2	164531	164477	0	0
T3	93402	93223	0	0
T4	17564	17475	0	0
T5	206746	206685	0	0
T6	154099	154025	0	0
T7	181122	181022	0	0
T8	77225	77155	0	0
T9	8362	8289	0	0
T10	58317	58221	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	411581215	0	0
T1	157263	157179	0	0
T2	164531	164477	0	0
T3	93402	93223	0	0
T4	17564	17475	0	0
T5	206746	206685	0	0
T6	154099	154025	0	0
T7	181122	181022	0	0
T8	77225	77155	0	0
T9	8362	8289	0	0
T10	58317	58221	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	277148	0	0
T6	154099	394	0	0
T7	181122	0	0	0
T8	77225	303	0	0
T9	8362	0	0	0
T10	58317	144	0	0
T16	155220	80	0	0
T20	0	346	0	0
T33	97665	279	0	0
T34	0	2111	0	0
T35	0	1622	0	0
T36	0	126	0	0
T37	0	753	0	0
T39	133048	0	0	0
T40	82405	0	0	0
T41	14519	0	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf

	Total	Covered	Percent
Conditions	24	19	79.17
Logical	24	19	79.17
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	411754288	34666322	0	0
DepthKnown_A	411754288	411581215	0	0
RvalidKnown_A	411754288	411581215	0	0
WreadyKnown_A	411754288	411581215	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	411754288	34666322	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	34666322	0	0
T1	157263	151621	0	0
T2	164531	28590	0	0
T3	93402	11106	0	0
T4	17564	0	0	0
T5	206746	32440	0	0
T6	154099	0	0	0
T7	181122	13757	0	0
T8	77225	0	0	0
T9	8362	0	0	0
T10	58317	0	0	0
T39	0	4923	0	0
T40	0	2402	0	0
T41	0	11345	0	0
T61	0	5425	0	0
T62	0	1313	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	411581215	0	0
T1	157263	157179	0	0
T2	164531	164477	0	0
T3	93402	93223	0	0
T4	17564	17475	0	0
T5	206746	206685	0	0
T6	154099	154025	0	0
T7	181122	181022	0	0
T8	77225	77155	0	0
T9	8362	8289	0	0
T10	58317	58221	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	411581215	0	0
T1	157263	157179	0	0
T2	164531	164477	0	0
T3	93402	93223	0	0
T4	17564	17475	0	0
T5	206746	206685	0	0
T6	154099	154025	0	0
T7	181122	181022	0	0
T8	77225	77155	0	0
T9	8362	8289	0	0
T10	58317	58221	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	411581215	0	0
T1	157263	157179	0	0
T2	164531	164477	0	0
T3	93402	93223	0	0
T4	17564	17475	0	0
T5	206746	206685	0	0
T6	154099	154025	0	0
T7	181122	181022	0	0
T8	77225	77155	0	0
T9	8362	8289	0	0
T10	58317	58221	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	34666322	0	0
T1	157263	151621	0	0
T2	164531	28590	0	0
T3	93402	11106	0	0
T4	17564	0	0	0
T5	206746	32440	0	0
T6	154099	0	0	0
T7	181122	13757	0	0
T8	77225	0	0	0
T9	8362	0	0	0
T10	58317	0	0	0
T39	0	4923	0	0
T40	0	2402	0	0
T41	0	11345	0	0
T61	0	5425	0	0
T62	0	1313	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf

	Total	Covered	Percent
Conditions	24	19	79.17
Logical	24	19	79.17
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T6,T8,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T6,T8,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T6,T8,T10
1	1	0	Not Covered
1	1	1	Covered	T6,T8,T10

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T8,T10

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T8,T10

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T10
1	0	Covered	T6,T8,T10
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T6,T8,T10
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T8,T10

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	411754288	109318698	0	0
DepthKnown_A	411754288	411581215	0	0
RvalidKnown_A	411754288	411581215	0	0
WreadyKnown_A	411754288	411581215	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	411754288	109318698	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	109318698	0	0
T6	154099	75375	0	0
T7	181122	0	0	0
T8	77225	26528	0	0
T9	8362	0	0	0
T10	58317	9922	0	0
T16	155220	141720	0	0
T33	97665	52432	0	0
T34	0	961060	0	0
T35	0	915671	0	0
T36	0	148958	0	0
T37	0	477700	0	0
T38	0	49647	0	0
T39	133048	0	0	0
T40	82405	0	0	0
T41	14519	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	411581215	0	0
T1	157263	157179	0	0
T2	164531	164477	0	0
T3	93402	93223	0	0
T4	17564	17475	0	0
T5	206746	206685	0	0
T6	154099	154025	0	0
T7	181122	181022	0	0
T8	77225	77155	0	0
T9	8362	8289	0	0
T10	58317	58221	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	411581215	0	0
T1	157263	157179	0	0
T2	164531	164477	0	0
T3	93402	93223	0	0
T4	17564	17475	0	0
T5	206746	206685	0	0
T6	154099	154025	0	0
T7	181122	181022	0	0
T8	77225	77155	0	0
T9	8362	8289	0	0
T10	58317	58221	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	411581215	0	0
T1	157263	157179	0	0
T2	164531	164477	0	0
T3	93402	93223	0	0
T4	17564	17475	0	0
T5	206746	206685	0	0
T6	154099	154025	0	0
T7	181122	181022	0	0
T8	77225	77155	0	0
T9	8362	8289	0	0
T10	58317	58221	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	109318698	0	0
T6	154099	75375	0	0
T7	181122	0	0	0
T8	77225	26528	0	0
T9	8362	0	0	0
T10	58317	9922	0	0
T16	155220	141720	0	0
T33	97665	52432	0	0
T34	0	961060	0	0
T35	0	915671	0	0
T36	0	148958	0	0
T37	0	477700	0	0
T38	0	49647	0	0
T39	133048	0	0	0
T40	82405	0	0	0
T41	14519	0	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf

	Total	Covered	Percent
Conditions	24	20	83.33
Logical	24	20	83.33
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T39,T66
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	411754288	148845987	0	0
DepthKnown_A	411754288	411581215	0	0
RvalidKnown_A	411754288	411581215	0	0
WreadyKnown_A	411754288	411581215	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	411754288	148845987	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	148845987	0	0
T1	157263	152684	0	0
T2	164531	153675	0	0
T3	93402	84718	0	0
T4	17564	15325	0	0
T5	206746	204642	0	0
T6	154099	0	0	0
T7	181122	178506	0	0
T8	77225	0	0	0
T9	8362	6602	0	0
T10	58317	0	0	0
T39	0	127989	0	0
T40	0	77847	0	0
T41	0	11746	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	411581215	0	0
T1	157263	157179	0	0
T2	164531	164477	0	0
T3	93402	93223	0	0
T4	17564	17475	0	0
T5	206746	206685	0	0
T6	154099	154025	0	0
T7	181122	181022	0	0
T8	77225	77155	0	0
T9	8362	8289	0	0
T10	58317	58221	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	411581215	0	0
T1	157263	157179	0	0
T2	164531	164477	0	0
T3	93402	93223	0	0
T4	17564	17475	0	0
T5	206746	206685	0	0
T6	154099	154025	0	0
T7	181122	181022	0	0
T8	77225	77155	0	0
T9	8362	8289	0	0
T10	58317	58221	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	411581215	0	0
T1	157263	157179	0	0
T2	164531	164477	0	0
T3	93402	93223	0	0
T4	17564	17475	0	0
T5	206746	206685	0	0
T6	154099	154025	0	0
T7	181122	181022	0	0
T8	77225	77155	0	0
T9	8362	8289	0	0
T10	58317	58221	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	148845987	0	0
T1	157263	152684	0	0
T2	164531	153675	0	0
T3	93402	84718	0	0
T4	17564	15325	0	0
T5	206746	204642	0	0
T6	154099	0	0	0
T7	181122	178506	0	0
T8	77225	0	0	0
T9	8362	6602	0	0
T10	58317	0	0	0
T39	0	127989	0	0
T40	0	77847	0	0
T41	0	11746	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf

	Total	Covered	Percent
Conditions	24	20	83.33
Logical	24	20	83.33
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T6,T8,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T6,T8,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T83,T84,T85
1	0	1	Covered	T6,T8,T10
1	1	0	Not Covered
1	1	1	Covered	T6,T8,T10

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T8,T10

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T8,T10

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T10
1	0	Covered	T6,T8,T10
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T6,T8,T10
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T8,T10

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	411754288	210576308	0	0
DepthKnown_A	411754288	411581215	0	0
RvalidKnown_A	411754288	411581215	0	0
WreadyKnown_A	411754288	411581215	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	411754288	210576308	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	210576308	0	0
T6	154099	72582	0	0
T7	181122	0	0	0
T8	77225	48295	0	0
T9	8362	0	0	0
T10	58317	37102	0	0
T16	155220	1683	0	0
T20	0	259786	0	0
T33	97665	45976	0	0
T34	0	474495	0	0
T35	0	486410	0	0
T36	0	231462	0	0
T37	0	232308	0	0
T39	133048	0	0	0
T40	82405	0	0	0
T41	14519	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	411581215	0	0
T1	157263	157179	0	0
T2	164531	164477	0	0
T3	93402	93223	0	0
T4	17564	17475	0	0
T5	206746	206685	0	0
T6	154099	154025	0	0
T7	181122	181022	0	0
T8	77225	77155	0	0
T9	8362	8289	0	0
T10	58317	58221	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	411581215	0	0
T1	157263	157179	0	0
T2	164531	164477	0	0
T3	93402	93223	0	0
T4	17564	17475	0	0
T5	206746	206685	0	0
T6	154099	154025	0	0
T7	181122	181022	0	0
T8	77225	77155	0	0
T9	8362	8289	0	0
T10	58317	58221	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	411581215	0	0
T1	157263	157179	0	0
T2	164531	164477	0	0
T3	93402	93223	0	0
T4	17564	17475	0	0
T5	206746	206685	0	0
T6	154099	154025	0	0
T7	181122	181022	0	0
T8	77225	77155	0	0
T9	8362	8289	0	0
T10	58317	58221	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	411754288	210576308	0	0
T6	154099	72582	0	0
T7	181122	0	0	0
T8	77225	48295	0	0
T9	8362	0	0	0
T10	58317	37102	0	0
T16	155220	1683	0	0
T20	0	259786	0	0
T33	97665	45976	0	0
T34	0	474495	0	0
T35	0	486410	0	0
T36	0	231462	0	0
T37	0	232308	0	0
T39	133048	0	0	0
T40	82405	0	0	0
T41	14519	0	0	0