Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.72	100.00	100.00	94.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	412372379	7995	0	0
ctrl_rd_A	412372379	1408	0	0
host_fifo_config_rd_A	412372379	5498	0	0
host_nack_handler_timeout_rd_A	412372379	1237	0	0
host_timeout_ctrl_rd_A	412372379	1130	0	0
intr_enable_rd_A	412372379	2420	0	0
ovrd_rd_A	412372379	1959	0	0
target_fifo_config_rd_A	412372379	1355	0	0
target_id_rd_A	412372379	1469	0	0
target_timeout_ctrl_rd_A	412372379	1233	0	0
timeout_ctrl_rd_A	412372379	1160	0	0
timing0_rd_A	412372379	1153	0	0
timing1_rd_A	412372379	1315	0	0
timing2_rd_A	412372379	1073	0	0
timing3_rd_A	412372379	1220	0	0
timing4_rd_A	412372379	1259	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412372379	7995	0	0
T78	2261	5	0	0
T80	1993	8	0	0
T109	3080	459	0	0
T110	6675	257	0	0
T124	13173	685	0	0
T125	4567	1	0	0
T126	4918	1	0	0
T127	6910	3	0	0
T128	12388	534	0	0
T134	11635	577	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412372379	1408	0	0
T124	13173	22	0	0
T129	11111	3	0	0
T135	7052	102	0	0
T143	1713	20	0	0
T156	3520	22	0	0
T159	3553	4	0	0
T160	4821	21	0	0
T164	4472	9	0	0
T165	3122	34	0	0
T166	13177	44	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412372379	5498	0	0
T18	68438	0	0	0
T69	303315	158	0	0
T73	55527	0	0	0
T75	15292	0	0	0
T82	157790	0	0	0
T91	0	257	0	0
T163	0	137	0	0
T167	0	104	0	0
T168	0	232	0	0
T169	0	130	0	0
T170	0	209	0	0
T171	0	249	0	0
T172	0	222	0	0
T173	0	136	0	0
T174	129629	0	0	0
T175	45032	0	0	0
T176	44539	0	0	0
T177	13640	0	0	0
T178	96910	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412372379	1237	0	0
T124	13173	21	0	0
T129	11111	16	0	0
T134	11635	7	0	0
T135	7052	51	0	0
T143	1713	7	0	0
T156	3520	47	0	0
T158	3292	1	0	0
T159	3553	33	0	0
T160	4821	13	0	0
T165	3122	12	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412372379	1130	0	0
T124	13173	11	0	0
T129	11111	5	0	0
T134	11635	15	0	0
T135	7052	44	0	0
T143	1713	10	0	0
T156	3520	9	0	0
T158	3292	9	0	0
T159	3553	7	0	0
T160	4821	16	0	0
T165	3122	16	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412372379	2420	0	0
T18	68438	0	0	0
T69	303315	9	0	0
T73	55527	0	0	0
T75	15292	0	0	0
T82	157790	0	0	0
T124	0	10	0	0
T134	0	4	0	0
T163	0	37	0	0
T174	129629	0	0	0
T175	45032	0	0	0
T176	44539	0	0	0
T177	13640	0	0	0
T178	96910	0	0	0
T179	0	42	0	0
T180	0	6	0	0
T181	0	19	0	0
T182	0	6	0	0
T183	0	26	0	0
T184	0	15	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412372379	1959	0	0
T185	1494	68	0	0
T186	0	31	0	0
T187	0	19	0	0
T188	0	48	0	0
T189	0	15	0	0
T190	0	53	0	0
T191	0	35	0	0
T192	0	28	0	0
T193	0	43	0	0
T194	0	44	0	0
T195	52276	0	0	0
T196	314783	0	0	0
T197	38219	0	0	0
T198	170529	0	0	0
T199	388646	0	0	0
T200	70225	0	0	0
T201	9546	0	0	0
T202	162153	0	0	0
T203	145939	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412372379	1355	0	0
T124	13173	26	0	0
T129	11111	20	0	0
T134	11635	22	0	0
T135	7052	57	0	0
T143	1713	9	0	0
T156	3520	25	0	0
T158	3292	8	0	0
T159	3553	18	0	0
T160	4821	28	0	0
T165	3122	17	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412372379	1469	0	0
T124	13173	24	0	0
T129	11111	22	0	0
T134	11635	6	0	0
T135	7052	86	0	0
T156	3520	17	0	0
T158	3292	9	0	0
T159	3553	3	0	0
T160	4821	31	0	0
T164	4472	6	0	0
T165	3122	36	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412372379	1233	0	0
T124	13173	40	0	0
T129	11111	7	0	0
T134	11635	22	0	0
T135	7052	62	0	0
T143	1713	4	0	0
T158	3292	17	0	0
T159	3553	17	0	0
T160	4821	15	0	0
T165	3122	31	0	0
T166	13177	15	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412372379	1160	0	0
T124	13173	57	0	0
T129	11111	16	0	0
T134	11635	17	0	0
T135	7052	32	0	0
T143	1713	3	0	0
T156	3520	8	0	0
T158	3292	3	0	0
T159	3553	26	0	0
T160	4821	36	0	0
T165	3122	18	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412372379	1153	0	0
T124	13173	17	0	0
T129	11111	17	0	0
T134	11635	13	0	0
T135	7052	50	0	0
T143	1713	13	0	0
T156	3520	10	0	0
T158	3292	1	0	0
T159	3553	8	0	0
T160	4821	23	0	0
T165	3122	17	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412372379	1315	0	0
T124	13173	11	0	0
T129	11111	16	0	0
T134	11635	3	0	0
T135	7052	57	0	0
T143	1713	16	0	0
T156	3520	34	0	0
T159	3553	2	0	0
T160	4821	24	0	0
T165	3122	16	0	0
T166	13177	20	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412372379	1073	0	0
T124	13173	11	0	0
T129	11111	26	0	0
T134	11635	6	0	0
T135	7052	52	0	0
T143	1713	12	0	0
T156	3520	8	0	0
T159	3553	7	0	0
T160	4821	21	0	0
T165	3122	16	0	0
T166	13177	4	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412372379	1220	0	0
T124	13173	24	0	0
T129	11111	11	0	0
T134	11635	15	0	0
T135	7052	53	0	0
T143	1713	10	0	0
T156	3520	46	0	0
T158	3292	1	0	0
T159	3553	1	0	0
T160	4821	24	0	0
T165	3122	14	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412372379	1259	0	0
T124	13173	14	0	0
T129	11111	29	0	0
T134	11635	19	0	0
T135	7052	64	0	0
T156	3520	23	0	0
T158	3292	9	0	0
T159	3553	11	0	0
T160	4821	37	0	0
T164	4472	1	0	0
T165	3122	17	0	0