Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

171465

1

T2

115

T3

87

T6

699

ack

15251

1

T2

10

T3

3

T6

69

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	689	1			T2	1		T3	1		T60	1
high	38559	1			T2	36		T3	22		T6	158
med	69477	1			T2	45		T3	32		T6	299
sml	77265	1			T2	43		T3	35		T6	305
all_zero	726	1			T6	6		T10	1		T44	16

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

92798

1

T2

56

T3

43

T6

392

auto[1]

93918

1

T2

69

T3

47

T6

376

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

128414

1

T2

97

T3

60

T6

537

auto[1]

58302

1

T2

28

T3

30

T6

231

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

178657

1

T2

125

T3

82

T6

738

auto[1]

8059

1

T3

8

T6

30

T8

34

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

176276

1

T2

115

T3

83

T6

710

auto[1]

10440

1

T2

10

T3

7

T6

58

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

177191

1

T2

115

T3

84

T6

714

auto[1]

9525

1

T2

10

T3

6

T6

54

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

92798

1

T2

56

T3

43

T6

392

auto[1]

93918

1

T2

69

T3

47

T6

376

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

128414

1

T2

97

T3

60

T6

537

auto[1]

58302

1

T2

28

T3

30

T6

231

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

178657

1

T2

125

T3

82

T6

738

auto[1]

8059

1

T3

8

T6

30

T8

34

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

176276

1

T2

115

T3

83

T6

710

auto[1]

10440

1

T2

10

T3

7

T6

58

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

177191

1

T2

115

T3

84

T6

714

auto[1]

9525

1

T2

10

T3

6

T6

54

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

6

1

T217

1

T228

1

T229

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

4

1

T73

1

T229

1

T230

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

2

1

T176

1

T231

1

-

-

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

303

1

T6

3

T44

3

T80

2

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

161

1

T6

1

T60

1

T44

5

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

162

1

T60

1

T44

1

T45

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

586

1

T6

6

T60

4

T44

6

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

309

1

T60

1

T44

7

T80

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

273

1

T6

5

T60

4

T44

6

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

531

1

T6

4

T60

4

T44

6

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

254

1

T6

4

T44

3

T45

5

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

292

1

T6

2

T60

1

T44

2

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

6

1

T172

1

T232

1

T233

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

3

1

T234

1

T235

1

T236

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

4

1

T172

1

T93

1

T237

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	54696	1			T2	37		T3	21		T6	216
write_address_byte	10440	1			T2	10		T3	7		T6	58
read_with_ack	2276	1			T3	5		T6	3		T8	15
read_with_nack	5783	1			T3	3		T6	27		T8	19
stop_byte	9525	1			T2	10		T3	6		T6	54
write_address_byte_nak	5270	1			T3	5		T6	40		T60	23
data_byte_nack	171465	1			T2	115		T3	87		T6	699
stop_byte_nack	5689	1			T2	10		T3	6		T6	38
nakok_byte_nack	86222	1			T2	62		T3	45		T6	343
nakok_addr_byte_nack	2640	1			T3	2		T6	18		T60	11