Summary for Variable address_match
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for address_match
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12439895 |
1 |
|
|
T1 |
13790 |
|
T4 |
18304 |
|
T5 |
154672 |
auto[1] |
16415071 |
1 |
|
|
T1 |
536 |
|
T2 |
3088 |
|
T3 |
5164 |
Summary for Variable cp_address_match
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for cp_address_match
Excluded/Illegal bins
NAME | COUNT | STATUS |
illegal |
0 |
Illegal |
ignore |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
read_addr_no_match |
6230377 |
1 |
|
|
T1 |
5655 |
|
T4 |
10721 |
|
T5 |
70305 |
read_addr_match |
11692159 |
1 |
|
|
T1 |
228 |
|
T3 |
3069 |
|
T4 |
420 |
write_addr_no_match |
6015154 |
1 |
|
|
T1 |
8115 |
|
T4 |
7563 |
|
T5 |
84345 |
write_addr_match |
4645746 |
1 |
|
|
T1 |
302 |
|
T2 |
3068 |
|
T3 |
2073 |
Summary for Variable cp_read_byte
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
5 |
1 |
4 |
80.00 |
User Defined Bins for cp_read_byte
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
all_one |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
high |
3639369 |
1 |
|
|
T1 |
987 |
|
T3 |
1121 |
|
T4 |
2392 |
med |
6969030 |
1 |
|
|
T1 |
2713 |
|
T3 |
1061 |
|
T4 |
4192 |
low |
7150753 |
1 |
|
|
T1 |
2155 |
|
T3 |
799 |
|
T4 |
4510 |
all_zero |
163384 |
1 |
|
|
T1 |
28 |
|
T3 |
88 |
|
T4 |
47 |
Summary for Variable cp_write_byte
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
5 |
1 |
4 |
80.00 |
User Defined Bins for cp_write_byte
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
all_one |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
high |
2164197 |
1 |
|
|
T1 |
1662 |
|
T2 |
623 |
|
T3 |
120 |
med |
4138418 |
1 |
|
|
T1 |
2952 |
|
T2 |
1437 |
|
T3 |
1803 |
low |
4254841 |
1 |
|
|
T1 |
3716 |
|
T2 |
953 |
|
T3 |
27 |
all_zero |
103444 |
1 |
|
|
T1 |
87 |
|
T2 |
55 |
|
T3 |
123 |
Summary for Variable ip_mode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for ip_mode_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
device |
13136359 |
1 |
|
|
T1 |
14326 |
|
T4 |
19000 |
|
T5 |
158888 |
host |
15718607 |
1 |
|
|
T2 |
3088 |
|
T3 |
5164 |
|
T6 |
49742 |
Summary for Cross cross_address_match_x_ip_mode
Samples crossed: address_match ip_mode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_address_match_x_ip_mode
Bins
address_match | ip_mode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
device |
12439817 |
1 |
|
|
T1 |
13790 |
|
T4 |
18304 |
|
T5 |
154672 |
auto[0] |
host |
78 |
1 |
|
|
T209 |
1 |
|
T162 |
1 |
|
T108 |
1 |
auto[1] |
device |
696542 |
1 |
|
|
T1 |
536 |
|
T4 |
696 |
|
T5 |
4216 |
auto[1] |
host |
15718529 |
1 |
|
|
T2 |
3088 |
|
T3 |
5164 |
|
T6 |
49742 |
Summary for Cross cross_write_byte_x_ip_mode
Samples crossed: cp_write_byte ip_mode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
10 |
2 |
8 |
80.00 |
2 |
Automatically Generated Cross Bins for cross_write_byte_x_ip_mode
Element holes
cp_write_byte | ip_mode_cp | COUNT | AT LEAST | NUMBER | STATUS |
[all_one] |
* |
-- |
-- |
2 |
|
Covered bins
cp_write_byte | ip_mode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
high |
device |
1281586 |
1 |
|
|
T1 |
1662 |
|
T4 |
1545 |
|
T5 |
17010 |
high |
host |
882611 |
1 |
|
|
T2 |
623 |
|
T3 |
120 |
|
T6 |
3511 |
med |
device |
2448481 |
1 |
|
|
T1 |
2952 |
|
T4 |
2699 |
|
T5 |
34899 |
med |
host |
1689937 |
1 |
|
|
T2 |
1437 |
|
T3 |
1803 |
|
T6 |
7068 |
low |
device |
2545142 |
1 |
|
|
T1 |
3716 |
|
T4 |
3513 |
|
T5 |
34202 |
low |
host |
1709699 |
1 |
|
|
T2 |
953 |
|
T3 |
27 |
|
T6 |
7372 |
all_zero |
device |
57967 |
1 |
|
|
T1 |
87 |
|
T4 |
77 |
|
T5 |
530 |
all_zero |
host |
45477 |
1 |
|
|
T2 |
55 |
|
T3 |
123 |
|
T6 |
195 |
Summary for Cross cross_read_byte_x_ip_mode
Samples crossed: cp_write_byte ip_mode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
10 |
2 |
8 |
80.00 |
2 |
Automatically Generated Cross Bins for cross_read_byte_x_ip_mode
Element holes
cp_write_byte | ip_mode_cp | COUNT | AT LEAST | NUMBER | STATUS |
[all_one] |
* |
-- |
-- |
2 |
|
Covered bins
cp_write_byte | ip_mode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
high |
device |
1281586 |
1 |
|
|
T1 |
1662 |
|
T4 |
1545 |
|
T5 |
17010 |
high |
host |
882611 |
1 |
|
|
T2 |
623 |
|
T3 |
120 |
|
T6 |
3511 |
med |
device |
2448481 |
1 |
|
|
T1 |
2952 |
|
T4 |
2699 |
|
T5 |
34899 |
med |
host |
1689937 |
1 |
|
|
T2 |
1437 |
|
T3 |
1803 |
|
T6 |
7068 |
low |
device |
2545142 |
1 |
|
|
T1 |
3716 |
|
T4 |
3513 |
|
T5 |
34202 |
low |
host |
1709699 |
1 |
|
|
T2 |
953 |
|
T3 |
27 |
|
T6 |
7372 |
all_zero |
device |
57967 |
1 |
|
|
T1 |
87 |
|
T4 |
77 |
|
T5 |
530 |
all_zero |
host |
45477 |
1 |
|
|
T2 |
55 |
|
T3 |
123 |
|
T6 |
195 |