Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	51198248	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

12021441

1

T1

279

T2

1104

T3

5798

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	62230066	1			T1	885		T2	2117		T3	22594
values[0x0]	494380	1			T1	162		T2	101		T3	137
values[0x1]	495243	1			T1	176		T2	91		T3	148

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36342586	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

26877103

1

T1

542

T2

1384

T3

10780

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	223134	1			T2	1		T3	87		T5	33
valid_sources[0x01]	258821	1			T2	4		T3	94		T4	37
valid_sources[0x02]	283930	1			T2	3		T3	83		T5	32
valid_sources[0x03]	223385	1			T3	93		T5	29		T6	801
valid_sources[0x04]	232929	1			T2	4		T3	92		T5	25
valid_sources[0x05]	242003	1			T2	29		T3	75		T5	29
valid_sources[0x06]	235579	1			T2	13		T3	102		T5	34
valid_sources[0x07]	243846	1			T3	77		T5	41		T6	793
valid_sources[0x08]	221263	1			T2	11		T3	86		T5	29
valid_sources[0x09]	302737	1			T2	4		T3	112		T4	63
valid_sources[0x0a]	225118	1			T2	10		T3	76		T4	46
valid_sources[0x0b]	255226	1			T2	13		T3	117		T5	32
valid_sources[0x0c]	232189	1			T2	5		T3	95		T5	26
valid_sources[0x0d]	229083	1			T2	16		T3	109		T5	23
valid_sources[0x0e]	238872	1			T2	27		T3	88		T4	34
valid_sources[0x0f]	259647	1			T2	16		T3	96		T5	38
valid_sources[0x10]	239311	1			T2	29		T3	75		T5	36
valid_sources[0x11]	234878	1			T2	1		T3	103		T5	31
valid_sources[0x12]	234335	1			T2	16		T3	80		T5	32
valid_sources[0x13]	234328	1			T2	10		T3	118		T5	28
valid_sources[0x14]	209515	1			T3	75		T5	33		T6	825
valid_sources[0x15]	227761	1			T2	10		T3	89		T5	28
valid_sources[0x16]	254779	1			T2	7		T3	80		T5	51
valid_sources[0x17]	260196	1			T2	2		T3	105		T5	47
valid_sources[0x18]	227210	1			T2	5		T3	103		T4	90
valid_sources[0x19]	222338	1			T3	90		T5	17		T6	852
valid_sources[0x1a]	231393	1			T2	1		T3	92		T4	47
valid_sources[0x1b]	237306	1			T2	13		T3	82		T5	28
valid_sources[0x1c]	418161	1			T3	89		T5	44		T6	880
valid_sources[0x1d]	226865	1			T2	6		T3	97		T5	48
valid_sources[0x1e]	248878	1			T2	3		T3	79		T4	43
valid_sources[0x1f]	234893	1			T3	80		T5	45		T6	809
valid_sources[0x20]	237419	1			T2	12		T3	74		T5	36
valid_sources[0x21]	270324	1			T2	1		T3	101		T5	34
valid_sources[0x22]	254105	1			T2	23		T3	90		T5	48
valid_sources[0x23]	224946	1			T2	2		T3	84		T5	25
valid_sources[0x24]	226847	1			T2	12		T3	95		T5	43
valid_sources[0x25]	243234	1			T2	13		T3	87		T5	26
valid_sources[0x26]	223432	1			T2	9		T3	90		T5	70
valid_sources[0x27]	234148	1			T1	56		T2	3		T3	89
valid_sources[0x28]	229135	1			T2	1		T3	97		T5	35
valid_sources[0x29]	248736	1			T2	19		T3	95		T5	41
valid_sources[0x2a]	461391	1			T2	21		T3	106		T5	32
valid_sources[0x2b]	231304	1			T2	8		T3	76		T5	36
valid_sources[0x2c]	435261	1			T2	13		T3	80		T5	27
valid_sources[0x2d]	235753	1			T2	11		T3	86		T5	48
valid_sources[0x2e]	237068	1			T2	14		T3	84		T5	23
valid_sources[0x2f]	250827	1			T2	11		T3	102		T5	21
valid_sources[0x30]	233460	1			T2	7		T3	84		T5	48
valid_sources[0x31]	266108	1			T3	92		T5	25		T6	803
valid_sources[0x32]	230145	1			T2	16		T3	80		T5	43
valid_sources[0x33]	213744	1			T2	3		T3	67		T5	41
valid_sources[0x34]	238114	1			T2	4		T3	66		T5	38
valid_sources[0x35]	221443	1			T2	11		T3	86		T5	18
valid_sources[0x36]	235164	1			T2	4		T3	113		T5	27
valid_sources[0x37]	231902	1			T3	94		T4	52		T5	18
valid_sources[0x38]	228662	1			T3	101		T5	26		T6	820
valid_sources[0x39]	228920	1			T2	7		T3	97		T5	30
valid_sources[0x3a]	223376	1			T2	16		T3	96		T5	40
valid_sources[0x3b]	227440	1			T3	82		T5	45		T6	804
valid_sources[0x3c]	240981	1			T2	3		T3	97		T5	48
valid_sources[0x3d]	246392	1			T2	18		T3	76		T5	53
valid_sources[0x3e]	220642	1			T2	11		T3	82		T5	33
valid_sources[0x3f]	240839	1			T2	18		T3	87		T5	26
valid_sources[0x40]	308495	1			T2	9		T3	63		T4	10
valid_sources[0x41]	244411	1			T2	10		T3	83		T5	31
valid_sources[0x42]	230181	1			T2	22		T3	101		T5	36
valid_sources[0x43]	229737	1			T1	1		T2	8		T3	88
valid_sources[0x44]	231921	1			T2	9		T3	88		T5	34
valid_sources[0x45]	234984	1			T2	12		T3	80		T4	5
valid_sources[0x46]	264483	1			T2	12		T3	98		T4	74
valid_sources[0x47]	229820	1			T2	7		T3	82		T5	36
valid_sources[0x48]	239087	1			T2	19		T3	98		T5	30
valid_sources[0x49]	241869	1			T2	6		T3	84		T5	30
valid_sources[0x4a]	225517	1			T2	6		T3	80		T4	68
valid_sources[0x4b]	221562	1			T3	72		T5	27		T6	806
valid_sources[0x4c]	228341	1			T2	12		T3	79		T5	37
valid_sources[0x4d]	229940	1			T2	14		T3	86		T5	25
valid_sources[0x4e]	227378	1			T1	1		T2	11		T3	71
valid_sources[0x4f]	227651	1			T2	15		T3	88		T5	42
valid_sources[0x50]	225458	1			T2	3		T3	80		T4	49
valid_sources[0x51]	241707	1			T2	4		T3	85		T5	25
valid_sources[0x52]	277658	1			T2	4		T3	78		T5	35
valid_sources[0x53]	661142	1			T3	93		T5	40		T6	865
valid_sources[0x54]	244026	1			T2	21		T3	85		T5	31
valid_sources[0x55]	255476	1			T2	8		T3	95		T4	71
valid_sources[0x56]	283531	1			T2	7		T3	113		T5	43
valid_sources[0x57]	255155	1			T2	11		T3	90		T5	31
valid_sources[0x58]	242400	1			T2	13		T3	82		T5	55
valid_sources[0x59]	213541	1			T2	3		T3	96		T4	8
valid_sources[0x5a]	227940	1			T2	5		T3	86		T5	16
valid_sources[0x5b]	222105	1			T3	88		T4	17		T5	34
valid_sources[0x5c]	238022	1			T2	3		T3	84		T5	43
valid_sources[0x5d]	272185	1			T2	12		T3	75		T4	14
valid_sources[0x5e]	233847	1			T1	104		T3	106		T5	26
valid_sources[0x5f]	233019	1			T2	4		T3	81		T5	29
valid_sources[0x60]	243421	1			T2	13		T3	81		T5	67
valid_sources[0x61]	217851	1			T2	3		T3	97		T4	8
valid_sources[0x62]	223259	1			T2	2		T3	88		T5	35
valid_sources[0x63]	228069	1			T2	6		T3	83		T5	38
valid_sources[0x64]	227086	1			T2	6		T3	93		T5	26
valid_sources[0x65]	214683	1			T3	83		T5	14		T6	801
valid_sources[0x66]	256031	1			T2	5		T3	90		T5	36
valid_sources[0x67]	236136	1			T2	5		T3	97		T5	23
valid_sources[0x68]	232016	1			T1	1		T2	8		T3	90
valid_sources[0x69]	222857	1			T2	32		T3	89		T4	58
valid_sources[0x6a]	238940	1			T2	4		T3	80		T5	40
valid_sources[0x6b]	244731	1			T2	13		T3	95		T5	27
valid_sources[0x6c]	283563	1			T2	15		T3	74		T5	29
valid_sources[0x6d]	234200	1			T2	3		T3	87		T5	37
valid_sources[0x6e]	215637	1			T3	73		T5	37		T6	872
valid_sources[0x6f]	233845	1			T2	15		T3	95		T5	44
valid_sources[0x70]	227524	1			T2	3		T3	107		T5	27
valid_sources[0x71]	222968	1			T2	5		T3	96		T5	25
valid_sources[0x72]	211136	1			T2	15		T3	107		T5	24
valid_sources[0x73]	239358	1			T2	2		T3	78		T5	34
valid_sources[0x74]	277253	1			T2	26		T3	94		T5	42
valid_sources[0x75]	224591	1			T2	21		T3	76		T5	26
valid_sources[0x76]	240189	1			T2	25		T3	88		T5	34
valid_sources[0x77]	314964	1			T2	11		T3	80		T5	32
valid_sources[0x78]	318659	1			T2	1		T3	88		T5	35
valid_sources[0x79]	223310	1			T3	84		T5	41		T6	823
valid_sources[0x7a]	225758	1			T2	10		T3	91		T5	37
valid_sources[0x7b]	227125	1			T2	5		T3	108		T5	31
valid_sources[0x7c]	225638	1			T1	198		T2	7		T3	96
valid_sources[0x7d]	239527	1			T1	1		T3	99		T5	47
valid_sources[0x7e]	257150	1			T1	288		T2	1		T3	107
valid_sources[0x7f]	236517	1			T2	11		T3	64		T5	35
valid_sources[0x80]	230174	1			T3	86		T5	39		T6	791

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

11599887

1

T1

159

T2

992

T3

5669

values[0x0]

all_enables

biggest_size

250913

1

T1

73

T2

65

T3

68

values[0x1]

all_enables

biggest_size

170641

1

T1

47

T2

47

T3

61