Unified Coverage Report :: Module :: prim_subreg_arb

Module : prim_subreg_arb

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.60	87.50	96.30			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_intr_state_fmt_threshold.wr_en_data_arb	50.00	50.00
tb.dut.u_reg.u_intr_state_rx_threshold.wr_en_data_arb	50.00	50.00
tb.dut.u_reg.u_intr_state_acq_threshold.wr_en_data_arb	50.00	50.00
tb.dut.u_reg.u_intr_state_controller_halt.wr_en_data_arb	50.00	50.00
tb.dut.u_reg.u_intr_state_tx_stretch.wr_en_data_arb	50.00	50.00
tb.dut.u_reg.u_intr_state_tx_threshold.wr_en_data_arb	50.00	50.00
tb.dut.u_reg.u_intr_state_acq_full.wr_en_data_arb	50.00	50.00
tb.dut.u_reg.u_controller_events_unhandled_nack_timeout.wr_en_data_arb	80.00	100.00	60.00
tb.dut.u_reg.u_target_nack_count.wr_en_data_arb	83.33	100.00	66.67
tb.dut.u_reg.u_intr_state_rx_overflow.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_intr_state_scl_interference.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_intr_state_sda_interference.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_intr_state_stretch_timeout.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_intr_state_sda_unstable.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_intr_state_cmd_complete.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_intr_state_unexp_stop.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_intr_state_host_timeout.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_intr_enable_fmt_threshold.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_rx_threshold.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_acq_threshold.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_rx_overflow.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_controller_halt.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_scl_interference.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_sda_interference.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_stretch_timeout.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_sda_unstable.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_cmd_complete.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_tx_stretch.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_tx_threshold.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_acq_full.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_unexp_stop.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_host_timeout.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ctrl_enablehost.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ctrl_enabletarget.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ctrl_llpbk.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fdata_fbyte.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fdata_start.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fdata_stop.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fdata_readb.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fdata_rcont.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fdata_nakok.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fifo_ctrl_rxrst.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fifo_ctrl_fmtrst.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fifo_ctrl_acqrst.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fifo_ctrl_txrst.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_host_fifo_config_rx_thresh.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_host_fifo_config_fmt_thresh.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_target_fifo_config_tx_thresh.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_target_fifo_config_txrst_on_cond.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_target_fifo_config_acq_thresh.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ovrd_txovrden.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ovrd_sclval.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ovrd_sdaval.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_timing0_thigh.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_timing0_tlow.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_timing1_t_r.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_timing1_t_f.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_timing2_tsu_sta.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_timing2_thd_sta.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_timing3_tsu_dat.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_timing3_thd_dat.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_timing4_tsu_sto.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_timing4_t_buf.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_timeout_ctrl_val.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_timeout_ctrl_en.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_target_id_address0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_target_id_mask0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_target_id_address1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_target_id_mask1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_txdata.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_host_timeout_ctrl.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_target_timeout_ctrl_val.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_target_timeout_ctrl_en.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_host_nack_handler_timeout_val.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_host_nack_handler_timeout_en.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_controller_events_nack.wr_en_data_arb	100.00	100.00	100.00

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=1,Mubi=0 )
Line Coverage for Module self-instances :

SCORE	LINE
50.00	50.00

tb.dut.u_reg.u_intr_state_fmt_threshold.wr_en_data_arb

SCORE	LINE
50.00	50.00

tb.dut.u_reg.u_intr_state_rx_threshold.wr_en_data_arb

SCORE	LINE
50.00	50.00

tb.dut.u_reg.u_intr_state_acq_threshold.wr_en_data_arb

SCORE	LINE
50.00	50.00

tb.dut.u_reg.u_intr_state_controller_halt.wr_en_data_arb

SCORE	LINE
50.00	50.00

tb.dut.u_reg.u_intr_state_tx_stretch.wr_en_data_arb

SCORE	LINE
50.00	50.00

tb.dut.u_reg.u_intr_state_tx_threshold.wr_en_data_arb

SCORE	LINE
50.00	50.00

tb.dut.u_reg.u_intr_state_acq_full.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	1	50.00
CONT_ASSIGN	43	1	0	0.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
43	0	1
44	1	1
51		unreachable
52		unreachable
53		unreachable

---

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_state_rx_overflow.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_state_scl_interference.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_state_sda_interference.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_state_stretch_timeout.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_state_sda_unstable.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_state_cmd_complete.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_state_unexp_stop.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_state_host_timeout.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_controller_events_nack.wr_en_data_arb

SCORE	LINE
80.00	100.00

tb.dut.u_reg.u_controller_events_unhandled_nack_timeout.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	110	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
88	1	1
110	1	1

---

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 + DW=8,SwAccess=2,Mubi=0 + DW=12,SwAccess=0,Mubi=0 + DW=16,SwAccess=0,Mubi=0 + DW=31,SwAccess=0,Mubi=0 + DW=7,SwAccess=0,Mubi=0 + DW=32,SwAccess=0,Mubi=0 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_fmt_threshold.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_rx_threshold.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_acq_threshold.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_rx_overflow.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_controller_halt.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_scl_interference.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_sda_interference.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_stretch_timeout.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_sda_unstable.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_cmd_complete.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_tx_stretch.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_tx_threshold.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_acq_full.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_unexp_stop.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_host_timeout.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ctrl_enablehost.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ctrl_enabletarget.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ctrl_llpbk.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_fdata_fbyte.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_fdata_start.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_fdata_stop.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_fdata_readb.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_fdata_rcont.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_fdata_nakok.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_fifo_ctrl_rxrst.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_fifo_ctrl_fmtrst.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_fifo_ctrl_acqrst.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_fifo_ctrl_txrst.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_host_fifo_config_rx_thresh.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_host_fifo_config_fmt_thresh.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_target_fifo_config_tx_thresh.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_target_fifo_config_txrst_on_cond.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_target_fifo_config_acq_thresh.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ovrd_txovrden.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ovrd_sclval.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ovrd_sdaval.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_timing0_thigh.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_timing0_tlow.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_timing1_t_r.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_timing1_t_f.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_timing2_tsu_sta.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_timing2_thd_sta.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_timing3_tsu_dat.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_timing3_thd_dat.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_timing4_tsu_sto.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_timing4_t_buf.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_timeout_ctrl_val.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_timeout_ctrl_en.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_target_id_address0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_target_id_mask0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_target_id_address1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_target_id_mask1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_txdata.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_host_timeout_ctrl.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_target_timeout_ctrl_val.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_target_timeout_ctrl_en.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_host_nack_handler_timeout_val.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_host_nack_handler_timeout_en.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1
34	1	1
39		unreachable

---

Line Coverage for Module : prim_subreg_arb ( parameter DW=8,SwAccess=6,Mubi=0 )
Line Coverage for Module self-instances :

SCORE	LINE
83.33	100.00

tb.dut.u_reg.u_target_nack_count.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	168	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
140	1	1
162	1	1
168		unreachable

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=8,SwAccess=6,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
83.33	66.67

tb.dut.u_reg.u_target_nack_count.wr_en_data_arb

	Total	Covered	Percent
Conditions	3	2	66.67
Logical	3	2	66.67
Non-Logical	0	0
Event	0	0

 LINE       140
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T74,T75,T76

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state_rx_overflow.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state_scl_interference.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state_sda_interference.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state_stretch_timeout.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state_sda_unstable.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state_cmd_complete.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state_unexp_stop.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state_host_timeout.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_controller_events_nack.wr_en_data_arb

SCORE	COND
80.00	60.00

tb.dut.u_reg.u_controller_events_unhandled_nack_timeout.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T2,T3,T6

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_fmt_threshold.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_rx_threshold.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_acq_threshold.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_rx_overflow.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_controller_halt.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_scl_interference.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_sda_interference.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_stretch_timeout.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_sda_unstable.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_cmd_complete.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_tx_stretch.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_tx_threshold.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_acq_full.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_unexp_stop.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_host_timeout.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ctrl_enablehost.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ctrl_enabletarget.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ctrl_llpbk.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fdata_start.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fdata_stop.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fdata_readb.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fdata_rcont.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fdata_nakok.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fifo_ctrl_rxrst.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fifo_ctrl_fmtrst.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fifo_ctrl_acqrst.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fifo_ctrl_txrst.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_target_fifo_config_txrst_on_cond.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ovrd_txovrden.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ovrd_sclval.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ovrd_sdaval.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_timeout_ctrl_en.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_target_timeout_ctrl_en.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_host_nack_handler_timeout_en.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=31,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_timeout_ctrl_val.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_target_timeout_ctrl_val.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_host_nack_handler_timeout_val.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=16,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_timing0_thigh.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_timing0_tlow.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_timing1_t_r.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_timing1_t_f.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_timing2_tsu_sta.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_timing2_thd_sta.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_timing3_tsu_dat.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_timing3_thd_dat.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_timing4_tsu_sto.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_timing4_t_buf.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=7,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_target_id_address0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_target_id_mask0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_target_id_address1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_target_id_mask1.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=32,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_host_timeout_ctrl.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=8,SwAccess=2,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fdata_fbyte.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_txdata.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=12,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_host_fifo_config_rx_thresh.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_host_fifo_config_fmt_thresh.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_target_fifo_config_tx_thresh.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_target_fifo_config_acq_thresh.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_subreg_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	34	((we == 1'b1)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3