Unified Coverage Report :: Module :: i2c_reg_top

Module : i2c_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.84	100.00	99.36			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	99.84	100.00	99.36			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.84	100.00	99.36			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.79	98.52	98.10	100.00		97.35	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.72	100.00	100.00	94.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_acqdata_abyte	100.00	100.00
u_acqdata_signal	100.00	100.00
u_alert_test	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_controller_events_nack	100.00	100.00	100.00			100.00
u_controller_events_unhandled_nack_timeout	88.89	100.00	66.67			100.00
u_ctrl_enablehost	100.00	100.00	100.00			100.00
u_ctrl_enabletarget	100.00	100.00	100.00			100.00
u_ctrl_llpbk	100.00	100.00	100.00			100.00
u_fdata0_qe	100.00	100.00				100.00
u_fdata_fbyte	100.00	100.00	100.00			100.00
u_fdata_nakok	100.00	100.00	100.00			100.00
u_fdata_rcont	100.00	100.00	100.00			100.00
u_fdata_readb	100.00	100.00	100.00			100.00
u_fdata_start	100.00	100.00	100.00			100.00
u_fdata_stop	100.00	100.00	100.00			100.00
u_fifo_ctrl0_qe	100.00	100.00				100.00
u_fifo_ctrl_acqrst	100.00	100.00	100.00			100.00
u_fifo_ctrl_fmtrst	100.00	100.00	100.00			100.00
u_fifo_ctrl_rxrst	100.00	100.00	100.00			100.00
u_fifo_ctrl_txrst	100.00	100.00	100.00			100.00
u_host_fifo_config0_qe	100.00	100.00				100.00
u_host_fifo_config_fmt_thresh	100.00	100.00	100.00			100.00
u_host_fifo_config_rx_thresh	100.00	100.00	100.00			100.00
u_host_fifo_status_fmtlvl	100.00	100.00
u_host_fifo_status_rxlvl	100.00	100.00
u_host_nack_handler_timeout_en	100.00	100.00	100.00			100.00
u_host_nack_handler_timeout_val	100.00	100.00	100.00			100.00
u_host_timeout_ctrl	100.00	100.00	100.00			100.00
u_intr_enable_acq_full	100.00	100.00	100.00			100.00
u_intr_enable_acq_threshold	100.00	100.00	100.00			100.00
u_intr_enable_cmd_complete	100.00	100.00	100.00			100.00
u_intr_enable_controller_halt	100.00	100.00	100.00			100.00
u_intr_enable_fmt_threshold	100.00	100.00	100.00			100.00
u_intr_enable_host_timeout	100.00	100.00	100.00			100.00
u_intr_enable_rx_overflow	100.00	100.00	100.00			100.00
u_intr_enable_rx_threshold	100.00	100.00	100.00			100.00
u_intr_enable_scl_interference	100.00	100.00	100.00			100.00
u_intr_enable_sda_interference	100.00	100.00	100.00			100.00
u_intr_enable_sda_unstable	100.00	100.00	100.00			100.00
u_intr_enable_stretch_timeout	100.00	100.00	100.00			100.00
u_intr_enable_tx_stretch	100.00	100.00	100.00			100.00
u_intr_enable_tx_threshold	100.00	100.00	100.00			100.00
u_intr_enable_unexp_stop	100.00	100.00	100.00			100.00
u_intr_state_acq_full	62.59	77.78	50.00			60.00
u_intr_state_acq_threshold	62.59	77.78	50.00			60.00
u_intr_state_cmd_complete	100.00	100.00	100.00			100.00
u_intr_state_controller_halt	62.59	77.78	50.00			60.00
u_intr_state_fmt_threshold	62.59	77.78	50.00			60.00
u_intr_state_host_timeout	100.00	100.00	100.00			100.00
u_intr_state_rx_overflow	100.00	100.00	100.00			100.00
u_intr_state_rx_threshold	62.59	77.78	50.00			60.00
u_intr_state_scl_interference	100.00	100.00	100.00			100.00
u_intr_state_sda_interference	100.00	100.00	100.00			100.00
u_intr_state_sda_unstable	100.00	100.00	100.00			100.00
u_intr_state_stretch_timeout	100.00	100.00	100.00			100.00
u_intr_state_tx_stretch	62.59	77.78	50.00			60.00
u_intr_state_tx_threshold	62.59	77.78	50.00			60.00
u_intr_state_unexp_stop	100.00	100.00	100.00			100.00
u_intr_test_acq_full	100.00	100.00
u_intr_test_acq_threshold	100.00	100.00
u_intr_test_cmd_complete	100.00	100.00
u_intr_test_controller_halt	100.00	100.00
u_intr_test_fmt_threshold	100.00	100.00
u_intr_test_host_timeout	100.00	100.00
u_intr_test_rx_overflow	100.00	100.00
u_intr_test_rx_threshold	100.00	100.00
u_intr_test_scl_interference	100.00	100.00
u_intr_test_sda_interference	100.00	100.00
u_intr_test_sda_unstable	100.00	100.00
u_intr_test_stretch_timeout	100.00	100.00
u_intr_test_tx_stretch	100.00	100.00
u_intr_test_tx_threshold	100.00	100.00
u_intr_test_unexp_stop	100.00	100.00
u_ovrd_sclval	100.00	100.00	100.00			100.00
u_ovrd_sdaval	100.00	100.00	100.00			100.00
u_ovrd_txovrden	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_rdata	100.00	100.00
u_reg_if	98.67	97.14	97.53			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_status_acqempty	100.00	100.00
u_status_acqfull	100.00	100.00
u_status_fmtempty	100.00	100.00
u_status_fmtfull	100.00	100.00
u_status_hostidle	100.00	100.00
u_status_rxempty	100.00	100.00
u_status_rxfull	100.00	100.00
u_status_targetidle	100.00	100.00
u_status_txempty	100.00	100.00
u_status_txfull	100.00	100.00
u_target_fifo_config0_qe	100.00	100.00				100.00
u_target_fifo_config_acq_thresh	100.00	100.00	100.00			100.00
u_target_fifo_config_tx_thresh	100.00	100.00	100.00			100.00
u_target_fifo_config_txrst_on_cond	100.00	100.00	100.00			100.00
u_target_fifo_status_acqlvl	100.00	100.00
u_target_fifo_status_txlvl	100.00	100.00
u_target_id_address0	100.00	100.00	100.00			100.00
u_target_id_address1	100.00	100.00	100.00			100.00
u_target_id_mask0	100.00	100.00	100.00			100.00
u_target_id_mask1	100.00	100.00	100.00			100.00
u_target_nack_count	81.90	100.00	60.00			85.71
u_target_timeout_ctrl_en	100.00	100.00	100.00			100.00
u_target_timeout_ctrl_val	100.00	100.00	100.00			100.00
u_timeout_ctrl_en	100.00	100.00	100.00			100.00
u_timeout_ctrl_val	100.00	100.00	100.00			100.00
u_timing0_thigh	100.00	100.00	100.00			100.00
u_timing0_tlow	100.00	100.00	100.00			100.00
u_timing1_t_f	100.00	100.00	100.00			100.00
u_timing1_t_r	100.00	100.00	100.00			100.00
u_timing2_thd_sta	100.00	100.00	100.00			100.00
u_timing2_tsu_sta	100.00	100.00	100.00			100.00
u_timing3_thd_dat	100.00	100.00	100.00			100.00
u_timing3_tsu_dat	100.00	100.00	100.00			100.00
u_timing4_t_buf	100.00	100.00	100.00			100.00
u_timing4_tsu_sto	100.00	100.00	100.00			100.00
u_txdata	100.00	100.00	100.00			100.00
u_txdata0_qe	100.00	100.00				100.00
u_val_scl_rx	66.67	66.67
u_val_sda_rx	66.67	66.67

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c_reg_top

	Line No.	Total	Covered	Percent
TOTAL		333	333	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	1141	1	1	100.00
CONT_ASSIGN	1156	1	1	100.00
CONT_ASSIGN	1172	1	1	100.00
CONT_ASSIGN	1188	1	1	100.00
CONT_ASSIGN	1204	1	1	100.00
CONT_ASSIGN	1220	1	1	100.00
CONT_ASSIGN	1236	1	1	100.00
CONT_ASSIGN	1252	1	1	100.00
CONT_ASSIGN	1268	1	1	100.00
CONT_ASSIGN	1284	1	1	100.00
CONT_ASSIGN	1300	1	1	100.00
CONT_ASSIGN	1316	1	1	100.00
CONT_ASSIGN	1332	1	1	100.00
CONT_ASSIGN	1348	1	1	100.00
CONT_ASSIGN	1364	1	1	100.00
CONT_ASSIGN	1380	1	1	100.00
CONT_ASSIGN	1386	1	1	100.00
CONT_ASSIGN	1400	1	1	100.00
CONT_ASSIGN	1692	1	1	100.00
CONT_ASSIGN	1720	1	1	100.00
CONT_ASSIGN	1748	1	1	100.00
CONT_ASSIGN	1776	1	1	100.00
CONT_ASSIGN	1804	1	1	100.00
CONT_ASSIGN	1832	1	1	100.00
CONT_ASSIGN	1873	1	1	100.00
CONT_ASSIGN	1901	1	1	100.00
CONT_ASSIGN	1929	1	1	100.00
CONT_ASSIGN	1957	1	1	100.00
CONT_ASSIGN	1998	1	1	100.00
CONT_ASSIGN	2026	1	1	100.00
CONT_ASSIGN	2067	1	1	100.00
CONT_ASSIGN	2095	1	1	100.00
CONT_ASSIGN	2123	1	1	100.00
CONT_ASSIGN	2820	1	1	100.00
ALWAYS	3050	30	30	100.00
CONT_ASSIGN	3082	1	1	100.00
ALWAYS	3086	1	1	100.00
CONT_ASSIGN	3119	1	1	100.00
CONT_ASSIGN	3121	1	1	100.00
CONT_ASSIGN	3123	1	1	100.00
CONT_ASSIGN	3125	1	1	100.00
CONT_ASSIGN	3127	1	1	100.00
CONT_ASSIGN	3129	1	1	100.00
CONT_ASSIGN	3131	1	1	100.00
CONT_ASSIGN	3133	1	1	100.00
CONT_ASSIGN	3135	1	1	100.00
CONT_ASSIGN	3136	1	1	100.00
CONT_ASSIGN	3138	1	1	100.00
CONT_ASSIGN	3140	1	1	100.00
CONT_ASSIGN	3142	1	1	100.00
CONT_ASSIGN	3144	1	1	100.00
CONT_ASSIGN	3146	1	1	100.00
CONT_ASSIGN	3148	1	1	100.00
CONT_ASSIGN	3150	1	1	100.00
CONT_ASSIGN	3152	1	1	100.00
CONT_ASSIGN	3154	1	1	100.00
CONT_ASSIGN	3156	1	1	100.00
CONT_ASSIGN	3158	1	1	100.00
CONT_ASSIGN	3160	1	1	100.00
CONT_ASSIGN	3162	1	1	100.00
CONT_ASSIGN	3164	1	1	100.00
CONT_ASSIGN	3166	1	1	100.00
CONT_ASSIGN	3167	1	1	100.00
CONT_ASSIGN	3169	1	1	100.00
CONT_ASSIGN	3171	1	1	100.00
CONT_ASSIGN	3173	1	1	100.00
CONT_ASSIGN	3175	1	1	100.00
CONT_ASSIGN	3177	1	1	100.00
CONT_ASSIGN	3179	1	1	100.00
CONT_ASSIGN	3181	1	1	100.00
CONT_ASSIGN	3183	1	1	100.00
CONT_ASSIGN	3185	1	1	100.00
CONT_ASSIGN	3187	1	1	100.00
CONT_ASSIGN	3189	1	1	100.00
CONT_ASSIGN	3191	1	1	100.00
CONT_ASSIGN	3193	1	1	100.00
CONT_ASSIGN	3195	1	1	100.00
CONT_ASSIGN	3197	1	1	100.00
CONT_ASSIGN	3198	1	1	100.00
CONT_ASSIGN	3200	1	1	100.00
CONT_ASSIGN	3201	1	1	100.00
CONT_ASSIGN	3203	1	1	100.00
CONT_ASSIGN	3205	1	1	100.00
CONT_ASSIGN	3207	1	1	100.00
CONT_ASSIGN	3208	1	1	100.00
CONT_ASSIGN	3209	1	1	100.00
CONT_ASSIGN	3210	1	1	100.00
CONT_ASSIGN	3212	1	1	100.00
CONT_ASSIGN	3214	1	1	100.00
CONT_ASSIGN	3216	1	1	100.00
CONT_ASSIGN	3218	1	1	100.00
CONT_ASSIGN	3220	1	1	100.00
CONT_ASSIGN	3222	1	1	100.00
CONT_ASSIGN	3223	1	1	100.00
CONT_ASSIGN	3225	1	1	100.00
CONT_ASSIGN	3227	1	1	100.00
CONT_ASSIGN	3229	1	1	100.00
CONT_ASSIGN	3231	1	1	100.00
CONT_ASSIGN	3232	1	1	100.00
CONT_ASSIGN	3234	1	1	100.00
CONT_ASSIGN	3236	1	1	100.00
CONT_ASSIGN	3237	1	1	100.00
CONT_ASSIGN	3239	1	1	100.00
CONT_ASSIGN	3241	1	1	100.00
CONT_ASSIGN	3243	1	1	100.00
CONT_ASSIGN	3244	1	1	100.00
CONT_ASSIGN	3245	1	1	100.00
CONT_ASSIGN	3246	1	1	100.00
CONT_ASSIGN	3248	1	1	100.00
CONT_ASSIGN	3250	1	1	100.00
CONT_ASSIGN	3252	1	1	100.00
CONT_ASSIGN	3253	1	1	100.00
CONT_ASSIGN	3254	1	1	100.00
CONT_ASSIGN	3256	1	1	100.00
CONT_ASSIGN	3258	1	1	100.00
CONT_ASSIGN	3259	1	1	100.00
CONT_ASSIGN	3261	1	1	100.00
CONT_ASSIGN	3263	1	1	100.00
CONT_ASSIGN	3264	1	1	100.00
CONT_ASSIGN	3266	1	1	100.00
CONT_ASSIGN	3268	1	1	100.00
CONT_ASSIGN	3269	1	1	100.00
CONT_ASSIGN	3271	1	1	100.00
CONT_ASSIGN	3273	1	1	100.00
CONT_ASSIGN	3274	1	1	100.00
CONT_ASSIGN	3276	1	1	100.00
CONT_ASSIGN	3278	1	1	100.00
CONT_ASSIGN	3279	1	1	100.00
CONT_ASSIGN	3281	1	1	100.00
CONT_ASSIGN	3283	1	1	100.00
CONT_ASSIGN	3284	1	1	100.00
CONT_ASSIGN	3286	1	1	100.00
CONT_ASSIGN	3288	1	1	100.00
CONT_ASSIGN	3290	1	1	100.00
CONT_ASSIGN	3292	1	1	100.00
CONT_ASSIGN	3293	1	1	100.00
CONT_ASSIGN	3294	1	1	100.00
CONT_ASSIGN	3296	1	1	100.00
CONT_ASSIGN	3297	1	1	100.00
CONT_ASSIGN	3299	1	1	100.00
CONT_ASSIGN	3300	1	1	100.00
CONT_ASSIGN	3302	1	1	100.00
CONT_ASSIGN	3304	1	1	100.00
CONT_ASSIGN	3305	1	1	100.00
CONT_ASSIGN	3308	1	1	100.00
CONT_ASSIGN	3310	1	1	100.00
CONT_ASSIGN	3312	1	1	100.00
CONT_ASSIGN	3313	1	1	100.00
CONT_ASSIGN	3315	1	1	100.00
CONT_ASSIGN	3317	1	1	100.00
ALWAYS	3321	30	30	100.00
ALWAYS	3355	113	113	100.00
CONT_ASSIGN	3566	0	0
CONT_ASSIGN	3574	1	1	100.00
CONT_ASSIGN	3575	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
77	1	1
89	1	1
90	1	1
118	1	1
119	1	1
1141	1	1
1156	1	1
1172	1	1
1188	1	1
1204	1	1
1220	1	1
1236	1	1
1252	1	1
1268	1	1
1284	1	1
1300	1	1
1316	1	1
1332	1	1
1348	1	1
1364	1	1
1380	1	1
1386	1	1
1400	1	1
1692	1	1
1720	1	1
1748	1	1
1776	1	1
1804	1	1
1832	1	1
1873	1	1
1901	1	1
1929	1	1
1957	1	1
1998	1	1
2026	1	1
2067	1	1
2095	1	1
2123	1	1
2820	1	1
3050	1	1
3051	1	1
3052	1	1
3053	1	1
3054	1	1
3055	1	1
3056	1	1
3057	1	1
3058	1	1
3059	1	1
3060	1	1
3061	1	1
3062	1	1
3063	1	1
3064	1	1
3065	1	1
3066	1	1
3067	1	1
3068	1	1
3069	1	1
3070	1	1
3071	1	1
3072	1	1
3073	1	1
3074	1	1
3075	1	1
3076	1	1
3077	1	1
3078	1	1
3079	1	1
3082	1	1
3086	1	1
3119	1	1
3121	1	1
3123	1	1
3125	1	1
3127	1	1
3129	1	1
3131	1	1
3133	1	1
3135	1	1
3136	1	1
3138	1	1
3140	1	1
3142	1	1
3144	1	1
3146	1	1
3148	1	1
3150	1	1
3152	1	1
3154	1	1
3156	1	1
3158	1	1
3160	1	1
3162	1	1
3164	1	1
3166	1	1
3167	1	1
3169	1	1
3171	1	1
3173	1	1
3175	1	1
3177	1	1
3179	1	1
3181	1	1
3183	1	1
3185	1	1
3187	1	1
3189	1	1
3191	1	1
3193	1	1
3195	1	1
3197	1	1
3198	1	1
3200	1	1
3201	1	1
3203	1	1
3205	1	1
3207	1	1
3208	1	1
3209	1	1
3210	1	1
3212	1	1
3214	1	1
3216	1	1
3218	1	1
3220	1	1
3222	1	1
3223	1	1
3225	1	1
3227	1	1
3229	1	1
3231	1	1
3232	1	1
3234	1	1
3236	1	1
3237	1	1
3239	1	1
3241	1	1
3243	1	1
3244	1	1
3245	1	1
3246	1	1
3248	1	1
3250	1	1
3252	1	1
3253	1	1
3254	1	1
3256	1	1
3258	1	1
3259	1	1
3261	1	1
3263	1	1
3264	1	1
3266	1	1
3268	1	1
3269	1	1
3271	1	1
3273	1	1
3274	1	1
3276	1	1
3278	1	1
3279	1	1
3281	1	1
3283	1	1
3284	1	1
3286	1	1
3288	1	1
3290	1	1
3292	1	1
3293	1	1
3294	1	1
3296	1	1
3297	1	1
3299	1	1
3300	1	1
3302	1	1
3304	1	1
3305	1	1
3308	1	1
3310	1	1
3312	1	1
3313	1	1
3315	1	1
3317	1	1
3321	1	1
3322	1	1
3323	1	1
3324	1	1
3325	1	1
3326	1	1
3327	1	1
3328	1	1
3329	1	1
3330	1	1
3331	1	1
3332	1	1
3333	1	1
3334	1	1
3335	1	1
3336	1	1
3337	1	1
3338	1	1
3339	1	1
3340	1	1
3341	1	1
3342	1	1
3343	1	1
3344	1	1
3345	1	1
3346	1	1
3347	1	1
3348	1	1
3349	1	1
3350	1	1
3355	1	1
3356	1	1
3358	1	1
3359	1	1
3360	1	1
3361	1	1
3362	1	1
3363	1	1
3364	1	1
3365	1	1
3366	1	1
3367	1	1
3368	1	1
3369	1	1
3370	1	1
3371	1	1
3372	1	1
3376	1	1
3377	1	1
3378	1	1
3379	1	1
3380	1	1
3381	1	1
3382	1	1
3383	1	1
3384	1	1
3385	1	1
3386	1	1
3387	1	1
3388	1	1
3389	1	1
3390	1	1
3394	1	1
3395	1	1
3396	1	1
3397	1	1
3398	1	1
3399	1	1
3400	1	1
3401	1	1
3402	1	1
3403	1	1
3404	1	1
3405	1	1
3406	1	1
3407	1	1
3408	1	1
3412	1	1
3416	1	1
3417	1	1
3418	1	1
3422	1	1
3423	1	1
3424	1	1
3425	1	1
3426	1	1
3427	1	1
3428	1	1
3429	1	1
3430	1	1
3431	1	1
3435	1	1
3439	1	1
3440	1	1
3441	1	1
3442	1	1
3443	1	1
3444	1	1
3448	1	1
3449	1	1
3450	1	1
3451	1	1
3455	1	1
3456	1	1
3460	1	1
3461	1	1
3462	1	1
3466	1	1
3467	1	1
3471	1	1
3472	1	1
3476	1	1
3477	1	1
3478	1	1
3482	1	1
3483	1	1
3487	1	1
3488	1	1
3492	1	1
3493	1	1
3497	1	1
3498	1	1
3502	1	1
3503	1	1
3507	1	1
3508	1	1
3512	1	1
3513	1	1
3517	1	1
3518	1	1
3519	1	1
3520	1	1
3524	1	1
3525	1	1
3529	1	1
3533	1	1
3537	1	1
3538	1	1
3542	1	1
3546	1	1
3547	1	1
3551	1	1
3552	1	1
3566		unreachable
3574	1	1
3575	1	1

---

Cond Coverage for Module : i2c_reg_top

	Total	Covered	Percent
Conditions	313	311	99.36
Logical	313	311	99.36
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T106,T125,T126
1	1	Covered	T1,T2,T3

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T109,T110,T111
1	0	Covered	T107,T108,T124

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T109,T110,T111
0	1	0	Covered	T107,T108,T124
1	0	0	Covered	T109,T110,T111

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T107,T108,T124
0	1	0	Covered	T106,T122,T123
1	0	0	Covered	T106,T122,T125

 LINE       3051
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_INTR_STATE_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3052
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_INTR_ENABLE_OFFSET)
            ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3053
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_INTR_TEST_OFFSET)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3054
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_ALERT_TEST_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3055
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_CTRL_OFFSET)
            ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3056
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_STATUS_OFFSET)
            ----------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3057
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_RDATA_OFFSET)
            ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3058
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_FDATA_OFFSET)
            ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3059
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_FIFO_CTRL_OFFSET)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3060
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_HOST_FIFO_CONFIG_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3061
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_FIFO_CONFIG_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3062
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_HOST_FIFO_STATUS_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3063
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_FIFO_STATUS_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3064
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_OVRD_OFFSET)
            ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3065
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_VAL_OFFSET)
            --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3066
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING0_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3067
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING1_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3068
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING2_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3069
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING3_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3070
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING4_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3071
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMEOUT_CTRL_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3072
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_ID_OFFSET)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3073
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_ACQDATA_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3074
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TXDATA_OFFSET)
            ----------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3075
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_HOST_TIMEOUT_CTRL_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3076
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_TIMEOUT_CTRL_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3077
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_NACK_COUNT_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3078
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_HOST_NACK_HANDLER_TIMEOUT_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3079
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_CONTROLLER_EVENTS_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3082
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3082
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       3086
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[2] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[8] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T106,T108,T122

 LINE       3086
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b0011 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b0011 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b0011 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b0011 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b1 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T1,T2,T3
29 (addr_hit[28] & ((|(4'...	Covered	T1,T2,T4
28 (addr_hit[27] & ((|(4'...	Covered	T1,T2,T4
27 (addr_hit[26] & ((|(4'...	Covered	T1,T2,T4
26 (addr_hit[25] & ((|(4'...	Covered	T1,T2,T4
25 (addr_hit[24] & ((|(4'...	Covered	T1,T2,T4
24 (addr_hit[23] & ((|(4'...	Covered	T1,T2,T4
23 (addr_hit[22] & ((|(4'...	Covered	T1,T2,T4
22 (addr_hit[21] & ((|(4'...	Covered	T1,T2,T4
21 (addr_hit[20] & ((|(4'...	Covered	T1,T2,T4
20 (addr_hit[19] & ((|(4'...	Covered	T1,T2,T4
19 (addr_hit[18] & ((|(4'...	Covered	T1,T2,T4
18 (addr_hit[17] & ((|(4'...	Covered	T1,T2,T4
17 (addr_hit[16] & ((|(4'...	Covered	T1,T2,T4
16 (addr_hit[15] & ((|(4'...	Covered	T1,T2,T4
15 (addr_hit[14] & ((|(4'...	Covered	T1,T2,T4
14 (addr_hit[13] & ((|(4'...	Covered	T1,T2,T4
13 (addr_hit[12] & ((|(4'...	Covered	T1,T2,T4
12 (addr_hit[11] & ((|(4'...	Covered	T1,T2,T4
11 (addr_hit[10] & ((|(4'...	Covered	T1,T2,T4
10 (addr_hit[9] & ((|(4'b...	Covered	T1,T2,T4
9 (addr_hit[8] & ((|(4'b...	Covered	T1,T2,T4
8 (addr_hit[7] & ((|(4'b...	Covered	T1,T2,T4
7 (addr_hit[6] & ((|(4'b...	Covered	T1,T2,T3
6 (addr_hit[5] & ((|(4'b...	Covered	T1,T2,T3
5 (addr_hit[4] & ((|(4'b...	Covered	T1,T2,T4
4 (addr_hit[3] & ((|(4'b...	Covered	T1,T2,T4
3 (addr_hit[2] & ((|(4'b...	Covered	T1,T2,T4
2 (addr_hit[1] & ((|(4'b...	Covered	T1,T2,T4
1 (addr_hit[0] & ((|(4'b...	Covered	T1,T2,T3

 LINE       3086
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       3086
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       3086
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       3086
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       3086
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       3086
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       3086
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       3086
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       3086
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       3086
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       3086
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       3086
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T4

 LINE       3086
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       3086
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       3086
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       3086
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       3086
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       3086
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       3086
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       3086
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       3086
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       3086
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       3086
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       3086
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       3086
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       3086
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       3086
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       3086
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       3086
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       3119
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T106,T122,T127
1	1	1	Covered	T1,T2,T3

 LINE       3136
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T106,T125,T128
1	1	1	Covered	T1,T2,T3

 LINE       3167
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T126,T128,T129
1	1	1	Covered	T6,T44,T77

 LINE       3198
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T106,T130,T128
1	1	1	Covered	T102,T103,T104

 LINE       3201
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T126,T129,T131
1	1	1	Covered	T1,T2,T3

 LINE       3208
 EXPRESSION (addr_hit[5] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T132,T133,T134
1	1	1	Covered	T1,T2,T3

 LINE       3209
 EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T107,T124,T135
1	1	1	Covered	T3,T6,T8

 LINE       3210
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T106,T125,T126
1	1	1	Covered	T2,T3,T6

 LINE       3223
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T122,T125,T126
1	1	1	Covered	T1,T2,T3

 LINE       3232
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T106,T122,T125
1	1	1	Covered	T1,T2,T3

 LINE       3237
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T106,T126,T130
1	1	1	Covered	T1,T2,T3

 LINE       3244
 EXPRESSION (addr_hit[11] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T107,T127,T133
1	1	1	Covered	T44,T68,T45

 LINE       3245
 EXPRESSION (addr_hit[12] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T5

 LINE       3246
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T122,T124,T125
1	1	1	Covered	T38,T39,T40

 LINE       3253
 EXPRESSION (addr_hit[14] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T108,T136,T137
1	1	1	Not Covered

 LINE       3254
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T122,T126,T129
1	1	1	Covered	T1,T2,T3

 LINE       3259
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T106,T108,T125
1	1	1	Covered	T1,T2,T3

 LINE       3264
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T122,T126,T129
1	1	1	Covered	T1,T2,T3

 LINE       3269
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T106,T125,T126
1	1	1	Covered	T1,T2,T3

 LINE       3274
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T106,T122,T124
1	1	1	Covered	T1,T2,T3

 LINE       3279
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T107,T124,T128
1	1	1	Covered	T1,T2,T3

 LINE       3284
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T106,T125,T128
1	1	1	Covered	T1,T4,T5

 LINE       3293
 EXPRESSION (addr_hit[22] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T138,T139
1	1	1	Covered	T1,T4,T5

 LINE       3294
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T122,T126,T130
1	1	1	Covered	T1,T4,T5

 LINE       3297
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T106,T108,T122
1	1	1	Covered	T1,T4,T5

 LINE       3300
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T106,T125,T126
1	1	1	Covered	T74,T75,T76

 LINE       3305
 EXPRESSION (addr_hit[26] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T135,T140,T139
1	1	1	Covered	T74,T75,T76

 LINE       3308
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T106,T123,T125
1	1	1	Covered	T3,T65,T66

 LINE       3313
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T106,T122,T125
1	1	1	Covered	T3,T5,T6

---

Branch Coverage for Module : i2c_reg_top

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	3082	2	2	100.00
IF	68	3	3	100.00
CASE	3356	30	30	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	3082	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	68	if ((!rst_ni))
-2-:	70	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T109,T110,T111
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	3356	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : i2c_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	444758471	63211546	0	0
reAfterRv	444758471	63211304	0	0
rePulse	444758471	62227974	0	0
wePulse	444758471	983330	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	444758471	63211546	0	0
T1	89582	1223	0	0
T2	22527	2309	0	0
T3	46854	22879	0	0
T4	140733	1633	0	0
T5	988588	9023	0	0
T6	147805	212490	0	0
T7	89517	9760	0	0
T8	123844	60879	0	0
T9	231932	107745	0	0
T10	28920	2555	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	444758471	63211304	0	0
T1	89582	1223	0	0
T2	22527	2309	0	0
T3	46854	22879	0	0
T4	140733	1633	0	0
T5	988588	9023	0	0
T6	147805	212488	0	0
T7	89517	9760	0	0
T8	123844	60879	0	0
T9	231932	107745	0	0
T10	28920	2555	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	444758471	62227974	0	0
T1	89582	885	0	0
T2	22527	2117	0	0
T3	46854	22594	0	0
T4	140733	996	0	0
T5	988588	5392	0	0
T6	147805	207250	0	0
T7	89517	9433	0	0
T8	123844	60064	0	0
T9	231932	106663	0	0
T10	28920	2281	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	444758471	983330	0	0
T1	89582	338	0	0
T2	22527	192	0	0
T3	46854	285	0	0
T4	140733	637	0	0
T5	988588	3631	0	0
T6	147805	5238	0	0
T7	89517	327	0	0
T8	123844	815	0	0
T9	231932	1082	0	0
T10	28920	274	0	0