Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.72	100.00	100.00	94.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	444758471	8012	0	0
ctrl_rd_A	444758471	1536	0	0
host_fifo_config_rd_A	444758471	5576	0	0
host_nack_handler_timeout_rd_A	444758471	1359	0	0
host_timeout_ctrl_rd_A	444758471	1135	0	0
intr_enable_rd_A	444758471	4905	0	0
ovrd_rd_A	444758471	2242	0	0
target_fifo_config_rd_A	444758471	1662	0	0
target_id_rd_A	444758471	1684	0	0
target_timeout_ctrl_rd_A	444758471	1415	0	0
timeout_ctrl_rd_A	444758471	1334	0	0
timing0_rd_A	444758471	1449	0	0
timing1_rd_A	444758471	1338	0	0
timing2_rd_A	444758471	1309	0	0
timing3_rd_A	444758471	1315	0	0
timing4_rd_A	444758471	1415	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444758471	8012	0	0
T106	2920	358	0	0
T107	6576	1	0	0
T108	4447	1	0	0
T122	1688	47	0	0
T123	3487	8	0	0
T124	12445	1	0	0
T125	12764	782	0	0
T126	3993	652	0	0
T127	7452	4	0	0
T142	3157	17	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444758471	1536	0	0
T123	3487	9	0	0
T125	12764	30	0	0
T127	7452	35	0	0
T142	3157	17	0	0
T143	2896	16	0	0
T159	3373	38	0	0
T166	3665	5	0	0
T167	3284	19	0	0
T168	25112	129	0	0
T169	2460	22	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444758471	5576	0	0
T19	299809	0	0	0
T23	37786	0	0	0
T36	97583	0	0	0
T43	133170	0	0	0
T44	132278	201	0	0
T63	128430	0	0	0
T68	12239	0	0	0
T73	0	135	0	0
T80	48035	0	0	0
T83	18807	0	0	0
T84	15447	0	0	0
T121	0	172	0	0
T170	0	140	0	0
T171	0	116	0	0
T172	0	155	0	0
T173	0	149	0	0
T174	0	183	0	0
T175	0	147	0	0
T176	0	427	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444758471	1359	0	0
T123	3487	9	0	0
T125	12764	25	0	0
T127	7452	21	0	0
T128	5942	5	0	0
T142	3157	10	0	0
T143	2896	16	0	0
T159	3373	20	0	0
T166	3665	32	0	0
T167	3284	9	0	0
T168	25112	149	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444758471	1135	0	0
T123	3487	19	0	0
T125	12764	7	0	0
T127	7452	32	0	0
T128	5942	12	0	0
T142	3157	14	0	0
T143	2896	9	0	0
T159	3373	45	0	0
T166	3665	3	0	0
T167	3284	15	0	0
T168	25112	148	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444758471	4905	0	0
T19	299809	0	0	0
T23	37786	0	0	0
T36	97583	0	0	0
T43	133170	0	0	0
T44	132278	25	0	0
T63	128430	0	0	0
T68	12239	0	0	0
T73	0	11	0	0
T80	48035	0	0	0
T83	18807	0	0	0
T84	15447	0	0	0
T121	0	6	0	0
T159	0	24	0	0
T176	0	14	0	0
T177	0	61	0	0
T178	0	8	0	0
T179	0	47	0	0
T180	0	11	0	0
T181	0	7	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444758471	2242	0	0
T47	148123	0	0	0
T79	177249	0	0	0
T115	0	31	0	0
T182	2802	53	0	0
T183	0	53	0	0
T184	0	40	0	0
T185	0	72	0	0
T186	0	67	0	0
T187	0	15	0	0
T188	0	82	0	0
T189	0	48	0	0
T190	0	44	0	0
T191	34765	0	0	0
T192	33366	0	0	0
T193	11147	0	0	0
T194	243660	0	0	0
T195	22605	0	0	0
T196	45629	0	0	0
T197	143521	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444758471	1662	0	0
T123	3487	18	0	0
T125	12764	20	0	0
T127	7452	46	0	0
T128	5942	19	0	0
T142	3157	19	0	0
T143	2896	28	0	0
T159	3373	24	0	0
T166	3665	11	0	0
T168	25112	130	0	0
T169	2460	18	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444758471	1684	0	0
T123	3487	27	0	0
T125	12764	23	0	0
T127	7452	50	0	0
T142	3157	9	0	0
T143	2896	17	0	0
T166	3665	9	0	0
T167	3284	22	0	0
T168	25112	151	0	0
T169	2460	24	0	0
T198	14790	198	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444758471	1415	0	0
T123	3487	9	0	0
T125	12764	16	0	0
T127	7452	42	0	0
T128	5942	3	0	0
T142	3157	22	0	0
T143	2896	13	0	0
T159	3373	31	0	0
T166	3665	14	0	0
T167	3284	12	0	0
T168	25112	130	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444758471	1334	0	0
T123	3487	5	0	0
T125	12764	18	0	0
T127	7452	27	0	0
T128	5942	18	0	0
T142	3157	7	0	0
T143	2896	12	0	0
T159	3373	4	0	0
T166	3665	20	0	0
T167	3284	2	0	0
T168	25112	146	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444758471	1449	0	0
T123	3487	10	0	0
T125	12764	12	0	0
T127	7452	38	0	0
T128	5942	9	0	0
T142	3157	15	0	0
T143	2896	12	0	0
T159	3373	57	0	0
T167	3284	19	0	0
T168	25112	123	0	0
T169	2460	17	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444758471	1338	0	0
T123	3487	14	0	0
T125	12764	27	0	0
T127	7452	25	0	0
T128	5942	3	0	0
T142	3157	21	0	0
T143	2896	7	0	0
T159	3373	19	0	0
T166	3665	1	0	0
T167	3284	19	0	0
T168	25112	144	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444758471	1309	0	0
T123	3487	10	0	0
T125	12764	7	0	0
T127	7452	18	0	0
T142	3157	4	0	0
T143	2896	14	0	0
T159	3373	9	0	0
T166	3665	15	0	0
T167	3284	9	0	0
T168	25112	143	0	0
T169	2460	10	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444758471	1315	0	0
T123	3487	2	0	0
T125	12764	14	0	0
T127	7452	31	0	0
T128	5942	18	0	0
T142	3157	17	0	0
T143	2896	16	0	0
T166	3665	2	0	0
T167	3284	35	0	0
T168	25112	92	0	0
T169	2460	14	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444758471	1415	0	0
T123	3487	19	0	0
T125	12764	6	0	0
T127	7452	41	0	0
T128	5942	23	0	0
T142	3157	22	0	0
T143	2896	14	0	0
T159	3373	17	0	0
T166	3665	8	0	0
T167	3284	4	0	0
T168	25112	153	0	0