Unified Coverage Report :: Module :: i2c_target_fsm

Module : i2c_target_fsm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.14	94.15	84.00		89.02	83.54	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core.u_i2c_target_fsm	90.14	94.15	84.00		89.02	83.54	100.00

---

Module Instance : tb.dut.i2c_core.u_i2c_target_fsm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.14	94.15	84.00		89.02	83.54	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.14	94.15	84.00		89.02	83.54	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.44	97.17	72.94			91.67	100.00	i2c_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c_target_fsm

	Line No.	Total	Covered	Percent
TOTAL		325	306	94.15
ALWAYS	118	8	7	87.50
ALWAYS	132	3	3	100.00
ALWAYS	145	7	7	100.00
ALWAYS	160	5	5	100.00
ALWAYS	171	3	3	100.00
ALWAYS	180	5	5	100.00
ALWAYS	191	7	7	100.00
ALWAYS	215	6	6	100.00
ALWAYS	225	6	6	100.00
ALWAYS	235	6	6	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
ALWAYS	257	9	9	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
ALWAYS	278	7	7	100.00
ALWAYS	289	5	5	100.00
CONT_ASSIGN	306	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	310	1	1	100.00
ALWAYS	341	4	4	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	362	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
ALWAYS	369	111	101	90.99
CONT_ASSIGN	630	1	1	100.00
CONT_ASSIGN	631	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
CONT_ASSIGN	644	1	1	100.00
CONT_ASSIGN	649	1	1	100.00
ALWAYS	653	103	95	92.23
CONT_ASSIGN	938	1	1	100.00
ALWAYS	942	3	3	100.00
ALWAYS	951	3	3	100.00
CONT_ASSIGN	958	1	1	100.00
CONT_ASSIGN	959	1	1	100.00
CONT_ASSIGN	962	1	1	100.00
CONT_ASSIGN	965	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
118	1	1
119	1	1
120	1	1
121	1	1
122	1	1
123	0	1
126	1	1
127	1	1
			MISSING_ELSE
132	1	1
133	1	1
135	1	1
145	1	1
146	1	1
147	1	1
149	1	1
150	1	1
151	1	1
153	1	1
160	1	1
161	1	1
162	1	1
163	1	1
165	1	1
171	1	1
172	1	1
174	1	1
180	1	1
181	1	1
182	1	1
184	1	1
185	1	1
191	1	1
192	1	1
193	1	1
194	1	1
196	1	1
197	1	1
198	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
230	1	1
			MISSING_ELSE
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
240	1	1
			MISSING_ELSE
245	1	1
246	1	1
249	1	1
250	1	1
253	1	1
257	1	1
258	1	1
259	1	1
260	1	1
261	1	1
264	2	2
265	1	1
267	1	1
272	1	1
273	1	1
274	1	1
278	1	1
279	1	1
280	1	1
281	1	1
282	1	1
283	2	2
			MISSING_ELSE
			MISSING_ELSE
289	1	1
290	1	1
291	1	1
292	2	2
			MISSING_ELSE
			MISSING_ELSE
306	1	1
309	1	1
310	1	1
341	1	1
342	1	1
343	1	1
344	1	1
			MISSING_ELSE
358	1	1
362	1	1
365	1	1
369	1	1
370	1	1
371	1	1
372	1	1
373	1	1
374	1	1
375	1	1
376	1	1
377	1	1
378	1	1
379	1	1
380	1	1
381	1	1
382	1	1
384	1	1
389	1	1
390	1	1
391	1	1
392	1	1
393	1	1
394	1	1
403	1	1
404	1	1
408	1	1
409	1	1
411	1	1
412	1	1
413	1	1
414	1	1
			MISSING_ELSE
			MISSING_ELSE
420	1	1
422	1	1
425	0	1
			MISSING_ELSE
430	1	1
431	1	1
435	1	1
436	1	1
440	1	1
441	1	1
444	1	1
445	1	1
449	1	1
451	1	1
			MISSING_ELSE
454	1	1
455	1	1
457	1	1
			==> MISSING_ELSE
463	1	1
467	1	1
468	1	1
472	1	1
475	1	1
479	1	1
482	1	1
486	1	1
489	1	1
490	1	1
492	1	1
			MISSING_ELSE
497	1	1
498	1	1
499	1	1
503	1	1
507	1	1
508	1	1
511	0	1
			MISSING_ELSE
516	1	1
517	1	1
521	1	1
522	1	1
526	1	1
527	1	1
529	1	1
530	1	1
531	1	1
			==> MISSING_ELSE
537	1	1
538	1	1
539	1	1
541	1	1
542	0	1
546	0	1
547	0	1
548	1	1
549	1	1
550	1	1
551	1	1
553	1	1
			MISSING_ELSE
559	1	1
560	1	1
561	1	1
563	1	1
567	0	1
			MISSING_ELSE
572	1	1
573	1	1
574	1	1
578	1	1
579	1	1
580	1	1
582	1	1
583	0	1
584	0	1
585	0	1
			MISSING_ELSE
591	1	1
592	1	1
593	1	1
612	1	1
613	1	1
618	1	1
619	1	1
620	0	1
622	1	1
624	1	1
625	1	1
626	1	1
			MISSING_ELSE
630	1	1
631	1	1
635	1	1
644	1	1
649	1	1
653	1	1
654	1	1
655	1	1
656	1	1
657	1	1
659	1	1
671	1	1
672	1	1
673	1	1
			MISSING_ELSE
680	1	1
681	1	1
682	1	1
684	1	1
685	1	1
688	1	1
			MISSING_ELSE
694	1	1
696	0	1
697	1	1
699	1	1
			==> MISSING_ELSE
704	2	2
			MISSING_ELSE
708	1	1
709	1	1
710	1	1
711	1	1
			MISSING_ELSE
716	1	1
722	1	1
728	0	1
729	1	1
732	1	1
733	1	1
735	1	1
738	1	1
			==> MISSING_ELSE
744	1	1
745	1	1
747	1	1
752	2	2
			MISSING_ELSE
756	1	1
757	1	1
758	1	1
759	1	1
			MISSING_ELSE
764	1	1
765	1	1
766	1	1
768	1	1
769	1	1
770	1	1
			==> MISSING_ELSE
776	1	1
777	1	1
			MISSING_ELSE
783	1	1
785	1	1
786	1	1
789	1	1
			MISSING_ELSE
797	1	1
801	1	1
802	1	1
803	1	1
804	1	1
			MISSING_ELSE
809	1	1
811	0	1
812	1	1
813	1	1
814	0	1
815	1	1
818	1	1
820	1	1
			==> MISSING_ELSE
826	2	2
			MISSING_ELSE
830	1	1
831	1	1
832	1	1
833	1	1
			MISSING_ELSE
838	1	1
839	1	1
			==> MISSING_ELSE
847	1	1
848	0	1
849	1	1
855	1	1
			MISSING_ELSE
861	1	1
862	1	1
863	0	1
864	1	1
871	1	1
872	1	1
873	1	1
876	1	1
			MISSING_ELSE
881	1	1
882	1	1
			MISSING_ELSE
890	1	1
891	0	1
892	1	1
893	1	1
894	1	1
895	1	1
			MISSING_ELSE
901	1	1
902	1	1
			MISSING_ELSE
918	1	1
927	0	1
928	1	1
929	1	1
930	1	1
931	1	1
			MISSING_ELSE
938	1	1
942	1	1
943	1	1
945	1	1
951	1	1
952	1	1
954	1	1
958	1	1
959	1	1
962	1	1
965	1	1

---

Cond Coverage for Module : i2c_target_fsm

	Total	Covered	Percent
Conditions	125	105	84.00
Logical	125	105	84.00
Non-Logical	0	0
Event	0	0

 LINE       147
 EXPRESSION (((!target_idle_o)) && event_host_timeout_o)
             ---------1--------    ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T4,T11,T12

 LINE       150
 EXPRESSION (((!target_idle_o)) && scl_i)
             ---------1--------    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       217
 EXPRESSION (start_det_trigger || stop_det_trigger)
             --------1--------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5

 LINE       219
 EXPRESSION (start_det_pending || stop_det_pending)
             --------1--------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5

 LINE       229
 EXPRESSION (((!target_enable_i)) || ((!scl_i)) || start_det || stop_det_trigger)
             ----------1---------    -----2----    ----3----    --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T4,T5
0	0	0	1	Covered	T1,T4,T5
0	0	1	0	Covered	T1,T4,T5
0	1	0	0	Covered	T1,T4,T5
1	0	0	0	Covered	T1,T2,T3

 LINE       239
 EXPRESSION (((!target_enable_i)) || ((!scl_i)) || stop_det || start_det_trigger)
             ----------1---------    -----2----    ----3---    --------4--------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T4,T5
0	0	0	1	Covered	T1,T4,T5
0	0	1	0	Covered	T1,T4,T5
0	1	0	0	Covered	T1,T4,T5
1	0	0	0	Covered	T1,T2,T3

 LINE       245
 EXPRESSION (target_enable_i && ((scl_i_q && scl_i) & (sda_i_q && ((!sda_i)))))
             -------1-------    -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       245
 SUB-EXPRESSION ((scl_i_q && scl_i) & (sda_i_q && ((!sda_i))))
                 ---------1--------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       245
 SUB-EXPRESSION (scl_i_q && scl_i)
                 ---1---    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       245
 SUB-EXPRESSION (sda_i_q && ((!sda_i)))
                 ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       246
 EXPRESSION (target_enable_i && start_det_pending && (ctrl_det_count >= thd_dat_i))
             -------1-------    --------2--------    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T5

 LINE       249
 EXPRESSION (target_enable_i && ((scl_i_q && scl_i) & (((!sda_i_q)) && sda_i)))
             -------1-------    -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       249
 SUB-EXPRESSION ((scl_i_q && scl_i) & (((!sda_i_q)) && sda_i))
                 ---------1--------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       249
 SUB-EXPRESSION (scl_i_q && scl_i)
                 ---1---    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       249
 SUB-EXPRESSION (((!sda_i_q)) && sda_i)
                 ------1-----    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       250
 EXPRESSION (target_enable_i && stop_det_pending && (ctrl_det_count >= thd_dat_i))
             -------1-------    --------2-------    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T5

 LINE       253
 EXPRESSION (bit_idx == 4'd8)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       261
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       264
 EXPRESSION (input_byte_clr || bit_ack)
             -------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5

 LINE       272
 EXPRESSION ((input_byte[7:1] & target_mask0_i) == target_address0_i)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       273
 EXPRESSION ((input_byte[7:1] & target_mask1_i) == target_address1_i)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       274
 EXPRESSION (address0_match || address1_match)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5

 LINE       282
 EXPRESSION (((!scl_i_q)) && scl_i)
             ------1-----    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       291
 EXPRESSION (((!scl_i_q)) && scl_i)
             ------1-----    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       343
 EXPRESSION (bit_ack && address_match)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T3

 LINE       362
 EXPRESSION (xfer_for_us_q & rw_bit_q & stop_det & ((!expect_stop)))
             ------1------   ----2---   ----3---   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T13,T14,T15
1	0	1	1	Covered	T1,T4,T5
1	1	0	1	Covered	T1,T4,T5
1	1	1	0	Covered	T1,T4,T5
1	1	1	1	Covered	T16,T17,T18

 LINE       365
 EXPRESSION (((!nack_transaction_q)) && nack_transaction_d)
             -----------1-----------    ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       444
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T4,T5

 LINE       529
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T4,T5

 LINE       635
 EXPRESSION (nack_timeout_en_i && (stretch_active_cnt >= nack_timeout_i))
             --------1--------    -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       644
 EXPRESSION (((~tx_fifo_rvalid_i)) | (acq_fifo_depth_i > 9'(1'b1)))
             ----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3

 LINE       697
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T4,T5

 LINE       716
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T4,T5

 LINE       764
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T4,T5

 LINE       812
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T4,T5

 LINE       838
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T4,T5

 LINE       855
 EXPRESSION (rw_bit_q ? StretchTx : AcquireByte)
             ----1---

-1-	Status	Tests
0	Covered	T19,T20,T21
1	Not Covered

 LINE       881
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       901
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T19,T20,T21
1	Covered	T19,T20,T21

 LINE       918
 EXPRESSION (((!target_idle)) && ((!target_enable_i)))
             --------1-------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Not Covered

 LINE       938
 EXPRESSION (target_enable_i && ((!target_idle)) && (stop_det | start_det))
             -------1-------    --------2-------    -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T1,T4,T5
1	1	1	Covered	T1,T4,T5

 LINE       938
 SUB-EXPRESSION (stop_det | start_det)
                 ----1---   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5

 LINE       962
 EXPRESSION (((!target_idle_o)) & (stretch_idle_cnt > host_timeout_i))
             ---------1--------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T4,T11,T12

---

FSM Coverage for Module : i2c_target_fsm

Summary for FSM :: state_q

	Total	Covered	Percent
States	24	24	100.00	(Not included in score)
Transitions	82	73	89.02
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AcquireAckHold	831	Covered	T1,T4,T5
AcquireAckPulse	826	Covered	T1,T4,T5
AcquireAckSetup	820	Covered	T1,T4,T5
AcquireAckWait	802	Covered	T1,T4,T5
AcquireByte	738	Covered	T1,T4,T5
AcquireStart	929	Covered	T1,T4,T5
AddrAckHold	709	Covered	T1,T4,T5
AddrAckPulse	704	Covered	T1,T4,T5
AddrAckSetup	699	Covered	T1,T4,T5
AddrAckWait	682	Covered	T1,T4,T5
AddrRead	672	Covered	T1,T4,T5
Idle	927	Covered	T1,T2,T3
StretchAcqFull	818	Covered	T19,T20,T21
StretchAcqSetup	893	Covered	T19,T20,T21
StretchAddr	732	Covered	T19,T20,T21
StretchTx	745	Covered	T1,T4,T5
StretchTxSetup	871	Covered	T1,T4,T5
TransmitAck	766	Covered	T1,T4,T5
TransmitAckPulse	777	Covered	T1,T4,T5
TransmitHold	757	Covered	T1,T4,T5
TransmitPulse	752	Covered	T1,T4,T5
TransmitSetup	747	Covered	T1,T4,T5
TransmitWait	735	Covered	T1,T4,T5
WaitForStop	688	Covered	T1,T4,T5

transitions	Line No.	Covered	Tests
AcquireAckHold->AcquireByte	839	Covered	T1,T4,T5
AcquireAckHold->AcquireStart	929	Covered	T14,T22
AcquireAckHold->Idle	927	Covered	T14,T22
AcquireAckPulse->AcquireAckHold	831	Covered	T1,T4,T5
AcquireAckPulse->AcquireStart	929	Covered	T14,T22
AcquireAckPulse->Idle	927	Covered	T14,T22
AcquireAckSetup->AcquireAckPulse	826	Covered	T1,T4,T5
AcquireAckSetup->AcquireStart	929	Covered	T14,T22
AcquireAckSetup->Idle	927	Covered	T14,T22
AcquireAckWait->AcquireAckSetup	820	Covered	T1,T4,T5
AcquireAckWait->AcquireStart	929	Covered	T14,T22
AcquireAckWait->Idle	927	Covered	T14,T22
AcquireAckWait->StretchAcqFull	818	Covered	T19,T20,T21
AcquireAckWait->WaitForStop	811	Not Covered
AcquireByte->AcquireAckWait	802	Covered	T1,T4,T5
AcquireByte->AcquireStart	929	Covered	T1,T4,T5
AcquireByte->Idle	927	Covered	T1,T4,T5
AcquireStart->AddrRead	672	Covered	T1,T4,T5
AcquireStart->Idle	927	Covered	T14,T22
AddrAckHold->AcquireByte	738	Covered	T1,T4,T5
AddrAckHold->AcquireStart	929	Covered	T14,T22
AddrAckHold->Idle	927	Covered	T14,T22
AddrAckHold->StretchAddr	732	Covered	T19,T20,T21
AddrAckHold->TransmitWait	735	Covered	T1,T4,T5
AddrAckHold->WaitForStop	728	Not Covered
AddrAckPulse->AcquireStart	929	Covered	T14,T22
AddrAckPulse->AddrAckHold	709	Covered	T1,T4,T5
AddrAckPulse->Idle	927	Covered	T14,T22
AddrAckSetup->AcquireStart	929	Covered	T14,T22
AddrAckSetup->AddrAckPulse	704	Covered	T1,T4,T5
AddrAckSetup->Idle	927	Covered	T14,T22
AddrAckWait->AcquireStart	929	Covered	T14,T22
AddrAckWait->AddrAckSetup	699	Covered	T1,T4,T5
AddrAckWait->Idle	927	Covered	T14,T22
AddrAckWait->WaitForStop	696	Not Covered
AddrRead->AcquireStart	929	Covered	T23,T24,T14
AddrRead->AddrAckWait	682	Covered	T1,T4,T5
AddrRead->Idle	927	Covered	T25,T26,T27
AddrRead->WaitForStop	688	Covered	T28,T29,T30
Idle->AcquireStart	929	Covered	T1,T4,T5
StretchAcqFull->AcquireStart	929	Covered	T14,T22
StretchAcqFull->Idle	927	Covered	T14,T22
StretchAcqFull->StretchAcqSetup	893	Covered	T19,T20,T21
StretchAcqFull->WaitForStop	891	Not Covered
StretchAcqSetup->AcquireAckSetup	902	Covered	T19,T20,T21
StretchAcqSetup->AcquireStart	929	Not Covered
StretchAcqSetup->Idle	927	Not Covered
StretchAddr->AcquireByte	855	Covered	T19,T20,T21
StretchAddr->AcquireStart	929	Covered	T14,T22
StretchAddr->Idle	927	Covered	T14,T22
StretchAddr->StretchTx	855	Not Covered
StretchAddr->WaitForStop	848	Not Covered
StretchTx->AcquireStart	929	Covered	T14,T22
StretchTx->Idle	927	Covered	T14,T22
StretchTx->StretchTxSetup	871	Covered	T1,T4,T5
StretchTx->WaitForStop	863	Not Covered
StretchTxSetup->AcquireStart	929	Covered	T14,T22
StretchTxSetup->Idle	927	Covered	T14,T22
StretchTxSetup->TransmitSetup	882	Covered	T1,T4,T5
TransmitAck->AcquireStart	929	Covered	T14,T22
TransmitAck->Idle	927	Covered	T14,T22
TransmitAck->TransmitAckPulse	777	Covered	T1,T4,T5
TransmitAckPulse->AcquireStart	929	Covered	T14,T22
TransmitAckPulse->Idle	927	Covered	T14,T22
TransmitAckPulse->TransmitWait	786	Covered	T1,T4,T5
TransmitAckPulse->WaitForStop	789	Covered	T1,T4,T5
TransmitHold->AcquireStart	929	Covered	T14,T22
TransmitHold->Idle	927	Covered	T14,T22
TransmitHold->TransmitAck	766	Covered	T1,T4,T5
TransmitHold->TransmitSetup	770	Covered	T1,T4,T5
TransmitPulse->AcquireStart	929	Covered	T16,T17,T18
TransmitPulse->Idle	927	Covered	T16,T17,T18
TransmitPulse->TransmitHold	757	Covered	T1,T4,T5
TransmitSetup->AcquireStart	929	Covered	T14,T22
TransmitSetup->Idle	927	Covered	T14,T22
TransmitSetup->TransmitPulse	752	Covered	T1,T4,T5
TransmitWait->AcquireStart	929	Covered	T14,T22
TransmitWait->Idle	927	Covered	T14,T22
TransmitWait->StretchTx	745	Covered	T1,T4,T5
TransmitWait->TransmitSetup	747	Covered	T1,T4,T5
WaitForStop->AcquireStart	929	Covered	T1,T4,T5
WaitForStop->Idle	927	Covered	T1,T4,T5

---

Branch Coverage for Module : i2c_target_fsm

	Line No.	Total	Covered	Percent
Branches		164	137	83.54
IF	119	6	4	66.67
IF	132	2	2	100.00
IF	145	4	4	100.00
IF	160	3	3	100.00
IF	171	2	2	100.00
IF	180	2	2	100.00
IF	191	2	2	100.00
IF	215	4	4	100.00
IF	225	4	4	100.00
IF	235	4	4	100.00
IF	257	5	5	100.00
IF	278	5	5	100.00
IF	289	4	4	100.00
IF	341	3	3	100.00
CASE	384	41	32	78.05
IF	612	4	3	75.00
CASE	659	61	47	77.05
IF	918	4	3	75.00
IF	942	2	2	100.00
IF	951	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	119	if (load_tcount)
-2-:	120	case (tcount_sel)
-3-:	126	if (target_enable_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	tSetupData	-	Covered	T1,T4,T5
1	tHoldData	-	Covered	T1,T4,T5
1	tNoDelay	-	Not Covered
1	default	-	Not Covered
0	-	1	Covered	T1,T4,T5
0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	132	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	145	if ((!rst_ni))
-2-:	147	if (((!target_idle_o) && event_host_timeout_o))
-3-:	150	if (((!target_idle_o) && scl_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T11,T12
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	160	if ((!rst_ni))
-2-:	162	if (actively_stretching)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	171	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	180	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	215	if ((!rst_ni))
-2-:	217	if ((start_det_trigger || stop_det_trigger))
-3-:	219	if ((start_det_pending || stop_det_pending))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	225	if ((!rst_ni))
-2-:	227	if (start_det_trigger)
-3-:	229	if (((((!target_enable_i) || (!scl_i)) || start_det) || stop_det_trigger))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	235	if ((!rst_ni))
-2-:	237	if (stop_det_trigger)
-3-:	239	if (((((!target_enable_i) || (!scl_i)) || stop_det) || start_det_trigger))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	257	if ((!rst_ni))
-2-:	259	if (start_det)
-3-:	261	if ((scl_i_q && (!scl_i)))
-4-:	264	if ((input_byte_clr || bit_ack))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T4,T5
0	0	1	1	Covered	T1,T2,T3
0	0	1	0	Covered	T1,T2,T3
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	278	if ((!rst_ni))
-2-:	280	if (input_byte_clr)
-3-:	282	if (((!scl_i_q) && scl_i))
-4-:	283	if ((!bit_ack))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T4,T5
0	0	1	1	Covered	T1,T2,T3
0	0	1	0	Covered	T1,T2,T3
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	289	if ((!rst_ni))
-2-:	291	if (((!scl_i_q) && scl_i))
-3-:	292	if (bit_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	341	if ((!rst_ni))
-2-:	343	if ((bit_ack && address_match))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	384	case (state_q)
-2-:	411	if (bit_ack)
-3-:	412	if (address_match)
-4-:	422	if (scl_i)
-5-:	444	if ((tcount_q == 20'b1))
-6-:	445	if (nack_transaction_q)
-7-:	449	if ((!stretch_addr))
-8-:	454	if (restart_det_q)
-9-:	490	if ((!scl_i))
-10-:	508	if (scl_i)
-11-:	529	if ((tcount_q == 20'b1))
-12-:	541	if (nack_timeout)
-13-:	548	if ((!stretch_addr))
-14-:	550	if (restart_det_q)
-15-:	563	if (nack_timeout)
-16-:	582	if (nack_timeout)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
Idle	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
AcquireStart	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
AddrRead	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
AddrRead	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T28,T29,T30
AddrRead	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
AddrAckWait	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
AddrAckWait	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
AddrAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
AddrAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
AddrAckHold	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	Not Covered
AddrAckHold	-	-	-	1	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
AddrAckHold	-	-	-	1	0	0	-	-	-	-	-	-	-	-	-	Covered	T19,T20,T21
AddrAckHold	-	-	-	1	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
AddrAckHold	-	-	-	1	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
AddrAckHold	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
TransmitWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
TransmitSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
TransmitPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
TransmitHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
TransmitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
TransmitAckPulse	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T1,T4,T5
TransmitAckPulse	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T4,T5
WaitForStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
AcquireByte	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
AcquireAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Not Covered
AcquireAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T1,T4,T5
AcquireAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
AcquireAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
AcquireAckHold	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T4,T5
AcquireAckHold	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Not Covered
StretchAddr	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Not Covered
StretchAddr	-	-	-	-	-	-	-	-	-	-	0	1	1	-	-	Covered	T19,T20,T21
StretchAddr	-	-	-	-	-	-	-	-	-	-	0	1	0	-	-	Covered	T19,T20,T31
StretchAddr	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T19,T20,T21
StretchTx	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Not Covered
StretchTx	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T4,T5
StretchTxSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
StretchAcqFull	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Not Covered
StretchAcqFull	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T19,T20,T21
StretchAcqSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T20,T21
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	612	if (stop_det)
-2-:	619	if (nack_transaction_q)
-3-:	624	if (start_det)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Not Covered
1	0	-	Covered	T1,T4,T5
0	-	1	Covered	T1,T4,T5
0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	659	case (state_q)
-2-:	671	if ((!scl_i))
-3-:	680	if (bit_ack)
-4-:	681	if (address_match)
-5-:	694	if (scl_i)
-6-:	697	if ((tcount_q == 20'b1))
-7-:	704	if (scl_i)
-8-:	708	if ((!scl_i))
-9-:	716	if ((tcount_q == 20'b1))
-10-:	722	if (nack_transaction_q)
-11-:	729	if (stretch_addr)
-12-:	733	if (rw_bit_q)
-13-:	744	if (stretch_tx)
-14-:	752	if (scl_i)
-15-:	756	if ((!scl_i))
-16-:	764	if ((tcount_q == 20'b1))
-17-:	765	if (bit_ack)
-18-:	776	if (scl_i)
-19-:	783	if ((!scl_i))
-20-:	785	if (host_ack)
-21-:	801	if (bit_ack)
-22-:	809	if (scl_i)
-23-:	812	if ((tcount_q == 20'b1))
-24-:	813	if (nack_transaction_q)
-25-:	815	if (stretch_rx)
-26-:	826	if (scl_i)
-27-:	830	if ((!scl_i))
-28-:	838	if ((tcount_q == 20'b1))
-29-:	847	if (nack_timeout)
-30-:	849	if ((!stretch_addr))
-31-:	855	(rw_bit_q) ? 
-32-:	862	if (nack_timeout)
-33-:	864	if ((!stretch_tx))
-34-:	881	if ((tcount_q == 20'b1))
-35-:	890	if (nack_timeout)
-36-:	892	if ((~stretch_rx))
-37-:	901	if ((tcount_q == 20'b1))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	-29-	-30-	-31-	-32-	-33-	-34-	-35-	-36-	-37-	Status	Tests
Idle	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
AcquireStart	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
AcquireStart	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
AddrRead	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
AddrRead	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T28,T29,T30
AddrRead	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
AddrAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
AddrAckWait	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
AddrAckWait	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
AddrAckSetup	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
AddrAckSetup	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
AddrAckPulse	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
AddrAckPulse	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
AddrAckHold	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
AddrAckHold	-	-	-	-	-	-	-	1	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T20,T21
AddrAckHold	-	-	-	-	-	-	-	1	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
AddrAckHold	-	-	-	-	-	-	-	1	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
AddrAckHold	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
TransmitWait	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
TransmitWait	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
TransmitSetup	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
TransmitSetup	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
TransmitPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
TransmitPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
TransmitHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
TransmitHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
TransmitHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
TransmitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
TransmitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
TransmitAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
TransmitAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
TransmitAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
WaitForStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
AcquireByte	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
AcquireByte	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
AcquireAckWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
AcquireAckWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
AcquireAckWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T20,T21
AcquireAckWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
AcquireAckWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
AcquireAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
AcquireAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
AcquireAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
AcquireAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
AcquireAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
AcquireAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Not Covered
StretchAddr	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Not Covered
StretchAddr	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	1	-	-	-	-	-	-	Not Covered
StretchAddr	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	0	-	-	-	-	-	-	Covered	T19,T20,T21
StretchAddr	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T19,T20,T21
StretchTx	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Not Covered
StretchTx	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	Covered	T1,T4,T5
StretchTx	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	Covered	T1,T4,T5
StretchTxSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T1,T4,T5
StretchTxSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Covered	T1,T4,T5
StretchAcqFull	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Not Covered
StretchAcqFull	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T19,T20,T21
StretchAcqFull	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T19,T20,T21
StretchAcqSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T19,T20,T21
StretchAcqSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T19,T20,T21
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	918	if (((!target_idle) && (!target_enable_i)))
-2-:	928	if (start_det)
-3-:	930	if (stop_det)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	942	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	951	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : i2c_target_fsm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AcqDepthRdCheck_A	444141709	3697918	0	0
AcqFifoDeepEnough_A	444141709	443961323	0	0
SclOutputGlitch_A	444141709	52625	0	0

AcqDepthRdCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444141709	3697918	0	0
T1	89582	285	0	0
T2	22527	0	0	0
T3	46854	0	0	0
T4	140733	2773	0	0
T5	988588	29409	0	0
T6	147805	0	0	0
T7	89517	634	0	0
T8	123844	0	0	0
T9	231932	0	0	0
T10	28920	0	0	0
T28	0	316	0	0
T32	0	14493	0	0
T33	0	41	0	0
T34	0	19368	0	0
T35	0	136	0	0
T36	0	202	0	0

AcqFifoDeepEnough_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444141709	443961323	0	0
T1	89582	89510	0	0
T2	22527	22452	0	0
T3	46854	46763	0	0
T4	140733	140658	0	0
T5	988588	988514	0	0
T6	147805	147691	0	0
T7	89517	89452	0	0
T8	123844	123783	0	0
T9	231932	231792	0	0
T10	28920	28844	0	0

SclOutputGlitch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444141709	52625	0	0
T1	89582	29	0	0
T2	22527	0	0	0
T3	46854	0	0	0
T4	140733	57	0	0
T5	988588	207	0	0
T6	147805	0	0	0
T7	89517	0	0	0
T8	123844	0	0	0
T9	231932	0	0	0
T10	28920	0	0	0
T19	0	151	0	0
T23	0	14	0	0
T28	0	20	0	0
T32	0	67	0	0
T33	0	11	0	0
T34	0	58	0	0
T37	0	146	0	0