Unified Coverage Report :: Group :: i2c_env_pkg::i2c_interrupts_cg

Group : i2c_env_pkg::i2c_interrupts_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.interrupts_cg	100.00	1	100	1	64	64

---

Group Instance : i2c_env_pkg.interrupts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.interrupts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	0	45	100.00

Variables for Group Instance i2c_env_pkg.interrupts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_acq_stretch	2	0	2	100.00	100	1	1	2
cp_acq_stretch_test	1	0	1	100.00	100	1	1	2
cp_acq_threshold	2	0	2	100.00	100	1	1	2
cp_acq_threshold_test	1	0	1	100.00	100	1	1	2
cp_cmd_complete	2	0	2	100.00	100	1	1	2
cp_cmd_complete_test	1	0	1	100.00	100	1	1	2
cp_fmt_threshold	2	0	2	100.00	100	1	1	2
cp_fmt_threshold_test	1	0	1	100.00	100	1	1	2
cp_host_timeout	2	0	2	100.00	100	1	1	2
cp_host_timeout_test	1	0	1	100.00	100	1	1	2
cp_nak	2	0	2	100.00	100	1	1	2
cp_nak_test	1	0	1	100.00	100	1	1	2
cp_rx_overflow	2	0	2	100.00	100	1	1	2
cp_rx_overflow_test	1	0	1	100.00	100	1	1	2
cp_rx_threshold	2	0	2	100.00	100	1	1	2
cp_rx_threshold_test	1	0	1	100.00	100	1	1	2
cp_scl_interference	2	0	2	100.00	100	1	1	2
cp_scl_interference_test	1	0	1	100.00	100	1	1	2
cp_sda_interference	2	0	2	100.00	100	1	1	2
cp_sda_interference_test	1	0	1	100.00	100	1	1	2
cp_sda_unstable	2	0	2	100.00	100	1	1	2
cp_sda_unstable_test	1	0	1	100.00	100	1	1	2
cp_stretch_timeout	2	0	2	100.00	100	1	1	2
cp_stretch_timeout_test	1	0	1	100.00	100	1	1	2
cp_tx_stretch	2	0	2	100.00	100	1	1	2
cp_tx_stretch_test	1	0	1	100.00	100	1	1	2
cp_tx_threshold	2	0	2	100.00	100	1	1	2
cp_tx_threshold_test	1	0	1	100.00	100	1	1	2
cp_unexp_stop	2	0	2	100.00	100	1	1	2
cp_unexp_stop_test	1	0	1	100.00	100	1	1	2

Summary for Variable cp_acq_stretch

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_acq_stretch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

345

1

T1

8

T3

4

T7

11

auto[1]

308

1

T1

1

T3

15

T7

8

---

Summary for Variable cp_acq_stretch_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_acq_stretch_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

176

1

T1

2

T3

7

T7

5

---

Summary for Variable cp_acq_threshold

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_acq_threshold

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

353

1

T1

3

T3

10

T7

1

auto[1]

321

1

T1

6

T3

9

T7

3

---

Summary for Variable cp_acq_threshold_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_acq_threshold_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

180

1

T1

3

T3

6

T7

7

---

Summary for Variable cp_cmd_complete

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_cmd_complete

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

361

1

T1

1

T3

7

T7

10

auto[1]

339

1

T1

2

T3

11

T7

6

---

Summary for Variable cp_cmd_complete_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_cmd_complete_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

178

1

T1

3

T3

4

T7

1

---

Summary for Variable cp_fmt_threshold

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_fmt_threshold

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

351

1

T1

10

T3

10

T7

6

auto[1]

350

1

T1

5

T3

4

T7

7

---

Summary for Variable cp_fmt_threshold_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_fmt_threshold_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

189

1

T1

1

T3

1

T7

4

---

Summary for Variable cp_host_timeout

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_host_timeout

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299

1

T1

5

T3

8

T7

16

auto[1]

393

1

T1

8

T3

6

T7

11

---

Summary for Variable cp_host_timeout_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_host_timeout_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

196

1

T1

2

T3

5

T7

2

---

Summary for Variable cp_nak

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nak

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

334

1

T1

7

T3

5

T7

6

auto[1]

295

1

T1

3

T3

4

T7

7

---

Summary for Variable cp_nak_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_nak_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

170

1

T1

2

T3

5

T7

4

---

Summary for Variable cp_rx_overflow

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rx_overflow

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

346

1

T1

3

T3

10

T7

10

auto[1]

339

1

T1

5

T3

10

T7

14

---

Summary for Variable cp_rx_overflow_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_rx_overflow_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

165

1

T1

4

T3

3

T7

4

---

Summary for Variable cp_rx_threshold

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rx_threshold

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

319

1

T1

4

T3

8

T7

10

auto[1]

306

1

T1

1

T3

3

T7

7

---

Summary for Variable cp_rx_threshold_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_rx_threshold_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

189

1

T1

3

T3

3

T7

5

---

Summary for Variable cp_scl_interference

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_scl_interference

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

290

1

T1

5

T3

8

T7

11

auto[1]

329

1

T1

7

T3

12

T7

13

---

Summary for Variable cp_scl_interference_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_scl_interference_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

191

1

T1

3

T3

5

T7

7

---

Summary for Variable cp_sda_interference

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sda_interference

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

306

1

T1

8

T3

12

T7

16

auto[1]

363

1

T1

2

T3

13

T7

4

---

Summary for Variable cp_sda_interference_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_sda_interference_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

185

1

T1

1

T3

3

T7

3

---

Summary for Variable cp_sda_unstable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sda_unstable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

389

1

T1

4

T3

12

T7

14

auto[1]

282

1

T1

4

T3

9

T7

6

---

Summary for Variable cp_sda_unstable_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_sda_unstable_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

164

1

T1

2

T3

6

T7

5

---

Summary for Variable cp_stretch_timeout

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stretch_timeout

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

319

1

T1

2

T3

7

T7

9

auto[1]

365

1

T1

5

T3

16

T7

1

---

Summary for Variable cp_stretch_timeout_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_stretch_timeout_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

175

1

T1

3

T3

4

T7

3

---

Summary for Variable cp_tx_stretch

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_tx_stretch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

345

1

T1

6

T3

9

T7

2

auto[1]

352

1

T1

4

T3

7

T7

10

---

Summary for Variable cp_tx_stretch_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_tx_stretch_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

196

1

T1

1

T3

4

T7

6

---

Summary for Variable cp_tx_threshold

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_tx_threshold

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

357

1

T1

5

T3

11

T7

10

auto[1]

278

1

T1

4

T3

17

T7

3

---

Summary for Variable cp_tx_threshold_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_tx_threshold_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

154

1

T1

3

T3

9

T7

2

---

Summary for Variable cp_unexp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_unexp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

321

1

T3

17

T7

4

T6

4

auto[1]

301

1

T1

1

T3

6

T7

14

---

Summary for Variable cp_unexp_stop_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_unexp_stop_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

166

1

T1

5

T3

2

T7

5