Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	19950	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

29656

1

T1

12

T2

562

T3

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	26101	1			T1	11		T2	863		T3	20
values[0x0]	11425	1			T1	6		T2	267		T3	8
values[0x1]	12080	1			T1	5		T2	300		T3	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13790	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

35816

1

T1

15

T2

872

T3

20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	186	1			T2	8		T3	1		T4	1
valid_sources[0x01]	183	1			T2	6		T20	3		T22	7
valid_sources[0x02]	339	1			T2	8		T4	3		T5	4
valid_sources[0x03]	254	1			T2	19		T4	1		T5	2
valid_sources[0x04]	165	1			T2	10		T4	1		T7	1
valid_sources[0x05]	174	1			T2	2		T4	1		T5	4
valid_sources[0x06]	177	1			T2	3		T5	2		T11	7
valid_sources[0x07]	285	1			T2	4		T4	1		T5	2
valid_sources[0x08]	192	1			T2	7		T4	1		T8	1
valid_sources[0x09]	184	1			T2	13		T5	5		T6	1
valid_sources[0x0a]	164	1			T5	2		T11	3		T12	1
valid_sources[0x0b]	195	1			T1	1		T2	6		T3	6
valid_sources[0x0c]	148	1			T2	4		T11	2		T12	1
valid_sources[0x0d]	232	1			T2	7		T4	2		T5	5
valid_sources[0x0e]	295	1			T2	7		T4	1		T5	3
valid_sources[0x0f]	212	1			T2	8		T5	6		T12	1
valid_sources[0x10]	104	1			T2	9		T4	1		T5	1
valid_sources[0x11]	174	1			T2	8		T5	1		T6	2
valid_sources[0x12]	161	1			T2	4		T5	2		T11	6
valid_sources[0x13]	318	1			T2	5		T4	2		T5	1
valid_sources[0x14]	313	1			T2	8		T4	1		T5	7
valid_sources[0x15]	310	1			T2	3		T5	10		T11	5
valid_sources[0x16]	210	1			T2	8		T5	3		T9	1
valid_sources[0x17]	165	1			T2	11		T4	1		T5	5
valid_sources[0x18]	160	1			T2	3		T4	1		T5	8
valid_sources[0x19]	122	1			T2	5		T5	8		T9	2
valid_sources[0x1a]	186	1			T2	16		T4	1		T5	6
valid_sources[0x1b]	173	1			T2	6		T4	1		T5	5
valid_sources[0x1c]	210	1			T1	1		T2	10		T5	2
valid_sources[0x1d]	141	1			T2	1		T4	2		T5	7
valid_sources[0x1e]	285	1			T2	4		T5	4		T12	4
valid_sources[0x1f]	185	1			T2	3		T4	1		T5	5
valid_sources[0x20]	156	1			T2	3		T5	1		T19	4
valid_sources[0x21]	166	1			T2	4		T4	1		T5	8
valid_sources[0x22]	159	1			T2	15		T5	6		T12	5
valid_sources[0x23]	174	1			T2	7		T5	5		T11	1
valid_sources[0x24]	286	1			T2	14		T8	4		T11	6
valid_sources[0x25]	277	1			T2	4		T5	7		T6	1
valid_sources[0x26]	202	1			T2	7		T5	7		T11	1
valid_sources[0x27]	170	1			T1	1		T2	1		T7	2
valid_sources[0x28]	205	1			T2	4		T4	2		T5	11
valid_sources[0x29]	212	1			T2	9		T4	1		T5	9
valid_sources[0x2a]	170	1			T2	10		T3	1		T4	1
valid_sources[0x2b]	202	1			T2	7		T5	5		T7	1
valid_sources[0x2c]	109	1			T2	5		T4	5		T5	2
valid_sources[0x2d]	212	1			T2	3		T4	2		T5	13
valid_sources[0x2e]	186	1			T2	6		T5	1		T8	1
valid_sources[0x2f]	178	1			T2	6		T5	2		T19	1
valid_sources[0x30]	160	1			T2	4		T3	1		T19	7
valid_sources[0x31]	151	1			T2	3		T4	1		T5	2
valid_sources[0x32]	163	1			T2	5		T4	1		T5	5
valid_sources[0x33]	177	1			T2	7		T4	1		T9	1
valid_sources[0x34]	179	1			T2	11		T4	1		T5	5
valid_sources[0x35]	235	1			T2	2		T4	2		T5	22
valid_sources[0x36]	184	1			T2	8		T5	3		T11	3
valid_sources[0x37]	148	1			T2	5		T5	4		T9	1
valid_sources[0x38]	135	1			T2	11		T5	8		T11	2
valid_sources[0x39]	175	1			T2	6		T4	2		T5	4
valid_sources[0x3a]	122	1			T2	3		T3	2		T5	6
valid_sources[0x3b]	146	1			T1	2		T2	2		T4	3
valid_sources[0x3c]	192	1			T2	5		T3	3		T5	3
valid_sources[0x3d]	281	1			T2	2		T4	1		T5	3
valid_sources[0x3e]	147	1			T2	5		T5	7		T19	5
valid_sources[0x3f]	179	1			T2	6		T5	18		T9	1
valid_sources[0x40]	249	1			T2	9		T3	2		T5	13
valid_sources[0x41]	132	1			T2	6		T4	1		T5	8
valid_sources[0x42]	190	1			T2	5		T5	10		T11	1
valid_sources[0x43]	506	1			T2	3		T4	2		T8	2
valid_sources[0x44]	177	1			T2	8		T4	1		T5	10
valid_sources[0x45]	188	1			T2	12		T5	3		T11	3
valid_sources[0x46]	157	1			T2	9		T11	3		T12	4
valid_sources[0x47]	285	1			T2	6		T4	1		T5	9
valid_sources[0x48]	166	1			T2	9		T5	5		T11	9
valid_sources[0x49]	258	1			T2	7		T4	1		T5	1
valid_sources[0x4a]	156	1			T2	2		T4	1		T5	5
valid_sources[0x4b]	164	1			T2	13		T4	2		T5	8
valid_sources[0x4c]	214	1			T2	3		T4	1		T9	1
valid_sources[0x4d]	152	1			T2	12		T4	1		T5	8
valid_sources[0x4e]	154	1			T2	1		T4	2		T5	2
valid_sources[0x4f]	174	1			T2	3		T4	2		T5	3
valid_sources[0x50]	179	1			T1	2		T2	4		T5	20
valid_sources[0x51]	129	1			T2	2		T4	6		T5	4
valid_sources[0x52]	176	1			T2	3		T4	2		T5	8
valid_sources[0x53]	151	1			T2	4		T4	2		T5	6
valid_sources[0x54]	198	1			T2	5		T5	10		T6	1
valid_sources[0x55]	189	1			T2	3		T4	1		T5	9
valid_sources[0x56]	217	1			T2	2		T4	3		T5	8
valid_sources[0x57]	161	1			T2	4		T4	1		T5	6
valid_sources[0x58]	116	1			T2	7		T5	3		T11	2
valid_sources[0x59]	155	1			T2	7		T4	3		T5	1
valid_sources[0x5a]	168	1			T2	3		T5	2		T7	1
valid_sources[0x5b]	157	1			T2	3		T4	1		T5	7
valid_sources[0x5c]	137	1			T2	12		T3	1		T5	4
valid_sources[0x5d]	193	1			T2	8		T4	1		T5	7
valid_sources[0x5e]	199	1			T2	2		T4	1		T5	5
valid_sources[0x5f]	188	1			T2	4		T5	1		T11	1
valid_sources[0x60]	291	1			T2	1		T5	8		T11	1
valid_sources[0x61]	166	1			T2	3		T4	1		T5	2
valid_sources[0x62]	243	1			T2	2		T5	2		T10	40
valid_sources[0x63]	326	1			T2	5		T5	7		T9	1
valid_sources[0x64]	171	1			T2	1		T5	11		T11	2
valid_sources[0x65]	198	1			T2	9		T5	11		T6	2
valid_sources[0x66]	155	1			T2	3		T4	1		T5	13
valid_sources[0x67]	139	1			T3	1		T4	1		T5	8
valid_sources[0x68]	180	1			T2	10		T5	1		T12	1
valid_sources[0x69]	143	1			T2	1		T5	7		T8	1
valid_sources[0x6a]	94	1			T2	6		T4	1		T5	5
valid_sources[0x6b]	224	1			T2	6		T4	2		T5	1
valid_sources[0x6c]	220	1			T2	6		T5	9		T11	1
valid_sources[0x6d]	227	1			T2	3		T4	2		T5	15
valid_sources[0x6e]	123	1			T2	1		T4	1		T5	5
valid_sources[0x6f]	136	1			T1	1		T2	3		T4	2
valid_sources[0x70]	148	1			T2	4		T4	1		T5	9
valid_sources[0x71]	156	1			T2	6		T5	3		T11	3
valid_sources[0x72]	156	1			T2	2		T5	7		T19	10
valid_sources[0x73]	177	1			T2	4		T5	3		T11	2
valid_sources[0x74]	192	1			T2	2		T4	1		T5	7
valid_sources[0x75]	190	1			T2	7		T4	2		T5	1
valid_sources[0x76]	139	1			T2	4		T11	2		T19	4
valid_sources[0x77]	157	1			T2	15		T5	7		T6	2
valid_sources[0x78]	163	1			T2	4		T4	2		T5	3
valid_sources[0x79]	170	1			T2	5		T5	1		T12	1
valid_sources[0x7a]	185	1			T2	4		T4	1		T5	15
valid_sources[0x7b]	184	1			T2	1		T5	4		T7	1
valid_sources[0x7c]	155	1			T2	8		T4	1		T5	3
valid_sources[0x7d]	349	1			T2	8		T5	2		T8	3
valid_sources[0x7e]	146	1			T2	4		T4	1		T5	8
valid_sources[0x7f]	185	1			T2	8		T3	2		T5	3
valid_sources[0x80]	236	1			T2	5		T4	1		T5	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

10898

1

T1

6

T2

141

T3

11

values[0x0]

all_enables

biggest_size

9611

1

T1

5

T2

200

T3

4

values[0x1]

all_enables

biggest_size

9147

1

T1

1

T2

221

T3

1